1 /* 2 * I2C adapter for the IMG Serial Control Bus (SCB) IP block. 3 * 4 * Copyright (C) 2009, 2010, 2012, 2014 Imagination Technologies Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * There are three ways that this I2C controller can be driven: 11 * 12 * - Raw control of the SDA and SCK signals. 13 * 14 * This corresponds to MODE_RAW, which takes control of the signals 15 * directly for a certain number of clock cycles (the INT_TIMING 16 * interrupt can be used for timing). 17 * 18 * - Atomic commands. A low level I2C symbol (such as generate 19 * start/stop/ack/nack bit, generate byte, receive byte, and receive 20 * ACK) is given to the hardware, with detection of completion by bits 21 * in the LINESTAT register. 22 * 23 * This mode of operation is used by MODE_ATOMIC, which uses an I2C 24 * state machine in the interrupt handler to compose/react to I2C 25 * transactions using atomic mode commands, and also by MODE_SEQUENCE, 26 * which emits a simple fixed sequence of atomic mode commands. 27 * 28 * Due to software control, the use of atomic commands usually results 29 * in suboptimal use of the bus, with gaps between the I2C symbols while 30 * the driver decides what to do next. 31 * 32 * - Automatic mode. A bus address, and whether to read/write is 33 * specified, and the hardware takes care of the I2C state machine, 34 * using a FIFO to send/receive bytes of data to an I2C slave. The 35 * driver just has to keep the FIFO drained or filled in response to the 36 * appropriate FIFO interrupts. 37 * 38 * This corresponds to MODE_AUTOMATIC, which manages the FIFOs and deals 39 * with control of repeated start bits between I2C messages. 40 * 41 * Use of automatic mode and the FIFO can make much more efficient use 42 * of the bus compared to individual atomic commands, with potentially 43 * no wasted time between I2C symbols or I2C messages. 44 * 45 * In most cases MODE_AUTOMATIC is used, however if any of the messages in 46 * a transaction are zero byte writes (e.g. used by i2cdetect for probing 47 * the bus), MODE_ATOMIC must be used since automatic mode is normally 48 * started by the writing of data into the FIFO. 49 * 50 * The other modes are used in specific circumstances where MODE_ATOMIC and 51 * MODE_AUTOMATIC aren't appropriate. MODE_RAW is used to implement a bus 52 * recovery routine. MODE_SEQUENCE is used to reset the bus and make sure 53 * it is in a sane state. 54 * 55 * Notice that the driver implements a timer-based timeout mechanism. 56 * The reason for this mechanism is to reduce the number of interrupts 57 * received in automatic mode. 58 * 59 * The driver would get a slave event and transaction done interrupts for 60 * each atomic mode command that gets completed. However, these events are 61 * not needed in automatic mode, becase those atomic mode commands are 62 * managed automatically by the hardware. 63 * 64 * In practice, normal I2C transactions will be complete well before you 65 * get the timer interrupt, as the timer is re-scheduled during FIFO 66 * maintenance and disabled after the transaction is complete. 67 * 68 * In this way normal automatic mode operation isn't impacted by 69 * unnecessary interrupts, but the exceptional abort condition can still be 70 * detected (with a slight delay). 71 */ 72 73 #include <linux/bitops.h> 74 #include <linux/clk.h> 75 #include <linux/completion.h> 76 #include <linux/err.h> 77 #include <linux/i2c.h> 78 #include <linux/init.h> 79 #include <linux/interrupt.h> 80 #include <linux/io.h> 81 #include <linux/kernel.h> 82 #include <linux/module.h> 83 #include <linux/of_platform.h> 84 #include <linux/platform_device.h> 85 #include <linux/slab.h> 86 #include <linux/timer.h> 87 88 /* Register offsets */ 89 90 #define SCB_STATUS_REG 0x00 91 #define SCB_OVERRIDE_REG 0x04 92 #define SCB_READ_ADDR_REG 0x08 93 #define SCB_READ_COUNT_REG 0x0c 94 #define SCB_WRITE_ADDR_REG 0x10 95 #define SCB_READ_DATA_REG 0x14 96 #define SCB_WRITE_DATA_REG 0x18 97 #define SCB_FIFO_STATUS_REG 0x1c 98 #define SCB_CONTROL_SOFT_RESET 0x1f 99 #define SCB_CLK_SET_REG 0x3c 100 #define SCB_INT_STATUS_REG 0x40 101 #define SCB_INT_CLEAR_REG 0x44 102 #define SCB_INT_MASK_REG 0x48 103 #define SCB_CONTROL_REG 0x4c 104 #define SCB_TIME_TPL_REG 0x50 105 #define SCB_TIME_TPH_REG 0x54 106 #define SCB_TIME_TP2S_REG 0x58 107 #define SCB_TIME_TBI_REG 0x60 108 #define SCB_TIME_TSL_REG 0x64 109 #define SCB_TIME_TDL_REG 0x68 110 #define SCB_TIME_TSDL_REG 0x6c 111 #define SCB_TIME_TSDH_REG 0x70 112 #define SCB_READ_XADDR_REG 0x74 113 #define SCB_WRITE_XADDR_REG 0x78 114 #define SCB_WRITE_COUNT_REG 0x7c 115 #define SCB_CORE_REV_REG 0x80 116 #define SCB_TIME_TCKH_REG 0x84 117 #define SCB_TIME_TCKL_REG 0x88 118 #define SCB_FIFO_FLUSH_REG 0x8c 119 #define SCB_READ_FIFO_REG 0x94 120 #define SCB_CLEAR_REG 0x98 121 122 /* SCB_CONTROL_REG bits */ 123 124 #define SCB_CONTROL_CLK_ENABLE 0x1e0 125 #define SCB_CONTROL_TRANSACTION_HALT 0x200 126 127 #define FIFO_READ_FULL BIT(0) 128 #define FIFO_READ_EMPTY BIT(1) 129 #define FIFO_WRITE_FULL BIT(2) 130 #define FIFO_WRITE_EMPTY BIT(3) 131 132 /* SCB_CLK_SET_REG bits */ 133 #define SCB_FILT_DISABLE BIT(31) 134 #define SCB_FILT_BYPASS BIT(30) 135 #define SCB_FILT_INC_MASK 0x7f 136 #define SCB_FILT_INC_SHIFT 16 137 #define SCB_INC_MASK 0x7f 138 #define SCB_INC_SHIFT 8 139 140 /* SCB_INT_*_REG bits */ 141 142 #define INT_BUS_INACTIVE BIT(0) 143 #define INT_UNEXPECTED_START BIT(1) 144 #define INT_SCLK_LOW_TIMEOUT BIT(2) 145 #define INT_SDAT_LOW_TIMEOUT BIT(3) 146 #define INT_WRITE_ACK_ERR BIT(4) 147 #define INT_ADDR_ACK_ERR BIT(5) 148 #define INT_FIFO_FULL BIT(9) 149 #define INT_FIFO_FILLING BIT(10) 150 #define INT_FIFO_EMPTY BIT(11) 151 #define INT_FIFO_EMPTYING BIT(12) 152 #define INT_TRANSACTION_DONE BIT(15) 153 #define INT_SLAVE_EVENT BIT(16) 154 #define INT_MASTER_HALTED BIT(17) 155 #define INT_TIMING BIT(18) 156 #define INT_STOP_DETECTED BIT(19) 157 158 #define INT_FIFO_FULL_FILLING (INT_FIFO_FULL | INT_FIFO_FILLING) 159 160 /* Level interrupts need clearing after handling instead of before */ 161 #define INT_LEVEL 0x01e00 162 163 /* Don't allow any interrupts while the clock may be off */ 164 #define INT_ENABLE_MASK_INACTIVE 0x00000 165 166 /* Interrupt masks for the different driver modes */ 167 168 #define INT_ENABLE_MASK_RAW INT_TIMING 169 170 #define INT_ENABLE_MASK_ATOMIC (INT_TRANSACTION_DONE | \ 171 INT_SLAVE_EVENT | \ 172 INT_ADDR_ACK_ERR | \ 173 INT_WRITE_ACK_ERR) 174 175 #define INT_ENABLE_MASK_AUTOMATIC (INT_SCLK_LOW_TIMEOUT | \ 176 INT_ADDR_ACK_ERR | \ 177 INT_WRITE_ACK_ERR | \ 178 INT_FIFO_FULL | \ 179 INT_FIFO_FILLING | \ 180 INT_FIFO_EMPTY | \ 181 INT_MASTER_HALTED | \ 182 INT_STOP_DETECTED) 183 184 #define INT_ENABLE_MASK_WAITSTOP (INT_SLAVE_EVENT | \ 185 INT_ADDR_ACK_ERR | \ 186 INT_WRITE_ACK_ERR) 187 188 /* SCB_STATUS_REG fields */ 189 190 #define LINESTAT_SCLK_LINE_STATUS BIT(0) 191 #define LINESTAT_SCLK_EN BIT(1) 192 #define LINESTAT_SDAT_LINE_STATUS BIT(2) 193 #define LINESTAT_SDAT_EN BIT(3) 194 #define LINESTAT_DET_START_STATUS BIT(4) 195 #define LINESTAT_DET_STOP_STATUS BIT(5) 196 #define LINESTAT_DET_ACK_STATUS BIT(6) 197 #define LINESTAT_DET_NACK_STATUS BIT(7) 198 #define LINESTAT_BUS_IDLE BIT(8) 199 #define LINESTAT_T_DONE_STATUS BIT(9) 200 #define LINESTAT_SCLK_OUT_STATUS BIT(10) 201 #define LINESTAT_SDAT_OUT_STATUS BIT(11) 202 #define LINESTAT_GEN_LINE_MASK_STATUS BIT(12) 203 #define LINESTAT_START_BIT_DET BIT(13) 204 #define LINESTAT_STOP_BIT_DET BIT(14) 205 #define LINESTAT_ACK_DET BIT(15) 206 #define LINESTAT_NACK_DET BIT(16) 207 #define LINESTAT_INPUT_HELD_V BIT(17) 208 #define LINESTAT_ABORT_DET BIT(18) 209 #define LINESTAT_ACK_OR_NACK_DET (LINESTAT_ACK_DET | LINESTAT_NACK_DET) 210 #define LINESTAT_INPUT_DATA 0xff000000 211 #define LINESTAT_INPUT_DATA_SHIFT 24 212 213 #define LINESTAT_CLEAR_SHIFT 13 214 #define LINESTAT_LATCHED (0x3f << LINESTAT_CLEAR_SHIFT) 215 216 /* SCB_OVERRIDE_REG fields */ 217 218 #define OVERRIDE_SCLK_OVR BIT(0) 219 #define OVERRIDE_SCLKEN_OVR BIT(1) 220 #define OVERRIDE_SDAT_OVR BIT(2) 221 #define OVERRIDE_SDATEN_OVR BIT(3) 222 #define OVERRIDE_MASTER BIT(9) 223 #define OVERRIDE_LINE_OVR_EN BIT(10) 224 #define OVERRIDE_DIRECT BIT(11) 225 #define OVERRIDE_CMD_SHIFT 4 226 #define OVERRIDE_CMD_MASK 0x1f 227 #define OVERRIDE_DATA_SHIFT 24 228 229 #define OVERRIDE_SCLK_DOWN (OVERRIDE_LINE_OVR_EN | \ 230 OVERRIDE_SCLKEN_OVR) 231 #define OVERRIDE_SCLK_UP (OVERRIDE_LINE_OVR_EN | \ 232 OVERRIDE_SCLKEN_OVR | \ 233 OVERRIDE_SCLK_OVR) 234 #define OVERRIDE_SDAT_DOWN (OVERRIDE_LINE_OVR_EN | \ 235 OVERRIDE_SDATEN_OVR) 236 #define OVERRIDE_SDAT_UP (OVERRIDE_LINE_OVR_EN | \ 237 OVERRIDE_SDATEN_OVR | \ 238 OVERRIDE_SDAT_OVR) 239 240 /* OVERRIDE_CMD values */ 241 242 #define CMD_PAUSE 0x00 243 #define CMD_GEN_DATA 0x01 244 #define CMD_GEN_START 0x02 245 #define CMD_GEN_STOP 0x03 246 #define CMD_GEN_ACK 0x04 247 #define CMD_GEN_NACK 0x05 248 #define CMD_RET_DATA 0x08 249 #define CMD_RET_ACK 0x09 250 251 /* Fixed timing values */ 252 253 #define TIMEOUT_TBI 0x0 254 #define TIMEOUT_TSL 0xffff 255 #define TIMEOUT_TDL 0x0 256 257 /* Transaction timeout */ 258 259 #define IMG_I2C_TIMEOUT (msecs_to_jiffies(1000)) 260 261 /* 262 * Worst incs are 1 (innacurate) and 16*256 (irregular). 263 * So a sensible inc is the logarithmic mean: 64 (2^6), which is 264 * in the middle of the valid range (0-127). 265 */ 266 #define SCB_OPT_INC 64 267 268 /* Setup the clock enable filtering for 25 ns */ 269 #define SCB_FILT_GLITCH 25 270 271 /* 272 * Bits to return from interrupt handler functions for different modes. 273 * This delays completion until we've finished with the registers, so that the 274 * function waiting for completion can safely disable the clock to save power. 275 */ 276 #define ISR_COMPLETE_M BIT(31) 277 #define ISR_FATAL_M BIT(30) 278 #define ISR_WAITSTOP BIT(29) 279 #define ISR_STATUS_M 0x0000ffff /* contains +ve errno */ 280 #define ISR_COMPLETE(err) (ISR_COMPLETE_M | (ISR_STATUS_M & (err))) 281 #define ISR_FATAL(err) (ISR_COMPLETE(err) | ISR_FATAL_M) 282 283 enum img_i2c_mode { 284 MODE_INACTIVE, 285 MODE_RAW, 286 MODE_ATOMIC, 287 MODE_AUTOMATIC, 288 MODE_SEQUENCE, 289 MODE_FATAL, 290 MODE_WAITSTOP, 291 MODE_SUSPEND, 292 }; 293 294 /* Timing parameters for i2c modes (in ns) */ 295 struct img_i2c_timings { 296 const char *name; 297 unsigned int max_bitrate; 298 unsigned int tckh, tckl, tsdh, tsdl; 299 unsigned int tp2s, tpl, tph; 300 }; 301 302 /* The timings array must be ordered from slower to faster */ 303 static struct img_i2c_timings timings[] = { 304 /* Standard mode */ 305 { 306 .name = "standard", 307 .max_bitrate = 100000, 308 .tckh = 4000, 309 .tckl = 4700, 310 .tsdh = 4700, 311 .tsdl = 8700, 312 .tp2s = 4700, 313 .tpl = 4700, 314 .tph = 4000, 315 }, 316 /* Fast mode */ 317 { 318 .name = "fast", 319 .max_bitrate = 400000, 320 .tckh = 600, 321 .tckl = 1300, 322 .tsdh = 600, 323 .tsdl = 1200, 324 .tp2s = 1300, 325 .tpl = 600, 326 .tph = 600, 327 }, 328 }; 329 330 /* Reset dance */ 331 static u8 img_i2c_reset_seq[] = { CMD_GEN_START, 332 CMD_GEN_DATA, 0xff, 333 CMD_RET_ACK, 334 CMD_GEN_START, 335 CMD_GEN_STOP, 336 0 }; 337 /* Just issue a stop (after an abort condition) */ 338 static u8 img_i2c_stop_seq[] = { CMD_GEN_STOP, 339 0 }; 340 341 /* We're interested in different interrupts depending on the mode */ 342 static unsigned int img_i2c_int_enable_by_mode[] = { 343 [MODE_INACTIVE] = INT_ENABLE_MASK_INACTIVE, 344 [MODE_RAW] = INT_ENABLE_MASK_RAW, 345 [MODE_ATOMIC] = INT_ENABLE_MASK_ATOMIC, 346 [MODE_AUTOMATIC] = INT_ENABLE_MASK_AUTOMATIC, 347 [MODE_SEQUENCE] = INT_ENABLE_MASK_ATOMIC, 348 [MODE_FATAL] = 0, 349 [MODE_WAITSTOP] = INT_ENABLE_MASK_WAITSTOP, 350 [MODE_SUSPEND] = 0, 351 }; 352 353 /* Atomic command names */ 354 static const char * const img_i2c_atomic_cmd_names[] = { 355 [CMD_PAUSE] = "PAUSE", 356 [CMD_GEN_DATA] = "GEN_DATA", 357 [CMD_GEN_START] = "GEN_START", 358 [CMD_GEN_STOP] = "GEN_STOP", 359 [CMD_GEN_ACK] = "GEN_ACK", 360 [CMD_GEN_NACK] = "GEN_NACK", 361 [CMD_RET_DATA] = "RET_DATA", 362 [CMD_RET_ACK] = "RET_ACK", 363 }; 364 365 struct img_i2c { 366 struct i2c_adapter adap; 367 368 void __iomem *base; 369 370 /* 371 * The scb core clock is used to get the input frequency, and to disable 372 * it after every set of transactions to save some power. 373 */ 374 struct clk *scb_clk, *sys_clk; 375 unsigned int bitrate; 376 bool need_wr_rd_fence; 377 378 /* state */ 379 struct completion msg_complete; 380 spinlock_t lock; /* lock before doing anything with the state */ 381 struct i2c_msg msg; 382 383 /* After the last transaction, wait for a stop bit */ 384 bool last_msg; 385 int msg_status; 386 387 enum img_i2c_mode mode; 388 u32 int_enable; /* depends on mode */ 389 u32 line_status; /* line status over command */ 390 391 /* 392 * To avoid slave event interrupts in automatic mode, use a timer to 393 * poll the abort condition if we don't get an interrupt for too long. 394 */ 395 struct timer_list check_timer; 396 bool t_halt; 397 398 /* atomic mode state */ 399 bool at_t_done; 400 bool at_slave_event; 401 int at_cur_cmd; 402 u8 at_cur_data; 403 404 /* Sequence: either reset or stop. See img_i2c_sequence. */ 405 u8 *seq; 406 407 /* raw mode */ 408 unsigned int raw_timeout; 409 }; 410 411 static void img_i2c_writel(struct img_i2c *i2c, u32 offset, u32 value) 412 { 413 writel(value, i2c->base + offset); 414 } 415 416 static u32 img_i2c_readl(struct img_i2c *i2c, u32 offset) 417 { 418 return readl(i2c->base + offset); 419 } 420 421 /* 422 * The code to read from the master read fifo, and write to the master 423 * write fifo, checks a bit in an SCB register before every byte to 424 * ensure that the fifo is not full (write fifo) or empty (read fifo). 425 * Due to clock domain crossing inside the SCB block the updated value 426 * of this bit is only visible after 2 cycles. 427 * 428 * The scb_wr_rd_fence() function does 2 dummy writes (to the read-only 429 * revision register), and it's called after reading from or writing to the 430 * fifos to ensure that subsequent reads of the fifo status bits do not read 431 * stale values. 432 */ 433 static void img_i2c_wr_rd_fence(struct img_i2c *i2c) 434 { 435 if (i2c->need_wr_rd_fence) { 436 img_i2c_writel(i2c, SCB_CORE_REV_REG, 0); 437 img_i2c_writel(i2c, SCB_CORE_REV_REG, 0); 438 } 439 } 440 441 static void img_i2c_switch_mode(struct img_i2c *i2c, enum img_i2c_mode mode) 442 { 443 i2c->mode = mode; 444 i2c->int_enable = img_i2c_int_enable_by_mode[mode]; 445 i2c->line_status = 0; 446 } 447 448 static void img_i2c_raw_op(struct img_i2c *i2c) 449 { 450 i2c->raw_timeout = 0; 451 img_i2c_writel(i2c, SCB_OVERRIDE_REG, 452 OVERRIDE_SCLKEN_OVR | 453 OVERRIDE_SDATEN_OVR | 454 OVERRIDE_MASTER | 455 OVERRIDE_LINE_OVR_EN | 456 OVERRIDE_DIRECT | 457 ((i2c->at_cur_cmd & OVERRIDE_CMD_MASK) << OVERRIDE_CMD_SHIFT) | 458 (i2c->at_cur_data << OVERRIDE_DATA_SHIFT)); 459 } 460 461 static const char *img_i2c_atomic_op_name(unsigned int cmd) 462 { 463 if (unlikely(cmd >= ARRAY_SIZE(img_i2c_atomic_cmd_names))) 464 return "UNKNOWN"; 465 return img_i2c_atomic_cmd_names[cmd]; 466 } 467 468 /* Send a single atomic mode command to the hardware */ 469 static void img_i2c_atomic_op(struct img_i2c *i2c, int cmd, u8 data) 470 { 471 i2c->at_cur_cmd = cmd; 472 i2c->at_cur_data = data; 473 474 /* work around lack of data setup time when generating data */ 475 if (cmd == CMD_GEN_DATA && i2c->mode == MODE_ATOMIC) { 476 u32 line_status = img_i2c_readl(i2c, SCB_STATUS_REG); 477 478 if (line_status & LINESTAT_SDAT_LINE_STATUS && !(data & 0x80)) { 479 /* hold the data line down for a moment */ 480 img_i2c_switch_mode(i2c, MODE_RAW); 481 img_i2c_raw_op(i2c); 482 return; 483 } 484 } 485 486 dev_dbg(i2c->adap.dev.parent, 487 "atomic cmd=%s (%d) data=%#x\n", 488 img_i2c_atomic_op_name(cmd), cmd, data); 489 i2c->at_t_done = (cmd == CMD_RET_DATA || cmd == CMD_RET_ACK); 490 i2c->at_slave_event = false; 491 i2c->line_status = 0; 492 493 img_i2c_writel(i2c, SCB_OVERRIDE_REG, 494 ((cmd & OVERRIDE_CMD_MASK) << OVERRIDE_CMD_SHIFT) | 495 OVERRIDE_MASTER | 496 OVERRIDE_DIRECT | 497 (data << OVERRIDE_DATA_SHIFT)); 498 } 499 500 /* Start a transaction in atomic mode */ 501 static void img_i2c_atomic_start(struct img_i2c *i2c) 502 { 503 img_i2c_switch_mode(i2c, MODE_ATOMIC); 504 img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable); 505 img_i2c_atomic_op(i2c, CMD_GEN_START, 0x00); 506 } 507 508 static void img_i2c_soft_reset(struct img_i2c *i2c) 509 { 510 i2c->t_halt = false; 511 img_i2c_writel(i2c, SCB_CONTROL_REG, 0); 512 img_i2c_writel(i2c, SCB_CONTROL_REG, 513 SCB_CONTROL_CLK_ENABLE | SCB_CONTROL_SOFT_RESET); 514 } 515 516 /* 517 * Enable or release transaction halt for control of repeated starts. 518 * In version 3.3 of the IP when transaction halt is set, an interrupt 519 * will be generated after each byte of a transfer instead of after 520 * every transfer but before the stop bit. 521 * Due to this behaviour we have to be careful that every time we 522 * release the transaction halt we have to re-enable it straight away 523 * so that we only process a single byte, not doing so will result in 524 * all remaining bytes been processed and a stop bit being issued, 525 * which will prevent us having a repeated start. 526 */ 527 static void img_i2c_transaction_halt(struct img_i2c *i2c, bool t_halt) 528 { 529 u32 val; 530 531 if (i2c->t_halt == t_halt) 532 return; 533 i2c->t_halt = t_halt; 534 val = img_i2c_readl(i2c, SCB_CONTROL_REG); 535 if (t_halt) 536 val |= SCB_CONTROL_TRANSACTION_HALT; 537 else 538 val &= ~SCB_CONTROL_TRANSACTION_HALT; 539 img_i2c_writel(i2c, SCB_CONTROL_REG, val); 540 } 541 542 /* Drain data from the FIFO into the buffer (automatic mode) */ 543 static void img_i2c_read_fifo(struct img_i2c *i2c) 544 { 545 while (i2c->msg.len) { 546 u32 fifo_status; 547 u8 data; 548 549 img_i2c_wr_rd_fence(i2c); 550 fifo_status = img_i2c_readl(i2c, SCB_FIFO_STATUS_REG); 551 if (fifo_status & FIFO_READ_EMPTY) 552 break; 553 554 data = img_i2c_readl(i2c, SCB_READ_DATA_REG); 555 *i2c->msg.buf = data; 556 557 img_i2c_writel(i2c, SCB_READ_FIFO_REG, 0xff); 558 i2c->msg.len--; 559 i2c->msg.buf++; 560 } 561 } 562 563 /* Fill the FIFO with data from the buffer (automatic mode) */ 564 static void img_i2c_write_fifo(struct img_i2c *i2c) 565 { 566 while (i2c->msg.len) { 567 u32 fifo_status; 568 569 img_i2c_wr_rd_fence(i2c); 570 fifo_status = img_i2c_readl(i2c, SCB_FIFO_STATUS_REG); 571 if (fifo_status & FIFO_WRITE_FULL) 572 break; 573 574 img_i2c_writel(i2c, SCB_WRITE_DATA_REG, *i2c->msg.buf); 575 i2c->msg.len--; 576 i2c->msg.buf++; 577 } 578 579 /* Disable fifo emptying interrupt if nothing more to write */ 580 if (!i2c->msg.len) 581 i2c->int_enable &= ~INT_FIFO_EMPTYING; 582 } 583 584 /* Start a read transaction in automatic mode */ 585 static void img_i2c_read(struct img_i2c *i2c) 586 { 587 img_i2c_switch_mode(i2c, MODE_AUTOMATIC); 588 if (!i2c->last_msg) 589 i2c->int_enable |= INT_SLAVE_EVENT; 590 591 img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable); 592 img_i2c_writel(i2c, SCB_READ_ADDR_REG, i2c->msg.addr); 593 img_i2c_writel(i2c, SCB_READ_COUNT_REG, i2c->msg.len); 594 595 mod_timer(&i2c->check_timer, jiffies + msecs_to_jiffies(1)); 596 } 597 598 /* Start a write transaction in automatic mode */ 599 static void img_i2c_write(struct img_i2c *i2c) 600 { 601 img_i2c_switch_mode(i2c, MODE_AUTOMATIC); 602 if (!i2c->last_msg) 603 i2c->int_enable |= INT_SLAVE_EVENT; 604 605 img_i2c_writel(i2c, SCB_WRITE_ADDR_REG, i2c->msg.addr); 606 img_i2c_writel(i2c, SCB_WRITE_COUNT_REG, i2c->msg.len); 607 608 mod_timer(&i2c->check_timer, jiffies + msecs_to_jiffies(1)); 609 img_i2c_write_fifo(i2c); 610 611 /* img_i2c_write_fifo() may modify int_enable */ 612 img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable); 613 } 614 615 /* 616 * Indicate that the transaction is complete. This is called from the 617 * ISR to wake up the waiting thread, after which the ISR must not 618 * access any more SCB registers. 619 */ 620 static void img_i2c_complete_transaction(struct img_i2c *i2c, int status) 621 { 622 img_i2c_switch_mode(i2c, MODE_INACTIVE); 623 if (status) { 624 i2c->msg_status = status; 625 img_i2c_transaction_halt(i2c, false); 626 } 627 complete(&i2c->msg_complete); 628 } 629 630 static unsigned int img_i2c_raw_atomic_delay_handler(struct img_i2c *i2c, 631 u32 int_status, u32 line_status) 632 { 633 /* Stay in raw mode for this, so we don't just loop infinitely */ 634 img_i2c_atomic_op(i2c, i2c->at_cur_cmd, i2c->at_cur_data); 635 img_i2c_switch_mode(i2c, MODE_ATOMIC); 636 return 0; 637 } 638 639 static unsigned int img_i2c_raw(struct img_i2c *i2c, u32 int_status, 640 u32 line_status) 641 { 642 if (int_status & INT_TIMING) { 643 if (i2c->raw_timeout == 0) 644 return img_i2c_raw_atomic_delay_handler(i2c, 645 int_status, line_status); 646 --i2c->raw_timeout; 647 } 648 return 0; 649 } 650 651 static unsigned int img_i2c_sequence(struct img_i2c *i2c, u32 int_status) 652 { 653 static const unsigned int continue_bits[] = { 654 [CMD_GEN_START] = LINESTAT_START_BIT_DET, 655 [CMD_GEN_DATA] = LINESTAT_INPUT_HELD_V, 656 [CMD_RET_ACK] = LINESTAT_ACK_DET | LINESTAT_NACK_DET, 657 [CMD_RET_DATA] = LINESTAT_INPUT_HELD_V, 658 [CMD_GEN_STOP] = LINESTAT_STOP_BIT_DET, 659 }; 660 int next_cmd = -1; 661 u8 next_data = 0x00; 662 663 if (int_status & INT_SLAVE_EVENT) 664 i2c->at_slave_event = true; 665 if (int_status & INT_TRANSACTION_DONE) 666 i2c->at_t_done = true; 667 668 if (!i2c->at_slave_event || !i2c->at_t_done) 669 return 0; 670 671 /* wait if no continue bits are set */ 672 if (i2c->at_cur_cmd >= 0 && 673 i2c->at_cur_cmd < ARRAY_SIZE(continue_bits)) { 674 unsigned int cont_bits = continue_bits[i2c->at_cur_cmd]; 675 676 if (cont_bits) { 677 cont_bits |= LINESTAT_ABORT_DET; 678 if (!(i2c->line_status & cont_bits)) 679 return 0; 680 } 681 } 682 683 /* follow the sequence of commands in i2c->seq */ 684 next_cmd = *i2c->seq; 685 /* stop on a nil */ 686 if (!next_cmd) { 687 img_i2c_writel(i2c, SCB_OVERRIDE_REG, 0); 688 return ISR_COMPLETE(0); 689 } 690 /* when generating data, the next byte is the data */ 691 if (next_cmd == CMD_GEN_DATA) { 692 ++i2c->seq; 693 next_data = *i2c->seq; 694 } 695 ++i2c->seq; 696 img_i2c_atomic_op(i2c, next_cmd, next_data); 697 698 return 0; 699 } 700 701 static void img_i2c_reset_start(struct img_i2c *i2c) 702 { 703 /* Initiate the magic dance */ 704 img_i2c_switch_mode(i2c, MODE_SEQUENCE); 705 img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable); 706 i2c->seq = img_i2c_reset_seq; 707 i2c->at_slave_event = true; 708 i2c->at_t_done = true; 709 i2c->at_cur_cmd = -1; 710 711 /* img_i2c_reset_seq isn't empty so the following won't fail */ 712 img_i2c_sequence(i2c, 0); 713 } 714 715 static void img_i2c_stop_start(struct img_i2c *i2c) 716 { 717 /* Initiate a stop bit sequence */ 718 img_i2c_switch_mode(i2c, MODE_SEQUENCE); 719 img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable); 720 i2c->seq = img_i2c_stop_seq; 721 i2c->at_slave_event = true; 722 i2c->at_t_done = true; 723 i2c->at_cur_cmd = -1; 724 725 /* img_i2c_stop_seq isn't empty so the following won't fail */ 726 img_i2c_sequence(i2c, 0); 727 } 728 729 static unsigned int img_i2c_atomic(struct img_i2c *i2c, 730 u32 int_status, 731 u32 line_status) 732 { 733 int next_cmd = -1; 734 u8 next_data = 0x00; 735 736 if (int_status & INT_SLAVE_EVENT) 737 i2c->at_slave_event = true; 738 if (int_status & INT_TRANSACTION_DONE) 739 i2c->at_t_done = true; 740 741 if (!i2c->at_slave_event || !i2c->at_t_done) 742 goto next_atomic_cmd; 743 if (i2c->line_status & LINESTAT_ABORT_DET) { 744 dev_dbg(i2c->adap.dev.parent, "abort condition detected\n"); 745 next_cmd = CMD_GEN_STOP; 746 i2c->msg_status = -EIO; 747 goto next_atomic_cmd; 748 } 749 750 /* i2c->at_cur_cmd may have completed */ 751 switch (i2c->at_cur_cmd) { 752 case CMD_GEN_START: 753 next_cmd = CMD_GEN_DATA; 754 next_data = i2c_8bit_addr_from_msg(&i2c->msg); 755 break; 756 case CMD_GEN_DATA: 757 if (i2c->line_status & LINESTAT_INPUT_HELD_V) 758 next_cmd = CMD_RET_ACK; 759 break; 760 case CMD_RET_ACK: 761 if (i2c->line_status & LINESTAT_ACK_DET || 762 (i2c->line_status & LINESTAT_NACK_DET && 763 i2c->msg.flags & I2C_M_IGNORE_NAK)) { 764 if (i2c->msg.len == 0) { 765 next_cmd = CMD_GEN_STOP; 766 } else if (i2c->msg.flags & I2C_M_RD) { 767 next_cmd = CMD_RET_DATA; 768 } else { 769 next_cmd = CMD_GEN_DATA; 770 next_data = *i2c->msg.buf; 771 --i2c->msg.len; 772 ++i2c->msg.buf; 773 } 774 } else if (i2c->line_status & LINESTAT_NACK_DET) { 775 i2c->msg_status = -EIO; 776 next_cmd = CMD_GEN_STOP; 777 } 778 break; 779 case CMD_RET_DATA: 780 if (i2c->line_status & LINESTAT_INPUT_HELD_V) { 781 *i2c->msg.buf = (i2c->line_status & 782 LINESTAT_INPUT_DATA) 783 >> LINESTAT_INPUT_DATA_SHIFT; 784 --i2c->msg.len; 785 ++i2c->msg.buf; 786 if (i2c->msg.len) 787 next_cmd = CMD_GEN_ACK; 788 else 789 next_cmd = CMD_GEN_NACK; 790 } 791 break; 792 case CMD_GEN_ACK: 793 if (i2c->line_status & LINESTAT_ACK_DET) { 794 next_cmd = CMD_RET_DATA; 795 } else { 796 i2c->msg_status = -EIO; 797 next_cmd = CMD_GEN_STOP; 798 } 799 break; 800 case CMD_GEN_NACK: 801 next_cmd = CMD_GEN_STOP; 802 break; 803 case CMD_GEN_STOP: 804 img_i2c_writel(i2c, SCB_OVERRIDE_REG, 0); 805 return ISR_COMPLETE(0); 806 default: 807 dev_err(i2c->adap.dev.parent, "bad atomic command %d\n", 808 i2c->at_cur_cmd); 809 i2c->msg_status = -EIO; 810 next_cmd = CMD_GEN_STOP; 811 break; 812 } 813 814 next_atomic_cmd: 815 if (next_cmd != -1) { 816 /* don't actually stop unless we're the last transaction */ 817 if (next_cmd == CMD_GEN_STOP && !i2c->msg_status && 818 !i2c->last_msg) 819 return ISR_COMPLETE(0); 820 img_i2c_atomic_op(i2c, next_cmd, next_data); 821 } 822 return 0; 823 } 824 825 /* 826 * Timer function to check if something has gone wrong in automatic mode (so we 827 * don't have to handle so many interrupts just to catch an exception). 828 */ 829 static void img_i2c_check_timer(unsigned long arg) 830 { 831 struct img_i2c *i2c = (struct img_i2c *)arg; 832 unsigned long flags; 833 unsigned int line_status; 834 835 spin_lock_irqsave(&i2c->lock, flags); 836 line_status = img_i2c_readl(i2c, SCB_STATUS_REG); 837 838 /* check for an abort condition */ 839 if (line_status & LINESTAT_ABORT_DET) { 840 dev_dbg(i2c->adap.dev.parent, 841 "abort condition detected by check timer\n"); 842 /* enable slave event interrupt mask to trigger irq */ 843 img_i2c_writel(i2c, SCB_INT_MASK_REG, 844 i2c->int_enable | INT_SLAVE_EVENT); 845 } 846 847 spin_unlock_irqrestore(&i2c->lock, flags); 848 } 849 850 static unsigned int img_i2c_auto(struct img_i2c *i2c, 851 unsigned int int_status, 852 unsigned int line_status) 853 { 854 if (int_status & (INT_WRITE_ACK_ERR | INT_ADDR_ACK_ERR)) 855 return ISR_COMPLETE(EIO); 856 857 if (line_status & LINESTAT_ABORT_DET) { 858 dev_dbg(i2c->adap.dev.parent, "abort condition detected\n"); 859 /* empty the read fifo */ 860 if ((i2c->msg.flags & I2C_M_RD) && 861 (int_status & INT_FIFO_FULL_FILLING)) 862 img_i2c_read_fifo(i2c); 863 /* use atomic mode and try to force a stop bit */ 864 i2c->msg_status = -EIO; 865 img_i2c_stop_start(i2c); 866 return 0; 867 } 868 869 /* Enable transaction halt on start bit */ 870 if (!i2c->last_msg && line_status & LINESTAT_START_BIT_DET) { 871 img_i2c_transaction_halt(i2c, !i2c->last_msg); 872 /* we're no longer interested in the slave event */ 873 i2c->int_enable &= ~INT_SLAVE_EVENT; 874 } 875 876 mod_timer(&i2c->check_timer, jiffies + msecs_to_jiffies(1)); 877 878 if (int_status & INT_STOP_DETECTED) { 879 /* Drain remaining data in FIFO and complete transaction */ 880 if (i2c->msg.flags & I2C_M_RD) 881 img_i2c_read_fifo(i2c); 882 return ISR_COMPLETE(0); 883 } 884 885 if (i2c->msg.flags & I2C_M_RD) { 886 if (int_status & (INT_FIFO_FULL_FILLING | INT_MASTER_HALTED)) { 887 img_i2c_read_fifo(i2c); 888 if (i2c->msg.len == 0) 889 return ISR_WAITSTOP; 890 } 891 } else { 892 if (int_status & (INT_FIFO_EMPTY | INT_MASTER_HALTED)) { 893 if ((int_status & INT_FIFO_EMPTY) && 894 i2c->msg.len == 0) 895 return ISR_WAITSTOP; 896 img_i2c_write_fifo(i2c); 897 } 898 } 899 if (int_status & INT_MASTER_HALTED) { 900 /* 901 * Release and then enable transaction halt, to 902 * allow only a single byte to proceed. 903 */ 904 img_i2c_transaction_halt(i2c, false); 905 img_i2c_transaction_halt(i2c, !i2c->last_msg); 906 } 907 908 return 0; 909 } 910 911 static irqreturn_t img_i2c_isr(int irq, void *dev_id) 912 { 913 struct img_i2c *i2c = (struct img_i2c *)dev_id; 914 u32 int_status, line_status; 915 /* We handle transaction completion AFTER accessing registers */ 916 unsigned int hret; 917 918 /* Read interrupt status register. */ 919 int_status = img_i2c_readl(i2c, SCB_INT_STATUS_REG); 920 /* Clear detected interrupts. */ 921 img_i2c_writel(i2c, SCB_INT_CLEAR_REG, int_status); 922 923 /* 924 * Read line status and clear it until it actually is clear. We have 925 * to be careful not to lose any line status bits that get latched. 926 */ 927 line_status = img_i2c_readl(i2c, SCB_STATUS_REG); 928 if (line_status & LINESTAT_LATCHED) { 929 img_i2c_writel(i2c, SCB_CLEAR_REG, 930 (line_status & LINESTAT_LATCHED) 931 >> LINESTAT_CLEAR_SHIFT); 932 img_i2c_wr_rd_fence(i2c); 933 } 934 935 spin_lock(&i2c->lock); 936 937 /* Keep track of line status bits received */ 938 i2c->line_status &= ~LINESTAT_INPUT_DATA; 939 i2c->line_status |= line_status; 940 941 /* 942 * Certain interrupts indicate that sclk low timeout is not 943 * a problem. If any of these are set, just continue. 944 */ 945 if ((int_status & INT_SCLK_LOW_TIMEOUT) && 946 !(int_status & (INT_SLAVE_EVENT | 947 INT_FIFO_EMPTY | 948 INT_FIFO_FULL))) { 949 dev_crit(i2c->adap.dev.parent, 950 "fatal: clock low timeout occurred %s addr 0x%02x\n", 951 (i2c->msg.flags & I2C_M_RD) ? "reading" : "writing", 952 i2c->msg.addr); 953 hret = ISR_FATAL(EIO); 954 goto out; 955 } 956 957 if (i2c->mode == MODE_ATOMIC) 958 hret = img_i2c_atomic(i2c, int_status, line_status); 959 else if (i2c->mode == MODE_AUTOMATIC) 960 hret = img_i2c_auto(i2c, int_status, line_status); 961 else if (i2c->mode == MODE_SEQUENCE) 962 hret = img_i2c_sequence(i2c, int_status); 963 else if (i2c->mode == MODE_WAITSTOP && (int_status & INT_SLAVE_EVENT) && 964 (line_status & LINESTAT_STOP_BIT_DET)) 965 hret = ISR_COMPLETE(0); 966 else if (i2c->mode == MODE_RAW) 967 hret = img_i2c_raw(i2c, int_status, line_status); 968 else 969 hret = 0; 970 971 /* Clear detected level interrupts. */ 972 img_i2c_writel(i2c, SCB_INT_CLEAR_REG, int_status & INT_LEVEL); 973 974 out: 975 if (hret & ISR_WAITSTOP) { 976 /* 977 * Only wait for stop on last message. 978 * Also we may already have detected the stop bit. 979 */ 980 if (!i2c->last_msg || i2c->line_status & LINESTAT_STOP_BIT_DET) 981 hret = ISR_COMPLETE(0); 982 else 983 img_i2c_switch_mode(i2c, MODE_WAITSTOP); 984 } 985 986 /* now we've finished using regs, handle transaction completion */ 987 if (hret & ISR_COMPLETE_M) { 988 int status = -(hret & ISR_STATUS_M); 989 990 img_i2c_complete_transaction(i2c, status); 991 if (hret & ISR_FATAL_M) 992 img_i2c_switch_mode(i2c, MODE_FATAL); 993 } 994 995 /* Enable interrupts (int_enable may be altered by changing mode) */ 996 img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable); 997 998 spin_unlock(&i2c->lock); 999 1000 return IRQ_HANDLED; 1001 } 1002 1003 /* Force a bus reset sequence and wait for it to complete */ 1004 static int img_i2c_reset_bus(struct img_i2c *i2c) 1005 { 1006 unsigned long flags; 1007 unsigned long time_left; 1008 1009 spin_lock_irqsave(&i2c->lock, flags); 1010 reinit_completion(&i2c->msg_complete); 1011 img_i2c_reset_start(i2c); 1012 spin_unlock_irqrestore(&i2c->lock, flags); 1013 1014 time_left = wait_for_completion_timeout(&i2c->msg_complete, 1015 IMG_I2C_TIMEOUT); 1016 if (time_left == 0) 1017 return -ETIMEDOUT; 1018 return 0; 1019 } 1020 1021 static int img_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, 1022 int num) 1023 { 1024 struct img_i2c *i2c = i2c_get_adapdata(adap); 1025 bool atomic = false; 1026 int i, ret; 1027 unsigned long time_left; 1028 1029 if (i2c->mode == MODE_SUSPEND) { 1030 WARN(1, "refusing to service transaction in suspended state\n"); 1031 return -EIO; 1032 } 1033 1034 if (i2c->mode == MODE_FATAL) 1035 return -EIO; 1036 1037 for (i = 0; i < num; i++) { 1038 /* 1039 * 0 byte reads are not possible because the slave could try 1040 * and pull the data line low, preventing a stop bit. 1041 */ 1042 if (!msgs[i].len && msgs[i].flags & I2C_M_RD) 1043 return -EIO; 1044 /* 1045 * 0 byte writes are possible and used for probing, but we 1046 * cannot do them in automatic mode, so use atomic mode 1047 * instead. 1048 * 1049 * Also, the I2C_M_IGNORE_NAK mode can only be implemented 1050 * in atomic mode. 1051 */ 1052 if (!msgs[i].len || 1053 (msgs[i].flags & I2C_M_IGNORE_NAK)) 1054 atomic = true; 1055 } 1056 1057 ret = clk_prepare_enable(i2c->scb_clk); 1058 if (ret) 1059 return ret; 1060 1061 for (i = 0; i < num; i++) { 1062 struct i2c_msg *msg = &msgs[i]; 1063 unsigned long flags; 1064 1065 spin_lock_irqsave(&i2c->lock, flags); 1066 1067 /* 1068 * Make a copy of the message struct. We mustn't modify the 1069 * original or we'll confuse drivers and i2c-dev. 1070 */ 1071 i2c->msg = *msg; 1072 i2c->msg_status = 0; 1073 1074 /* 1075 * After the last message we must have waited for a stop bit. 1076 * Not waiting can cause problems when the clock is disabled 1077 * before the stop bit is sent, and the linux I2C interface 1078 * requires separate transfers not to joined with repeated 1079 * start. 1080 */ 1081 i2c->last_msg = (i == num - 1); 1082 reinit_completion(&i2c->msg_complete); 1083 1084 /* 1085 * Clear line status and all interrupts before starting a 1086 * transfer, as we may have unserviced interrupts from 1087 * previous transfers that might be handled in the context 1088 * of the new transfer. 1089 */ 1090 img_i2c_writel(i2c, SCB_INT_CLEAR_REG, ~0); 1091 img_i2c_writel(i2c, SCB_CLEAR_REG, ~0); 1092 1093 if (atomic) { 1094 img_i2c_atomic_start(i2c); 1095 } else { 1096 /* 1097 * Enable transaction halt if not the last message in 1098 * the queue so that we can control repeated starts. 1099 */ 1100 img_i2c_transaction_halt(i2c, !i2c->last_msg); 1101 1102 if (msg->flags & I2C_M_RD) 1103 img_i2c_read(i2c); 1104 else 1105 img_i2c_write(i2c); 1106 1107 /* 1108 * Release and then enable transaction halt, to 1109 * allow only a single byte to proceed. 1110 * This doesn't have an effect on the initial transfer 1111 * but will allow the following transfers to start 1112 * processing if the previous transfer was marked as 1113 * complete while the i2c block was halted. 1114 */ 1115 img_i2c_transaction_halt(i2c, false); 1116 img_i2c_transaction_halt(i2c, !i2c->last_msg); 1117 } 1118 spin_unlock_irqrestore(&i2c->lock, flags); 1119 1120 time_left = wait_for_completion_timeout(&i2c->msg_complete, 1121 IMG_I2C_TIMEOUT); 1122 del_timer_sync(&i2c->check_timer); 1123 1124 if (time_left == 0) { 1125 dev_err(adap->dev.parent, "i2c transfer timed out\n"); 1126 i2c->msg_status = -ETIMEDOUT; 1127 break; 1128 } 1129 1130 if (i2c->msg_status) 1131 break; 1132 } 1133 1134 clk_disable_unprepare(i2c->scb_clk); 1135 1136 return i2c->msg_status ? i2c->msg_status : num; 1137 } 1138 1139 static u32 img_i2c_func(struct i2c_adapter *adap) 1140 { 1141 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 1142 } 1143 1144 static const struct i2c_algorithm img_i2c_algo = { 1145 .master_xfer = img_i2c_xfer, 1146 .functionality = img_i2c_func, 1147 }; 1148 1149 static int img_i2c_init(struct img_i2c *i2c) 1150 { 1151 unsigned int clk_khz, bitrate_khz, clk_period, tckh, tckl, tsdh; 1152 unsigned int i, ret, data, prescale, inc, int_bitrate, filt; 1153 struct img_i2c_timings timing; 1154 u32 rev; 1155 1156 ret = clk_prepare_enable(i2c->scb_clk); 1157 if (ret) 1158 return ret; 1159 1160 rev = img_i2c_readl(i2c, SCB_CORE_REV_REG); 1161 if ((rev & 0x00ffffff) < 0x00020200) { 1162 dev_info(i2c->adap.dev.parent, 1163 "Unknown hardware revision (%d.%d.%d.%d)\n", 1164 (rev >> 24) & 0xff, (rev >> 16) & 0xff, 1165 (rev >> 8) & 0xff, rev & 0xff); 1166 clk_disable_unprepare(i2c->scb_clk); 1167 return -EINVAL; 1168 } 1169 1170 /* Fencing enabled by default. */ 1171 i2c->need_wr_rd_fence = true; 1172 1173 /* Determine what mode we're in from the bitrate */ 1174 timing = timings[0]; 1175 for (i = 0; i < ARRAY_SIZE(timings); i++) { 1176 if (i2c->bitrate <= timings[i].max_bitrate) { 1177 timing = timings[i]; 1178 break; 1179 } 1180 } 1181 if (i2c->bitrate > timings[ARRAY_SIZE(timings) - 1].max_bitrate) { 1182 dev_warn(i2c->adap.dev.parent, 1183 "requested bitrate (%u) is higher than the max bitrate supported (%u)\n", 1184 i2c->bitrate, 1185 timings[ARRAY_SIZE(timings) - 1].max_bitrate); 1186 timing = timings[ARRAY_SIZE(timings) - 1]; 1187 i2c->bitrate = timing.max_bitrate; 1188 } 1189 1190 bitrate_khz = i2c->bitrate / 1000; 1191 clk_khz = clk_get_rate(i2c->scb_clk) / 1000; 1192 1193 /* Find the prescale that would give us that inc (approx delay = 0) */ 1194 prescale = SCB_OPT_INC * clk_khz / (256 * 16 * bitrate_khz); 1195 prescale = clamp_t(unsigned int, prescale, 1, 8); 1196 clk_khz /= prescale; 1197 1198 /* Setup the clock increment value */ 1199 inc = (256 * 16 * bitrate_khz) / clk_khz; 1200 1201 /* 1202 * The clock generation logic allows to filter glitches on the bus. 1203 * This filter is able to remove bus glitches shorter than 50ns. 1204 * If the clock enable rate is greater than 20 MHz, no filtering 1205 * is required, so we need to disable it. 1206 * If it's between the 20-40 MHz range, there's no need to divide 1207 * the clock to get a filter. 1208 */ 1209 if (clk_khz < 20000) { 1210 filt = SCB_FILT_DISABLE; 1211 } else if (clk_khz < 40000) { 1212 filt = SCB_FILT_BYPASS; 1213 } else { 1214 /* Calculate filter clock */ 1215 filt = (64000 / ((clk_khz / 1000) * SCB_FILT_GLITCH)); 1216 1217 /* Scale up if needed */ 1218 if (64000 % ((clk_khz / 1000) * SCB_FILT_GLITCH)) 1219 inc++; 1220 1221 if (filt > SCB_FILT_INC_MASK) 1222 filt = SCB_FILT_INC_MASK; 1223 1224 filt = (filt & SCB_FILT_INC_MASK) << SCB_FILT_INC_SHIFT; 1225 } 1226 data = filt | ((inc & SCB_INC_MASK) << SCB_INC_SHIFT) | (prescale - 1); 1227 img_i2c_writel(i2c, SCB_CLK_SET_REG, data); 1228 1229 /* Obtain the clock period of the fx16 clock in ns */ 1230 clk_period = (256 * 1000000) / (clk_khz * inc); 1231 1232 /* Calculate the bitrate in terms of internal clock pulses */ 1233 int_bitrate = 1000000 / (bitrate_khz * clk_period); 1234 if ((1000000 % (bitrate_khz * clk_period)) >= 1235 ((bitrate_khz * clk_period) / 2)) 1236 int_bitrate++; 1237 1238 /* 1239 * Setup clock duty cycle, start with 50% and adjust TCKH and TCKL 1240 * values from there if they don't meet minimum timing requirements 1241 */ 1242 tckh = int_bitrate / 2; 1243 tckl = int_bitrate - tckh; 1244 1245 /* Adjust TCKH and TCKL values */ 1246 data = DIV_ROUND_UP(timing.tckl, clk_period); 1247 1248 if (tckl < data) { 1249 tckl = data; 1250 tckh = int_bitrate - tckl; 1251 } 1252 1253 if (tckh > 0) 1254 --tckh; 1255 1256 if (tckl > 0) 1257 --tckl; 1258 1259 img_i2c_writel(i2c, SCB_TIME_TCKH_REG, tckh); 1260 img_i2c_writel(i2c, SCB_TIME_TCKL_REG, tckl); 1261 1262 /* Setup TSDH value */ 1263 tsdh = DIV_ROUND_UP(timing.tsdh, clk_period); 1264 1265 if (tsdh > 1) 1266 data = tsdh - 1; 1267 else 1268 data = 0x01; 1269 img_i2c_writel(i2c, SCB_TIME_TSDH_REG, data); 1270 1271 /* This value is used later */ 1272 tsdh = data; 1273 1274 /* Setup TPL value */ 1275 data = timing.tpl / clk_period; 1276 if (data > 0) 1277 --data; 1278 img_i2c_writel(i2c, SCB_TIME_TPL_REG, data); 1279 1280 /* Setup TPH value */ 1281 data = timing.tph / clk_period; 1282 if (data > 0) 1283 --data; 1284 img_i2c_writel(i2c, SCB_TIME_TPH_REG, data); 1285 1286 /* Setup TSDL value to TPL + TSDH + 2 */ 1287 img_i2c_writel(i2c, SCB_TIME_TSDL_REG, data + tsdh + 2); 1288 1289 /* Setup TP2S value */ 1290 data = timing.tp2s / clk_period; 1291 if (data > 0) 1292 --data; 1293 img_i2c_writel(i2c, SCB_TIME_TP2S_REG, data); 1294 1295 img_i2c_writel(i2c, SCB_TIME_TBI_REG, TIMEOUT_TBI); 1296 img_i2c_writel(i2c, SCB_TIME_TSL_REG, TIMEOUT_TSL); 1297 img_i2c_writel(i2c, SCB_TIME_TDL_REG, TIMEOUT_TDL); 1298 1299 /* Take module out of soft reset and enable clocks */ 1300 img_i2c_soft_reset(i2c); 1301 1302 /* Disable all interrupts */ 1303 img_i2c_writel(i2c, SCB_INT_MASK_REG, 0); 1304 1305 /* Clear all interrupts */ 1306 img_i2c_writel(i2c, SCB_INT_CLEAR_REG, ~0); 1307 1308 /* Clear the scb_line_status events */ 1309 img_i2c_writel(i2c, SCB_CLEAR_REG, ~0); 1310 1311 /* Enable interrupts */ 1312 img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable); 1313 1314 /* Perform a synchronous sequence to reset the bus */ 1315 ret = img_i2c_reset_bus(i2c); 1316 1317 clk_disable_unprepare(i2c->scb_clk); 1318 1319 return ret; 1320 } 1321 1322 static int img_i2c_probe(struct platform_device *pdev) 1323 { 1324 struct device_node *node = pdev->dev.of_node; 1325 struct img_i2c *i2c; 1326 struct resource *res; 1327 int irq, ret; 1328 u32 val; 1329 1330 i2c = devm_kzalloc(&pdev->dev, sizeof(struct img_i2c), GFP_KERNEL); 1331 if (!i2c) 1332 return -ENOMEM; 1333 1334 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1335 i2c->base = devm_ioremap_resource(&pdev->dev, res); 1336 if (IS_ERR(i2c->base)) 1337 return PTR_ERR(i2c->base); 1338 1339 irq = platform_get_irq(pdev, 0); 1340 if (irq < 0) { 1341 dev_err(&pdev->dev, "can't get irq number\n"); 1342 return irq; 1343 } 1344 1345 i2c->sys_clk = devm_clk_get(&pdev->dev, "sys"); 1346 if (IS_ERR(i2c->sys_clk)) { 1347 dev_err(&pdev->dev, "can't get system clock\n"); 1348 return PTR_ERR(i2c->sys_clk); 1349 } 1350 1351 i2c->scb_clk = devm_clk_get(&pdev->dev, "scb"); 1352 if (IS_ERR(i2c->scb_clk)) { 1353 dev_err(&pdev->dev, "can't get core clock\n"); 1354 return PTR_ERR(i2c->scb_clk); 1355 } 1356 1357 ret = devm_request_irq(&pdev->dev, irq, img_i2c_isr, 0, 1358 pdev->name, i2c); 1359 if (ret) { 1360 dev_err(&pdev->dev, "can't request irq %d\n", irq); 1361 return ret; 1362 } 1363 1364 /* Set up the exception check timer */ 1365 setup_timer(&i2c->check_timer, img_i2c_check_timer, 1366 (unsigned long)i2c); 1367 1368 i2c->bitrate = timings[0].max_bitrate; 1369 if (!of_property_read_u32(node, "clock-frequency", &val)) 1370 i2c->bitrate = val; 1371 1372 i2c_set_adapdata(&i2c->adap, i2c); 1373 i2c->adap.dev.parent = &pdev->dev; 1374 i2c->adap.dev.of_node = node; 1375 i2c->adap.owner = THIS_MODULE; 1376 i2c->adap.algo = &img_i2c_algo; 1377 i2c->adap.retries = 5; 1378 i2c->adap.nr = pdev->id; 1379 snprintf(i2c->adap.name, sizeof(i2c->adap.name), "IMG SCB I2C"); 1380 1381 img_i2c_switch_mode(i2c, MODE_INACTIVE); 1382 spin_lock_init(&i2c->lock); 1383 init_completion(&i2c->msg_complete); 1384 1385 platform_set_drvdata(pdev, i2c); 1386 1387 ret = clk_prepare_enable(i2c->sys_clk); 1388 if (ret) 1389 return ret; 1390 1391 ret = img_i2c_init(i2c); 1392 if (ret) 1393 goto disable_clk; 1394 1395 ret = i2c_add_numbered_adapter(&i2c->adap); 1396 if (ret < 0) 1397 goto disable_clk; 1398 1399 return 0; 1400 1401 disable_clk: 1402 clk_disable_unprepare(i2c->sys_clk); 1403 return ret; 1404 } 1405 1406 static int img_i2c_remove(struct platform_device *dev) 1407 { 1408 struct img_i2c *i2c = platform_get_drvdata(dev); 1409 1410 i2c_del_adapter(&i2c->adap); 1411 clk_disable_unprepare(i2c->sys_clk); 1412 1413 return 0; 1414 } 1415 1416 #ifdef CONFIG_PM_SLEEP 1417 static int img_i2c_suspend(struct device *dev) 1418 { 1419 struct img_i2c *i2c = dev_get_drvdata(dev); 1420 1421 img_i2c_switch_mode(i2c, MODE_SUSPEND); 1422 1423 clk_disable_unprepare(i2c->sys_clk); 1424 1425 return 0; 1426 } 1427 1428 static int img_i2c_resume(struct device *dev) 1429 { 1430 struct img_i2c *i2c = dev_get_drvdata(dev); 1431 int ret; 1432 1433 ret = clk_prepare_enable(i2c->sys_clk); 1434 if (ret) 1435 return ret; 1436 1437 img_i2c_init(i2c); 1438 1439 return 0; 1440 } 1441 #endif /* CONFIG_PM_SLEEP */ 1442 1443 static SIMPLE_DEV_PM_OPS(img_i2c_pm, img_i2c_suspend, img_i2c_resume); 1444 1445 static const struct of_device_id img_scb_i2c_match[] = { 1446 { .compatible = "img,scb-i2c" }, 1447 { } 1448 }; 1449 MODULE_DEVICE_TABLE(of, img_scb_i2c_match); 1450 1451 static struct platform_driver img_scb_i2c_driver = { 1452 .driver = { 1453 .name = "img-i2c-scb", 1454 .of_match_table = img_scb_i2c_match, 1455 .pm = &img_i2c_pm, 1456 }, 1457 .probe = img_i2c_probe, 1458 .remove = img_i2c_remove, 1459 }; 1460 module_platform_driver(img_scb_i2c_driver); 1461 1462 MODULE_AUTHOR("James Hogan <jhogan@kernel.org>"); 1463 MODULE_DESCRIPTION("IMG host I2C driver"); 1464 MODULE_LICENSE("GPL v2"); 1465