1 /* 2 * I2C adapter for the IMG Serial Control Bus (SCB) IP block. 3 * 4 * Copyright (C) 2009, 2010, 2012, 2014 Imagination Technologies Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * There are three ways that this I2C controller can be driven: 11 * 12 * - Raw control of the SDA and SCK signals. 13 * 14 * This corresponds to MODE_RAW, which takes control of the signals 15 * directly for a certain number of clock cycles (the INT_TIMING 16 * interrupt can be used for timing). 17 * 18 * - Atomic commands. A low level I2C symbol (such as generate 19 * start/stop/ack/nack bit, generate byte, receive byte, and receive 20 * ACK) is given to the hardware, with detection of completion by bits 21 * in the LINESTAT register. 22 * 23 * This mode of operation is used by MODE_ATOMIC, which uses an I2C 24 * state machine in the interrupt handler to compose/react to I2C 25 * transactions using atomic mode commands, and also by MODE_SEQUENCE, 26 * which emits a simple fixed sequence of atomic mode commands. 27 * 28 * Due to software control, the use of atomic commands usually results 29 * in suboptimal use of the bus, with gaps between the I2C symbols while 30 * the driver decides what to do next. 31 * 32 * - Automatic mode. A bus address, and whether to read/write is 33 * specified, and the hardware takes care of the I2C state machine, 34 * using a FIFO to send/receive bytes of data to an I2C slave. The 35 * driver just has to keep the FIFO drained or filled in response to the 36 * appropriate FIFO interrupts. 37 * 38 * This corresponds to MODE_AUTOMATIC, which manages the FIFOs and deals 39 * with control of repeated start bits between I2C messages. 40 * 41 * Use of automatic mode and the FIFO can make much more efficient use 42 * of the bus compared to individual atomic commands, with potentially 43 * no wasted time between I2C symbols or I2C messages. 44 * 45 * In most cases MODE_AUTOMATIC is used, however if any of the messages in 46 * a transaction are zero byte writes (e.g. used by i2cdetect for probing 47 * the bus), MODE_ATOMIC must be used since automatic mode is normally 48 * started by the writing of data into the FIFO. 49 * 50 * The other modes are used in specific circumstances where MODE_ATOMIC and 51 * MODE_AUTOMATIC aren't appropriate. MODE_RAW is used to implement a bus 52 * recovery routine. MODE_SEQUENCE is used to reset the bus and make sure 53 * it is in a sane state. 54 * 55 * Notice that the driver implements a timer-based timeout mechanism. 56 * The reason for this mechanism is to reduce the number of interrupts 57 * received in automatic mode. 58 * 59 * The driver would get a slave event and transaction done interrupts for 60 * each atomic mode command that gets completed. However, these events are 61 * not needed in automatic mode, becase those atomic mode commands are 62 * managed automatically by the hardware. 63 * 64 * In practice, normal I2C transactions will be complete well before you 65 * get the timer interrupt, as the timer is re-scheduled during FIFO 66 * maintenance and disabled after the transaction is complete. 67 * 68 * In this way normal automatic mode operation isn't impacted by 69 * unnecessary interrupts, but the exceptional abort condition can still be 70 * detected (with a slight delay). 71 */ 72 73 #include <linux/bitops.h> 74 #include <linux/clk.h> 75 #include <linux/completion.h> 76 #include <linux/err.h> 77 #include <linux/i2c.h> 78 #include <linux/init.h> 79 #include <linux/interrupt.h> 80 #include <linux/io.h> 81 #include <linux/kernel.h> 82 #include <linux/module.h> 83 #include <linux/of_platform.h> 84 #include <linux/platform_device.h> 85 #include <linux/pm_runtime.h> 86 #include <linux/slab.h> 87 #include <linux/timer.h> 88 89 /* Register offsets */ 90 91 #define SCB_STATUS_REG 0x00 92 #define SCB_OVERRIDE_REG 0x04 93 #define SCB_READ_ADDR_REG 0x08 94 #define SCB_READ_COUNT_REG 0x0c 95 #define SCB_WRITE_ADDR_REG 0x10 96 #define SCB_READ_DATA_REG 0x14 97 #define SCB_WRITE_DATA_REG 0x18 98 #define SCB_FIFO_STATUS_REG 0x1c 99 #define SCB_CONTROL_SOFT_RESET 0x1f 100 #define SCB_CLK_SET_REG 0x3c 101 #define SCB_INT_STATUS_REG 0x40 102 #define SCB_INT_CLEAR_REG 0x44 103 #define SCB_INT_MASK_REG 0x48 104 #define SCB_CONTROL_REG 0x4c 105 #define SCB_TIME_TPL_REG 0x50 106 #define SCB_TIME_TPH_REG 0x54 107 #define SCB_TIME_TP2S_REG 0x58 108 #define SCB_TIME_TBI_REG 0x60 109 #define SCB_TIME_TSL_REG 0x64 110 #define SCB_TIME_TDL_REG 0x68 111 #define SCB_TIME_TSDL_REG 0x6c 112 #define SCB_TIME_TSDH_REG 0x70 113 #define SCB_READ_XADDR_REG 0x74 114 #define SCB_WRITE_XADDR_REG 0x78 115 #define SCB_WRITE_COUNT_REG 0x7c 116 #define SCB_CORE_REV_REG 0x80 117 #define SCB_TIME_TCKH_REG 0x84 118 #define SCB_TIME_TCKL_REG 0x88 119 #define SCB_FIFO_FLUSH_REG 0x8c 120 #define SCB_READ_FIFO_REG 0x94 121 #define SCB_CLEAR_REG 0x98 122 123 /* SCB_CONTROL_REG bits */ 124 125 #define SCB_CONTROL_CLK_ENABLE 0x1e0 126 #define SCB_CONTROL_TRANSACTION_HALT 0x200 127 128 #define FIFO_READ_FULL BIT(0) 129 #define FIFO_READ_EMPTY BIT(1) 130 #define FIFO_WRITE_FULL BIT(2) 131 #define FIFO_WRITE_EMPTY BIT(3) 132 133 /* SCB_CLK_SET_REG bits */ 134 #define SCB_FILT_DISABLE BIT(31) 135 #define SCB_FILT_BYPASS BIT(30) 136 #define SCB_FILT_INC_MASK 0x7f 137 #define SCB_FILT_INC_SHIFT 16 138 #define SCB_INC_MASK 0x7f 139 #define SCB_INC_SHIFT 8 140 141 /* SCB_INT_*_REG bits */ 142 143 #define INT_BUS_INACTIVE BIT(0) 144 #define INT_UNEXPECTED_START BIT(1) 145 #define INT_SCLK_LOW_TIMEOUT BIT(2) 146 #define INT_SDAT_LOW_TIMEOUT BIT(3) 147 #define INT_WRITE_ACK_ERR BIT(4) 148 #define INT_ADDR_ACK_ERR BIT(5) 149 #define INT_FIFO_FULL BIT(9) 150 #define INT_FIFO_FILLING BIT(10) 151 #define INT_FIFO_EMPTY BIT(11) 152 #define INT_FIFO_EMPTYING BIT(12) 153 #define INT_TRANSACTION_DONE BIT(15) 154 #define INT_SLAVE_EVENT BIT(16) 155 #define INT_MASTER_HALTED BIT(17) 156 #define INT_TIMING BIT(18) 157 #define INT_STOP_DETECTED BIT(19) 158 159 #define INT_FIFO_FULL_FILLING (INT_FIFO_FULL | INT_FIFO_FILLING) 160 161 /* Level interrupts need clearing after handling instead of before */ 162 #define INT_LEVEL 0x01e00 163 164 /* Don't allow any interrupts while the clock may be off */ 165 #define INT_ENABLE_MASK_INACTIVE 0x00000 166 167 /* Interrupt masks for the different driver modes */ 168 169 #define INT_ENABLE_MASK_RAW INT_TIMING 170 171 #define INT_ENABLE_MASK_ATOMIC (INT_TRANSACTION_DONE | \ 172 INT_SLAVE_EVENT | \ 173 INT_ADDR_ACK_ERR | \ 174 INT_WRITE_ACK_ERR) 175 176 #define INT_ENABLE_MASK_AUTOMATIC (INT_SCLK_LOW_TIMEOUT | \ 177 INT_ADDR_ACK_ERR | \ 178 INT_WRITE_ACK_ERR | \ 179 INT_FIFO_FULL | \ 180 INT_FIFO_FILLING | \ 181 INT_FIFO_EMPTY | \ 182 INT_MASTER_HALTED | \ 183 INT_STOP_DETECTED) 184 185 #define INT_ENABLE_MASK_WAITSTOP (INT_SLAVE_EVENT | \ 186 INT_ADDR_ACK_ERR | \ 187 INT_WRITE_ACK_ERR) 188 189 /* SCB_STATUS_REG fields */ 190 191 #define LINESTAT_SCLK_LINE_STATUS BIT(0) 192 #define LINESTAT_SCLK_EN BIT(1) 193 #define LINESTAT_SDAT_LINE_STATUS BIT(2) 194 #define LINESTAT_SDAT_EN BIT(3) 195 #define LINESTAT_DET_START_STATUS BIT(4) 196 #define LINESTAT_DET_STOP_STATUS BIT(5) 197 #define LINESTAT_DET_ACK_STATUS BIT(6) 198 #define LINESTAT_DET_NACK_STATUS BIT(7) 199 #define LINESTAT_BUS_IDLE BIT(8) 200 #define LINESTAT_T_DONE_STATUS BIT(9) 201 #define LINESTAT_SCLK_OUT_STATUS BIT(10) 202 #define LINESTAT_SDAT_OUT_STATUS BIT(11) 203 #define LINESTAT_GEN_LINE_MASK_STATUS BIT(12) 204 #define LINESTAT_START_BIT_DET BIT(13) 205 #define LINESTAT_STOP_BIT_DET BIT(14) 206 #define LINESTAT_ACK_DET BIT(15) 207 #define LINESTAT_NACK_DET BIT(16) 208 #define LINESTAT_INPUT_HELD_V BIT(17) 209 #define LINESTAT_ABORT_DET BIT(18) 210 #define LINESTAT_ACK_OR_NACK_DET (LINESTAT_ACK_DET | LINESTAT_NACK_DET) 211 #define LINESTAT_INPUT_DATA 0xff000000 212 #define LINESTAT_INPUT_DATA_SHIFT 24 213 214 #define LINESTAT_CLEAR_SHIFT 13 215 #define LINESTAT_LATCHED (0x3f << LINESTAT_CLEAR_SHIFT) 216 217 /* SCB_OVERRIDE_REG fields */ 218 219 #define OVERRIDE_SCLK_OVR BIT(0) 220 #define OVERRIDE_SCLKEN_OVR BIT(1) 221 #define OVERRIDE_SDAT_OVR BIT(2) 222 #define OVERRIDE_SDATEN_OVR BIT(3) 223 #define OVERRIDE_MASTER BIT(9) 224 #define OVERRIDE_LINE_OVR_EN BIT(10) 225 #define OVERRIDE_DIRECT BIT(11) 226 #define OVERRIDE_CMD_SHIFT 4 227 #define OVERRIDE_CMD_MASK 0x1f 228 #define OVERRIDE_DATA_SHIFT 24 229 230 #define OVERRIDE_SCLK_DOWN (OVERRIDE_LINE_OVR_EN | \ 231 OVERRIDE_SCLKEN_OVR) 232 #define OVERRIDE_SCLK_UP (OVERRIDE_LINE_OVR_EN | \ 233 OVERRIDE_SCLKEN_OVR | \ 234 OVERRIDE_SCLK_OVR) 235 #define OVERRIDE_SDAT_DOWN (OVERRIDE_LINE_OVR_EN | \ 236 OVERRIDE_SDATEN_OVR) 237 #define OVERRIDE_SDAT_UP (OVERRIDE_LINE_OVR_EN | \ 238 OVERRIDE_SDATEN_OVR | \ 239 OVERRIDE_SDAT_OVR) 240 241 /* OVERRIDE_CMD values */ 242 243 #define CMD_PAUSE 0x00 244 #define CMD_GEN_DATA 0x01 245 #define CMD_GEN_START 0x02 246 #define CMD_GEN_STOP 0x03 247 #define CMD_GEN_ACK 0x04 248 #define CMD_GEN_NACK 0x05 249 #define CMD_RET_DATA 0x08 250 #define CMD_RET_ACK 0x09 251 252 /* Fixed timing values */ 253 254 #define TIMEOUT_TBI 0x0 255 #define TIMEOUT_TSL 0xffff 256 #define TIMEOUT_TDL 0x0 257 258 /* Transaction timeout */ 259 260 #define IMG_I2C_TIMEOUT (msecs_to_jiffies(1000)) 261 262 /* 263 * Worst incs are 1 (innacurate) and 16*256 (irregular). 264 * So a sensible inc is the logarithmic mean: 64 (2^6), which is 265 * in the middle of the valid range (0-127). 266 */ 267 #define SCB_OPT_INC 64 268 269 /* Setup the clock enable filtering for 25 ns */ 270 #define SCB_FILT_GLITCH 25 271 272 /* 273 * Bits to return from interrupt handler functions for different modes. 274 * This delays completion until we've finished with the registers, so that the 275 * function waiting for completion can safely disable the clock to save power. 276 */ 277 #define ISR_COMPLETE_M BIT(31) 278 #define ISR_FATAL_M BIT(30) 279 #define ISR_WAITSTOP BIT(29) 280 #define ISR_STATUS_M 0x0000ffff /* contains +ve errno */ 281 #define ISR_COMPLETE(err) (ISR_COMPLETE_M | (ISR_STATUS_M & (err))) 282 #define ISR_FATAL(err) (ISR_COMPLETE(err) | ISR_FATAL_M) 283 284 #define IMG_I2C_PM_TIMEOUT 1000 /* ms */ 285 286 enum img_i2c_mode { 287 MODE_INACTIVE, 288 MODE_RAW, 289 MODE_ATOMIC, 290 MODE_AUTOMATIC, 291 MODE_SEQUENCE, 292 MODE_FATAL, 293 MODE_WAITSTOP, 294 MODE_SUSPEND, 295 }; 296 297 /* Timing parameters for i2c modes (in ns) */ 298 struct img_i2c_timings { 299 const char *name; 300 unsigned int max_bitrate; 301 unsigned int tckh, tckl, tsdh, tsdl; 302 unsigned int tp2s, tpl, tph; 303 }; 304 305 /* The timings array must be ordered from slower to faster */ 306 static struct img_i2c_timings timings[] = { 307 /* Standard mode */ 308 { 309 .name = "standard", 310 .max_bitrate = 100000, 311 .tckh = 4000, 312 .tckl = 4700, 313 .tsdh = 4700, 314 .tsdl = 8700, 315 .tp2s = 4700, 316 .tpl = 4700, 317 .tph = 4000, 318 }, 319 /* Fast mode */ 320 { 321 .name = "fast", 322 .max_bitrate = 400000, 323 .tckh = 600, 324 .tckl = 1300, 325 .tsdh = 600, 326 .tsdl = 1200, 327 .tp2s = 1300, 328 .tpl = 600, 329 .tph = 600, 330 }, 331 }; 332 333 /* Reset dance */ 334 static u8 img_i2c_reset_seq[] = { CMD_GEN_START, 335 CMD_GEN_DATA, 0xff, 336 CMD_RET_ACK, 337 CMD_GEN_START, 338 CMD_GEN_STOP, 339 0 }; 340 /* Just issue a stop (after an abort condition) */ 341 static u8 img_i2c_stop_seq[] = { CMD_GEN_STOP, 342 0 }; 343 344 /* We're interested in different interrupts depending on the mode */ 345 static unsigned int img_i2c_int_enable_by_mode[] = { 346 [MODE_INACTIVE] = INT_ENABLE_MASK_INACTIVE, 347 [MODE_RAW] = INT_ENABLE_MASK_RAW, 348 [MODE_ATOMIC] = INT_ENABLE_MASK_ATOMIC, 349 [MODE_AUTOMATIC] = INT_ENABLE_MASK_AUTOMATIC, 350 [MODE_SEQUENCE] = INT_ENABLE_MASK_ATOMIC, 351 [MODE_FATAL] = 0, 352 [MODE_WAITSTOP] = INT_ENABLE_MASK_WAITSTOP, 353 [MODE_SUSPEND] = 0, 354 }; 355 356 /* Atomic command names */ 357 static const char * const img_i2c_atomic_cmd_names[] = { 358 [CMD_PAUSE] = "PAUSE", 359 [CMD_GEN_DATA] = "GEN_DATA", 360 [CMD_GEN_START] = "GEN_START", 361 [CMD_GEN_STOP] = "GEN_STOP", 362 [CMD_GEN_ACK] = "GEN_ACK", 363 [CMD_GEN_NACK] = "GEN_NACK", 364 [CMD_RET_DATA] = "RET_DATA", 365 [CMD_RET_ACK] = "RET_ACK", 366 }; 367 368 struct img_i2c { 369 struct i2c_adapter adap; 370 371 void __iomem *base; 372 373 /* 374 * The scb core clock is used to get the input frequency, and to disable 375 * it after every set of transactions to save some power. 376 */ 377 struct clk *scb_clk, *sys_clk; 378 unsigned int bitrate; 379 bool need_wr_rd_fence; 380 381 /* state */ 382 struct completion msg_complete; 383 spinlock_t lock; /* lock before doing anything with the state */ 384 struct i2c_msg msg; 385 386 /* After the last transaction, wait for a stop bit */ 387 bool last_msg; 388 int msg_status; 389 390 enum img_i2c_mode mode; 391 u32 int_enable; /* depends on mode */ 392 u32 line_status; /* line status over command */ 393 394 /* 395 * To avoid slave event interrupts in automatic mode, use a timer to 396 * poll the abort condition if we don't get an interrupt for too long. 397 */ 398 struct timer_list check_timer; 399 bool t_halt; 400 401 /* atomic mode state */ 402 bool at_t_done; 403 bool at_slave_event; 404 int at_cur_cmd; 405 u8 at_cur_data; 406 407 /* Sequence: either reset or stop. See img_i2c_sequence. */ 408 u8 *seq; 409 410 /* raw mode */ 411 unsigned int raw_timeout; 412 }; 413 414 static int img_i2c_runtime_suspend(struct device *dev); 415 static int img_i2c_runtime_resume(struct device *dev); 416 417 static void img_i2c_writel(struct img_i2c *i2c, u32 offset, u32 value) 418 { 419 writel(value, i2c->base + offset); 420 } 421 422 static u32 img_i2c_readl(struct img_i2c *i2c, u32 offset) 423 { 424 return readl(i2c->base + offset); 425 } 426 427 /* 428 * The code to read from the master read fifo, and write to the master 429 * write fifo, checks a bit in an SCB register before every byte to 430 * ensure that the fifo is not full (write fifo) or empty (read fifo). 431 * Due to clock domain crossing inside the SCB block the updated value 432 * of this bit is only visible after 2 cycles. 433 * 434 * The scb_wr_rd_fence() function does 2 dummy writes (to the read-only 435 * revision register), and it's called after reading from or writing to the 436 * fifos to ensure that subsequent reads of the fifo status bits do not read 437 * stale values. 438 */ 439 static void img_i2c_wr_rd_fence(struct img_i2c *i2c) 440 { 441 if (i2c->need_wr_rd_fence) { 442 img_i2c_writel(i2c, SCB_CORE_REV_REG, 0); 443 img_i2c_writel(i2c, SCB_CORE_REV_REG, 0); 444 } 445 } 446 447 static void img_i2c_switch_mode(struct img_i2c *i2c, enum img_i2c_mode mode) 448 { 449 i2c->mode = mode; 450 i2c->int_enable = img_i2c_int_enable_by_mode[mode]; 451 i2c->line_status = 0; 452 } 453 454 static void img_i2c_raw_op(struct img_i2c *i2c) 455 { 456 i2c->raw_timeout = 0; 457 img_i2c_writel(i2c, SCB_OVERRIDE_REG, 458 OVERRIDE_SCLKEN_OVR | 459 OVERRIDE_SDATEN_OVR | 460 OVERRIDE_MASTER | 461 OVERRIDE_LINE_OVR_EN | 462 OVERRIDE_DIRECT | 463 ((i2c->at_cur_cmd & OVERRIDE_CMD_MASK) << OVERRIDE_CMD_SHIFT) | 464 (i2c->at_cur_data << OVERRIDE_DATA_SHIFT)); 465 } 466 467 static const char *img_i2c_atomic_op_name(unsigned int cmd) 468 { 469 if (unlikely(cmd >= ARRAY_SIZE(img_i2c_atomic_cmd_names))) 470 return "UNKNOWN"; 471 return img_i2c_atomic_cmd_names[cmd]; 472 } 473 474 /* Send a single atomic mode command to the hardware */ 475 static void img_i2c_atomic_op(struct img_i2c *i2c, int cmd, u8 data) 476 { 477 i2c->at_cur_cmd = cmd; 478 i2c->at_cur_data = data; 479 480 /* work around lack of data setup time when generating data */ 481 if (cmd == CMD_GEN_DATA && i2c->mode == MODE_ATOMIC) { 482 u32 line_status = img_i2c_readl(i2c, SCB_STATUS_REG); 483 484 if (line_status & LINESTAT_SDAT_LINE_STATUS && !(data & 0x80)) { 485 /* hold the data line down for a moment */ 486 img_i2c_switch_mode(i2c, MODE_RAW); 487 img_i2c_raw_op(i2c); 488 return; 489 } 490 } 491 492 dev_dbg(i2c->adap.dev.parent, 493 "atomic cmd=%s (%d) data=%#x\n", 494 img_i2c_atomic_op_name(cmd), cmd, data); 495 i2c->at_t_done = (cmd == CMD_RET_DATA || cmd == CMD_RET_ACK); 496 i2c->at_slave_event = false; 497 i2c->line_status = 0; 498 499 img_i2c_writel(i2c, SCB_OVERRIDE_REG, 500 ((cmd & OVERRIDE_CMD_MASK) << OVERRIDE_CMD_SHIFT) | 501 OVERRIDE_MASTER | 502 OVERRIDE_DIRECT | 503 (data << OVERRIDE_DATA_SHIFT)); 504 } 505 506 /* Start a transaction in atomic mode */ 507 static void img_i2c_atomic_start(struct img_i2c *i2c) 508 { 509 img_i2c_switch_mode(i2c, MODE_ATOMIC); 510 img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable); 511 img_i2c_atomic_op(i2c, CMD_GEN_START, 0x00); 512 } 513 514 static void img_i2c_soft_reset(struct img_i2c *i2c) 515 { 516 i2c->t_halt = false; 517 img_i2c_writel(i2c, SCB_CONTROL_REG, 0); 518 img_i2c_writel(i2c, SCB_CONTROL_REG, 519 SCB_CONTROL_CLK_ENABLE | SCB_CONTROL_SOFT_RESET); 520 } 521 522 /* 523 * Enable or release transaction halt for control of repeated starts. 524 * In version 3.3 of the IP when transaction halt is set, an interrupt 525 * will be generated after each byte of a transfer instead of after 526 * every transfer but before the stop bit. 527 * Due to this behaviour we have to be careful that every time we 528 * release the transaction halt we have to re-enable it straight away 529 * so that we only process a single byte, not doing so will result in 530 * all remaining bytes been processed and a stop bit being issued, 531 * which will prevent us having a repeated start. 532 */ 533 static void img_i2c_transaction_halt(struct img_i2c *i2c, bool t_halt) 534 { 535 u32 val; 536 537 if (i2c->t_halt == t_halt) 538 return; 539 i2c->t_halt = t_halt; 540 val = img_i2c_readl(i2c, SCB_CONTROL_REG); 541 if (t_halt) 542 val |= SCB_CONTROL_TRANSACTION_HALT; 543 else 544 val &= ~SCB_CONTROL_TRANSACTION_HALT; 545 img_i2c_writel(i2c, SCB_CONTROL_REG, val); 546 } 547 548 /* Drain data from the FIFO into the buffer (automatic mode) */ 549 static void img_i2c_read_fifo(struct img_i2c *i2c) 550 { 551 while (i2c->msg.len) { 552 u32 fifo_status; 553 u8 data; 554 555 img_i2c_wr_rd_fence(i2c); 556 fifo_status = img_i2c_readl(i2c, SCB_FIFO_STATUS_REG); 557 if (fifo_status & FIFO_READ_EMPTY) 558 break; 559 560 data = img_i2c_readl(i2c, SCB_READ_DATA_REG); 561 *i2c->msg.buf = data; 562 563 img_i2c_writel(i2c, SCB_READ_FIFO_REG, 0xff); 564 i2c->msg.len--; 565 i2c->msg.buf++; 566 } 567 } 568 569 /* Fill the FIFO with data from the buffer (automatic mode) */ 570 static void img_i2c_write_fifo(struct img_i2c *i2c) 571 { 572 while (i2c->msg.len) { 573 u32 fifo_status; 574 575 img_i2c_wr_rd_fence(i2c); 576 fifo_status = img_i2c_readl(i2c, SCB_FIFO_STATUS_REG); 577 if (fifo_status & FIFO_WRITE_FULL) 578 break; 579 580 img_i2c_writel(i2c, SCB_WRITE_DATA_REG, *i2c->msg.buf); 581 i2c->msg.len--; 582 i2c->msg.buf++; 583 } 584 585 /* Disable fifo emptying interrupt if nothing more to write */ 586 if (!i2c->msg.len) 587 i2c->int_enable &= ~INT_FIFO_EMPTYING; 588 } 589 590 /* Start a read transaction in automatic mode */ 591 static void img_i2c_read(struct img_i2c *i2c) 592 { 593 img_i2c_switch_mode(i2c, MODE_AUTOMATIC); 594 if (!i2c->last_msg) 595 i2c->int_enable |= INT_SLAVE_EVENT; 596 597 img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable); 598 img_i2c_writel(i2c, SCB_READ_ADDR_REG, i2c->msg.addr); 599 img_i2c_writel(i2c, SCB_READ_COUNT_REG, i2c->msg.len); 600 601 mod_timer(&i2c->check_timer, jiffies + msecs_to_jiffies(1)); 602 } 603 604 /* Start a write transaction in automatic mode */ 605 static void img_i2c_write(struct img_i2c *i2c) 606 { 607 img_i2c_switch_mode(i2c, MODE_AUTOMATIC); 608 if (!i2c->last_msg) 609 i2c->int_enable |= INT_SLAVE_EVENT; 610 611 img_i2c_writel(i2c, SCB_WRITE_ADDR_REG, i2c->msg.addr); 612 img_i2c_writel(i2c, SCB_WRITE_COUNT_REG, i2c->msg.len); 613 614 mod_timer(&i2c->check_timer, jiffies + msecs_to_jiffies(1)); 615 img_i2c_write_fifo(i2c); 616 617 /* img_i2c_write_fifo() may modify int_enable */ 618 img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable); 619 } 620 621 /* 622 * Indicate that the transaction is complete. This is called from the 623 * ISR to wake up the waiting thread, after which the ISR must not 624 * access any more SCB registers. 625 */ 626 static void img_i2c_complete_transaction(struct img_i2c *i2c, int status) 627 { 628 img_i2c_switch_mode(i2c, MODE_INACTIVE); 629 if (status) { 630 i2c->msg_status = status; 631 img_i2c_transaction_halt(i2c, false); 632 } 633 complete(&i2c->msg_complete); 634 } 635 636 static unsigned int img_i2c_raw_atomic_delay_handler(struct img_i2c *i2c, 637 u32 int_status, u32 line_status) 638 { 639 /* Stay in raw mode for this, so we don't just loop infinitely */ 640 img_i2c_atomic_op(i2c, i2c->at_cur_cmd, i2c->at_cur_data); 641 img_i2c_switch_mode(i2c, MODE_ATOMIC); 642 return 0; 643 } 644 645 static unsigned int img_i2c_raw(struct img_i2c *i2c, u32 int_status, 646 u32 line_status) 647 { 648 if (int_status & INT_TIMING) { 649 if (i2c->raw_timeout == 0) 650 return img_i2c_raw_atomic_delay_handler(i2c, 651 int_status, line_status); 652 --i2c->raw_timeout; 653 } 654 return 0; 655 } 656 657 static unsigned int img_i2c_sequence(struct img_i2c *i2c, u32 int_status) 658 { 659 static const unsigned int continue_bits[] = { 660 [CMD_GEN_START] = LINESTAT_START_BIT_DET, 661 [CMD_GEN_DATA] = LINESTAT_INPUT_HELD_V, 662 [CMD_RET_ACK] = LINESTAT_ACK_DET | LINESTAT_NACK_DET, 663 [CMD_RET_DATA] = LINESTAT_INPUT_HELD_V, 664 [CMD_GEN_STOP] = LINESTAT_STOP_BIT_DET, 665 }; 666 int next_cmd = -1; 667 u8 next_data = 0x00; 668 669 if (int_status & INT_SLAVE_EVENT) 670 i2c->at_slave_event = true; 671 if (int_status & INT_TRANSACTION_DONE) 672 i2c->at_t_done = true; 673 674 if (!i2c->at_slave_event || !i2c->at_t_done) 675 return 0; 676 677 /* wait if no continue bits are set */ 678 if (i2c->at_cur_cmd >= 0 && 679 i2c->at_cur_cmd < ARRAY_SIZE(continue_bits)) { 680 unsigned int cont_bits = continue_bits[i2c->at_cur_cmd]; 681 682 if (cont_bits) { 683 cont_bits |= LINESTAT_ABORT_DET; 684 if (!(i2c->line_status & cont_bits)) 685 return 0; 686 } 687 } 688 689 /* follow the sequence of commands in i2c->seq */ 690 next_cmd = *i2c->seq; 691 /* stop on a nil */ 692 if (!next_cmd) { 693 img_i2c_writel(i2c, SCB_OVERRIDE_REG, 0); 694 return ISR_COMPLETE(0); 695 } 696 /* when generating data, the next byte is the data */ 697 if (next_cmd == CMD_GEN_DATA) { 698 ++i2c->seq; 699 next_data = *i2c->seq; 700 } 701 ++i2c->seq; 702 img_i2c_atomic_op(i2c, next_cmd, next_data); 703 704 return 0; 705 } 706 707 static void img_i2c_reset_start(struct img_i2c *i2c) 708 { 709 /* Initiate the magic dance */ 710 img_i2c_switch_mode(i2c, MODE_SEQUENCE); 711 img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable); 712 i2c->seq = img_i2c_reset_seq; 713 i2c->at_slave_event = true; 714 i2c->at_t_done = true; 715 i2c->at_cur_cmd = -1; 716 717 /* img_i2c_reset_seq isn't empty so the following won't fail */ 718 img_i2c_sequence(i2c, 0); 719 } 720 721 static void img_i2c_stop_start(struct img_i2c *i2c) 722 { 723 /* Initiate a stop bit sequence */ 724 img_i2c_switch_mode(i2c, MODE_SEQUENCE); 725 img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable); 726 i2c->seq = img_i2c_stop_seq; 727 i2c->at_slave_event = true; 728 i2c->at_t_done = true; 729 i2c->at_cur_cmd = -1; 730 731 /* img_i2c_stop_seq isn't empty so the following won't fail */ 732 img_i2c_sequence(i2c, 0); 733 } 734 735 static unsigned int img_i2c_atomic(struct img_i2c *i2c, 736 u32 int_status, 737 u32 line_status) 738 { 739 int next_cmd = -1; 740 u8 next_data = 0x00; 741 742 if (int_status & INT_SLAVE_EVENT) 743 i2c->at_slave_event = true; 744 if (int_status & INT_TRANSACTION_DONE) 745 i2c->at_t_done = true; 746 747 if (!i2c->at_slave_event || !i2c->at_t_done) 748 goto next_atomic_cmd; 749 if (i2c->line_status & LINESTAT_ABORT_DET) { 750 dev_dbg(i2c->adap.dev.parent, "abort condition detected\n"); 751 next_cmd = CMD_GEN_STOP; 752 i2c->msg_status = -EIO; 753 goto next_atomic_cmd; 754 } 755 756 /* i2c->at_cur_cmd may have completed */ 757 switch (i2c->at_cur_cmd) { 758 case CMD_GEN_START: 759 next_cmd = CMD_GEN_DATA; 760 next_data = i2c_8bit_addr_from_msg(&i2c->msg); 761 break; 762 case CMD_GEN_DATA: 763 if (i2c->line_status & LINESTAT_INPUT_HELD_V) 764 next_cmd = CMD_RET_ACK; 765 break; 766 case CMD_RET_ACK: 767 if (i2c->line_status & LINESTAT_ACK_DET || 768 (i2c->line_status & LINESTAT_NACK_DET && 769 i2c->msg.flags & I2C_M_IGNORE_NAK)) { 770 if (i2c->msg.len == 0) { 771 next_cmd = CMD_GEN_STOP; 772 } else if (i2c->msg.flags & I2C_M_RD) { 773 next_cmd = CMD_RET_DATA; 774 } else { 775 next_cmd = CMD_GEN_DATA; 776 next_data = *i2c->msg.buf; 777 --i2c->msg.len; 778 ++i2c->msg.buf; 779 } 780 } else if (i2c->line_status & LINESTAT_NACK_DET) { 781 i2c->msg_status = -EIO; 782 next_cmd = CMD_GEN_STOP; 783 } 784 break; 785 case CMD_RET_DATA: 786 if (i2c->line_status & LINESTAT_INPUT_HELD_V) { 787 *i2c->msg.buf = (i2c->line_status & 788 LINESTAT_INPUT_DATA) 789 >> LINESTAT_INPUT_DATA_SHIFT; 790 --i2c->msg.len; 791 ++i2c->msg.buf; 792 if (i2c->msg.len) 793 next_cmd = CMD_GEN_ACK; 794 else 795 next_cmd = CMD_GEN_NACK; 796 } 797 break; 798 case CMD_GEN_ACK: 799 if (i2c->line_status & LINESTAT_ACK_DET) { 800 next_cmd = CMD_RET_DATA; 801 } else { 802 i2c->msg_status = -EIO; 803 next_cmd = CMD_GEN_STOP; 804 } 805 break; 806 case CMD_GEN_NACK: 807 next_cmd = CMD_GEN_STOP; 808 break; 809 case CMD_GEN_STOP: 810 img_i2c_writel(i2c, SCB_OVERRIDE_REG, 0); 811 return ISR_COMPLETE(0); 812 default: 813 dev_err(i2c->adap.dev.parent, "bad atomic command %d\n", 814 i2c->at_cur_cmd); 815 i2c->msg_status = -EIO; 816 next_cmd = CMD_GEN_STOP; 817 break; 818 } 819 820 next_atomic_cmd: 821 if (next_cmd != -1) { 822 /* don't actually stop unless we're the last transaction */ 823 if (next_cmd == CMD_GEN_STOP && !i2c->msg_status && 824 !i2c->last_msg) 825 return ISR_COMPLETE(0); 826 img_i2c_atomic_op(i2c, next_cmd, next_data); 827 } 828 return 0; 829 } 830 831 /* 832 * Timer function to check if something has gone wrong in automatic mode (so we 833 * don't have to handle so many interrupts just to catch an exception). 834 */ 835 static void img_i2c_check_timer(struct timer_list *t) 836 { 837 struct img_i2c *i2c = from_timer(i2c, t, check_timer); 838 unsigned long flags; 839 unsigned int line_status; 840 841 spin_lock_irqsave(&i2c->lock, flags); 842 line_status = img_i2c_readl(i2c, SCB_STATUS_REG); 843 844 /* check for an abort condition */ 845 if (line_status & LINESTAT_ABORT_DET) { 846 dev_dbg(i2c->adap.dev.parent, 847 "abort condition detected by check timer\n"); 848 /* enable slave event interrupt mask to trigger irq */ 849 img_i2c_writel(i2c, SCB_INT_MASK_REG, 850 i2c->int_enable | INT_SLAVE_EVENT); 851 } 852 853 spin_unlock_irqrestore(&i2c->lock, flags); 854 } 855 856 static unsigned int img_i2c_auto(struct img_i2c *i2c, 857 unsigned int int_status, 858 unsigned int line_status) 859 { 860 if (int_status & (INT_WRITE_ACK_ERR | INT_ADDR_ACK_ERR)) 861 return ISR_COMPLETE(EIO); 862 863 if (line_status & LINESTAT_ABORT_DET) { 864 dev_dbg(i2c->adap.dev.parent, "abort condition detected\n"); 865 /* empty the read fifo */ 866 if ((i2c->msg.flags & I2C_M_RD) && 867 (int_status & INT_FIFO_FULL_FILLING)) 868 img_i2c_read_fifo(i2c); 869 /* use atomic mode and try to force a stop bit */ 870 i2c->msg_status = -EIO; 871 img_i2c_stop_start(i2c); 872 return 0; 873 } 874 875 /* Enable transaction halt on start bit */ 876 if (!i2c->last_msg && line_status & LINESTAT_START_BIT_DET) { 877 img_i2c_transaction_halt(i2c, !i2c->last_msg); 878 /* we're no longer interested in the slave event */ 879 i2c->int_enable &= ~INT_SLAVE_EVENT; 880 } 881 882 mod_timer(&i2c->check_timer, jiffies + msecs_to_jiffies(1)); 883 884 if (int_status & INT_STOP_DETECTED) { 885 /* Drain remaining data in FIFO and complete transaction */ 886 if (i2c->msg.flags & I2C_M_RD) 887 img_i2c_read_fifo(i2c); 888 return ISR_COMPLETE(0); 889 } 890 891 if (i2c->msg.flags & I2C_M_RD) { 892 if (int_status & (INT_FIFO_FULL_FILLING | INT_MASTER_HALTED)) { 893 img_i2c_read_fifo(i2c); 894 if (i2c->msg.len == 0) 895 return ISR_WAITSTOP; 896 } 897 } else { 898 if (int_status & (INT_FIFO_EMPTY | INT_MASTER_HALTED)) { 899 if ((int_status & INT_FIFO_EMPTY) && 900 i2c->msg.len == 0) 901 return ISR_WAITSTOP; 902 img_i2c_write_fifo(i2c); 903 } 904 } 905 if (int_status & INT_MASTER_HALTED) { 906 /* 907 * Release and then enable transaction halt, to 908 * allow only a single byte to proceed. 909 */ 910 img_i2c_transaction_halt(i2c, false); 911 img_i2c_transaction_halt(i2c, !i2c->last_msg); 912 } 913 914 return 0; 915 } 916 917 static irqreturn_t img_i2c_isr(int irq, void *dev_id) 918 { 919 struct img_i2c *i2c = (struct img_i2c *)dev_id; 920 u32 int_status, line_status; 921 /* We handle transaction completion AFTER accessing registers */ 922 unsigned int hret; 923 924 /* Read interrupt status register. */ 925 int_status = img_i2c_readl(i2c, SCB_INT_STATUS_REG); 926 /* Clear detected interrupts. */ 927 img_i2c_writel(i2c, SCB_INT_CLEAR_REG, int_status); 928 929 /* 930 * Read line status and clear it until it actually is clear. We have 931 * to be careful not to lose any line status bits that get latched. 932 */ 933 line_status = img_i2c_readl(i2c, SCB_STATUS_REG); 934 if (line_status & LINESTAT_LATCHED) { 935 img_i2c_writel(i2c, SCB_CLEAR_REG, 936 (line_status & LINESTAT_LATCHED) 937 >> LINESTAT_CLEAR_SHIFT); 938 img_i2c_wr_rd_fence(i2c); 939 } 940 941 spin_lock(&i2c->lock); 942 943 /* Keep track of line status bits received */ 944 i2c->line_status &= ~LINESTAT_INPUT_DATA; 945 i2c->line_status |= line_status; 946 947 /* 948 * Certain interrupts indicate that sclk low timeout is not 949 * a problem. If any of these are set, just continue. 950 */ 951 if ((int_status & INT_SCLK_LOW_TIMEOUT) && 952 !(int_status & (INT_SLAVE_EVENT | 953 INT_FIFO_EMPTY | 954 INT_FIFO_FULL))) { 955 dev_crit(i2c->adap.dev.parent, 956 "fatal: clock low timeout occurred %s addr 0x%02x\n", 957 (i2c->msg.flags & I2C_M_RD) ? "reading" : "writing", 958 i2c->msg.addr); 959 hret = ISR_FATAL(EIO); 960 goto out; 961 } 962 963 if (i2c->mode == MODE_ATOMIC) 964 hret = img_i2c_atomic(i2c, int_status, line_status); 965 else if (i2c->mode == MODE_AUTOMATIC) 966 hret = img_i2c_auto(i2c, int_status, line_status); 967 else if (i2c->mode == MODE_SEQUENCE) 968 hret = img_i2c_sequence(i2c, int_status); 969 else if (i2c->mode == MODE_WAITSTOP && (int_status & INT_SLAVE_EVENT) && 970 (line_status & LINESTAT_STOP_BIT_DET)) 971 hret = ISR_COMPLETE(0); 972 else if (i2c->mode == MODE_RAW) 973 hret = img_i2c_raw(i2c, int_status, line_status); 974 else 975 hret = 0; 976 977 /* Clear detected level interrupts. */ 978 img_i2c_writel(i2c, SCB_INT_CLEAR_REG, int_status & INT_LEVEL); 979 980 out: 981 if (hret & ISR_WAITSTOP) { 982 /* 983 * Only wait for stop on last message. 984 * Also we may already have detected the stop bit. 985 */ 986 if (!i2c->last_msg || i2c->line_status & LINESTAT_STOP_BIT_DET) 987 hret = ISR_COMPLETE(0); 988 else 989 img_i2c_switch_mode(i2c, MODE_WAITSTOP); 990 } 991 992 /* now we've finished using regs, handle transaction completion */ 993 if (hret & ISR_COMPLETE_M) { 994 int status = -(hret & ISR_STATUS_M); 995 996 img_i2c_complete_transaction(i2c, status); 997 if (hret & ISR_FATAL_M) 998 img_i2c_switch_mode(i2c, MODE_FATAL); 999 } 1000 1001 /* Enable interrupts (int_enable may be altered by changing mode) */ 1002 img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable); 1003 1004 spin_unlock(&i2c->lock); 1005 1006 return IRQ_HANDLED; 1007 } 1008 1009 /* Force a bus reset sequence and wait for it to complete */ 1010 static int img_i2c_reset_bus(struct img_i2c *i2c) 1011 { 1012 unsigned long flags; 1013 unsigned long time_left; 1014 1015 spin_lock_irqsave(&i2c->lock, flags); 1016 reinit_completion(&i2c->msg_complete); 1017 img_i2c_reset_start(i2c); 1018 spin_unlock_irqrestore(&i2c->lock, flags); 1019 1020 time_left = wait_for_completion_timeout(&i2c->msg_complete, 1021 IMG_I2C_TIMEOUT); 1022 if (time_left == 0) 1023 return -ETIMEDOUT; 1024 return 0; 1025 } 1026 1027 static int img_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, 1028 int num) 1029 { 1030 struct img_i2c *i2c = i2c_get_adapdata(adap); 1031 bool atomic = false; 1032 int i, ret; 1033 unsigned long time_left; 1034 1035 if (i2c->mode == MODE_SUSPEND) { 1036 WARN(1, "refusing to service transaction in suspended state\n"); 1037 return -EIO; 1038 } 1039 1040 if (i2c->mode == MODE_FATAL) 1041 return -EIO; 1042 1043 for (i = 0; i < num; i++) { 1044 /* 1045 * 0 byte reads are not possible because the slave could try 1046 * and pull the data line low, preventing a stop bit. 1047 */ 1048 if (!msgs[i].len && msgs[i].flags & I2C_M_RD) 1049 return -EIO; 1050 /* 1051 * 0 byte writes are possible and used for probing, but we 1052 * cannot do them in automatic mode, so use atomic mode 1053 * instead. 1054 * 1055 * Also, the I2C_M_IGNORE_NAK mode can only be implemented 1056 * in atomic mode. 1057 */ 1058 if (!msgs[i].len || 1059 (msgs[i].flags & I2C_M_IGNORE_NAK)) 1060 atomic = true; 1061 } 1062 1063 ret = pm_runtime_get_sync(adap->dev.parent); 1064 if (ret < 0) 1065 return ret; 1066 1067 for (i = 0; i < num; i++) { 1068 struct i2c_msg *msg = &msgs[i]; 1069 unsigned long flags; 1070 1071 spin_lock_irqsave(&i2c->lock, flags); 1072 1073 /* 1074 * Make a copy of the message struct. We mustn't modify the 1075 * original or we'll confuse drivers and i2c-dev. 1076 */ 1077 i2c->msg = *msg; 1078 i2c->msg_status = 0; 1079 1080 /* 1081 * After the last message we must have waited for a stop bit. 1082 * Not waiting can cause problems when the clock is disabled 1083 * before the stop bit is sent, and the linux I2C interface 1084 * requires separate transfers not to joined with repeated 1085 * start. 1086 */ 1087 i2c->last_msg = (i == num - 1); 1088 reinit_completion(&i2c->msg_complete); 1089 1090 /* 1091 * Clear line status and all interrupts before starting a 1092 * transfer, as we may have unserviced interrupts from 1093 * previous transfers that might be handled in the context 1094 * of the new transfer. 1095 */ 1096 img_i2c_writel(i2c, SCB_INT_CLEAR_REG, ~0); 1097 img_i2c_writel(i2c, SCB_CLEAR_REG, ~0); 1098 1099 if (atomic) { 1100 img_i2c_atomic_start(i2c); 1101 } else { 1102 /* 1103 * Enable transaction halt if not the last message in 1104 * the queue so that we can control repeated starts. 1105 */ 1106 img_i2c_transaction_halt(i2c, !i2c->last_msg); 1107 1108 if (msg->flags & I2C_M_RD) 1109 img_i2c_read(i2c); 1110 else 1111 img_i2c_write(i2c); 1112 1113 /* 1114 * Release and then enable transaction halt, to 1115 * allow only a single byte to proceed. 1116 * This doesn't have an effect on the initial transfer 1117 * but will allow the following transfers to start 1118 * processing if the previous transfer was marked as 1119 * complete while the i2c block was halted. 1120 */ 1121 img_i2c_transaction_halt(i2c, false); 1122 img_i2c_transaction_halt(i2c, !i2c->last_msg); 1123 } 1124 spin_unlock_irqrestore(&i2c->lock, flags); 1125 1126 time_left = wait_for_completion_timeout(&i2c->msg_complete, 1127 IMG_I2C_TIMEOUT); 1128 del_timer_sync(&i2c->check_timer); 1129 1130 if (time_left == 0) { 1131 dev_err(adap->dev.parent, "i2c transfer timed out\n"); 1132 i2c->msg_status = -ETIMEDOUT; 1133 break; 1134 } 1135 1136 if (i2c->msg_status) 1137 break; 1138 } 1139 1140 pm_runtime_mark_last_busy(adap->dev.parent); 1141 pm_runtime_put_autosuspend(adap->dev.parent); 1142 1143 return i2c->msg_status ? i2c->msg_status : num; 1144 } 1145 1146 static u32 img_i2c_func(struct i2c_adapter *adap) 1147 { 1148 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 1149 } 1150 1151 static const struct i2c_algorithm img_i2c_algo = { 1152 .master_xfer = img_i2c_xfer, 1153 .functionality = img_i2c_func, 1154 }; 1155 1156 static int img_i2c_init(struct img_i2c *i2c) 1157 { 1158 unsigned int clk_khz, bitrate_khz, clk_period, tckh, tckl, tsdh; 1159 unsigned int i, data, prescale, inc, int_bitrate, filt; 1160 struct img_i2c_timings timing; 1161 u32 rev; 1162 int ret; 1163 1164 ret = pm_runtime_get_sync(i2c->adap.dev.parent); 1165 if (ret < 0) 1166 return ret; 1167 1168 rev = img_i2c_readl(i2c, SCB_CORE_REV_REG); 1169 if ((rev & 0x00ffffff) < 0x00020200) { 1170 dev_info(i2c->adap.dev.parent, 1171 "Unknown hardware revision (%d.%d.%d.%d)\n", 1172 (rev >> 24) & 0xff, (rev >> 16) & 0xff, 1173 (rev >> 8) & 0xff, rev & 0xff); 1174 pm_runtime_mark_last_busy(i2c->adap.dev.parent); 1175 pm_runtime_put_autosuspend(i2c->adap.dev.parent); 1176 return -EINVAL; 1177 } 1178 1179 /* Fencing enabled by default. */ 1180 i2c->need_wr_rd_fence = true; 1181 1182 /* Determine what mode we're in from the bitrate */ 1183 timing = timings[0]; 1184 for (i = 0; i < ARRAY_SIZE(timings); i++) { 1185 if (i2c->bitrate <= timings[i].max_bitrate) { 1186 timing = timings[i]; 1187 break; 1188 } 1189 } 1190 if (i2c->bitrate > timings[ARRAY_SIZE(timings) - 1].max_bitrate) { 1191 dev_warn(i2c->adap.dev.parent, 1192 "requested bitrate (%u) is higher than the max bitrate supported (%u)\n", 1193 i2c->bitrate, 1194 timings[ARRAY_SIZE(timings) - 1].max_bitrate); 1195 timing = timings[ARRAY_SIZE(timings) - 1]; 1196 i2c->bitrate = timing.max_bitrate; 1197 } 1198 1199 bitrate_khz = i2c->bitrate / 1000; 1200 clk_khz = clk_get_rate(i2c->scb_clk) / 1000; 1201 1202 /* Find the prescale that would give us that inc (approx delay = 0) */ 1203 prescale = SCB_OPT_INC * clk_khz / (256 * 16 * bitrate_khz); 1204 prescale = clamp_t(unsigned int, prescale, 1, 8); 1205 clk_khz /= prescale; 1206 1207 /* Setup the clock increment value */ 1208 inc = (256 * 16 * bitrate_khz) / clk_khz; 1209 1210 /* 1211 * The clock generation logic allows to filter glitches on the bus. 1212 * This filter is able to remove bus glitches shorter than 50ns. 1213 * If the clock enable rate is greater than 20 MHz, no filtering 1214 * is required, so we need to disable it. 1215 * If it's between the 20-40 MHz range, there's no need to divide 1216 * the clock to get a filter. 1217 */ 1218 if (clk_khz < 20000) { 1219 filt = SCB_FILT_DISABLE; 1220 } else if (clk_khz < 40000) { 1221 filt = SCB_FILT_BYPASS; 1222 } else { 1223 /* Calculate filter clock */ 1224 filt = (64000 / ((clk_khz / 1000) * SCB_FILT_GLITCH)); 1225 1226 /* Scale up if needed */ 1227 if (64000 % ((clk_khz / 1000) * SCB_FILT_GLITCH)) 1228 inc++; 1229 1230 if (filt > SCB_FILT_INC_MASK) 1231 filt = SCB_FILT_INC_MASK; 1232 1233 filt = (filt & SCB_FILT_INC_MASK) << SCB_FILT_INC_SHIFT; 1234 } 1235 data = filt | ((inc & SCB_INC_MASK) << SCB_INC_SHIFT) | (prescale - 1); 1236 img_i2c_writel(i2c, SCB_CLK_SET_REG, data); 1237 1238 /* Obtain the clock period of the fx16 clock in ns */ 1239 clk_period = (256 * 1000000) / (clk_khz * inc); 1240 1241 /* Calculate the bitrate in terms of internal clock pulses */ 1242 int_bitrate = 1000000 / (bitrate_khz * clk_period); 1243 if ((1000000 % (bitrate_khz * clk_period)) >= 1244 ((bitrate_khz * clk_period) / 2)) 1245 int_bitrate++; 1246 1247 /* 1248 * Setup clock duty cycle, start with 50% and adjust TCKH and TCKL 1249 * values from there if they don't meet minimum timing requirements 1250 */ 1251 tckh = int_bitrate / 2; 1252 tckl = int_bitrate - tckh; 1253 1254 /* Adjust TCKH and TCKL values */ 1255 data = DIV_ROUND_UP(timing.tckl, clk_period); 1256 1257 if (tckl < data) { 1258 tckl = data; 1259 tckh = int_bitrate - tckl; 1260 } 1261 1262 if (tckh > 0) 1263 --tckh; 1264 1265 if (tckl > 0) 1266 --tckl; 1267 1268 img_i2c_writel(i2c, SCB_TIME_TCKH_REG, tckh); 1269 img_i2c_writel(i2c, SCB_TIME_TCKL_REG, tckl); 1270 1271 /* Setup TSDH value */ 1272 tsdh = DIV_ROUND_UP(timing.tsdh, clk_period); 1273 1274 if (tsdh > 1) 1275 data = tsdh - 1; 1276 else 1277 data = 0x01; 1278 img_i2c_writel(i2c, SCB_TIME_TSDH_REG, data); 1279 1280 /* This value is used later */ 1281 tsdh = data; 1282 1283 /* Setup TPL value */ 1284 data = timing.tpl / clk_period; 1285 if (data > 0) 1286 --data; 1287 img_i2c_writel(i2c, SCB_TIME_TPL_REG, data); 1288 1289 /* Setup TPH value */ 1290 data = timing.tph / clk_period; 1291 if (data > 0) 1292 --data; 1293 img_i2c_writel(i2c, SCB_TIME_TPH_REG, data); 1294 1295 /* Setup TSDL value to TPL + TSDH + 2 */ 1296 img_i2c_writel(i2c, SCB_TIME_TSDL_REG, data + tsdh + 2); 1297 1298 /* Setup TP2S value */ 1299 data = timing.tp2s / clk_period; 1300 if (data > 0) 1301 --data; 1302 img_i2c_writel(i2c, SCB_TIME_TP2S_REG, data); 1303 1304 img_i2c_writel(i2c, SCB_TIME_TBI_REG, TIMEOUT_TBI); 1305 img_i2c_writel(i2c, SCB_TIME_TSL_REG, TIMEOUT_TSL); 1306 img_i2c_writel(i2c, SCB_TIME_TDL_REG, TIMEOUT_TDL); 1307 1308 /* Take module out of soft reset and enable clocks */ 1309 img_i2c_soft_reset(i2c); 1310 1311 /* Disable all interrupts */ 1312 img_i2c_writel(i2c, SCB_INT_MASK_REG, 0); 1313 1314 /* Clear all interrupts */ 1315 img_i2c_writel(i2c, SCB_INT_CLEAR_REG, ~0); 1316 1317 /* Clear the scb_line_status events */ 1318 img_i2c_writel(i2c, SCB_CLEAR_REG, ~0); 1319 1320 /* Enable interrupts */ 1321 img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable); 1322 1323 /* Perform a synchronous sequence to reset the bus */ 1324 ret = img_i2c_reset_bus(i2c); 1325 1326 pm_runtime_mark_last_busy(i2c->adap.dev.parent); 1327 pm_runtime_put_autosuspend(i2c->adap.dev.parent); 1328 1329 return ret; 1330 } 1331 1332 static int img_i2c_probe(struct platform_device *pdev) 1333 { 1334 struct device_node *node = pdev->dev.of_node; 1335 struct img_i2c *i2c; 1336 struct resource *res; 1337 int irq, ret; 1338 u32 val; 1339 1340 i2c = devm_kzalloc(&pdev->dev, sizeof(struct img_i2c), GFP_KERNEL); 1341 if (!i2c) 1342 return -ENOMEM; 1343 1344 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1345 i2c->base = devm_ioremap_resource(&pdev->dev, res); 1346 if (IS_ERR(i2c->base)) 1347 return PTR_ERR(i2c->base); 1348 1349 irq = platform_get_irq(pdev, 0); 1350 if (irq < 0) { 1351 dev_err(&pdev->dev, "can't get irq number\n"); 1352 return irq; 1353 } 1354 1355 i2c->sys_clk = devm_clk_get(&pdev->dev, "sys"); 1356 if (IS_ERR(i2c->sys_clk)) { 1357 dev_err(&pdev->dev, "can't get system clock\n"); 1358 return PTR_ERR(i2c->sys_clk); 1359 } 1360 1361 i2c->scb_clk = devm_clk_get(&pdev->dev, "scb"); 1362 if (IS_ERR(i2c->scb_clk)) { 1363 dev_err(&pdev->dev, "can't get core clock\n"); 1364 return PTR_ERR(i2c->scb_clk); 1365 } 1366 1367 ret = devm_request_irq(&pdev->dev, irq, img_i2c_isr, 0, 1368 pdev->name, i2c); 1369 if (ret) { 1370 dev_err(&pdev->dev, "can't request irq %d\n", irq); 1371 return ret; 1372 } 1373 1374 /* Set up the exception check timer */ 1375 timer_setup(&i2c->check_timer, img_i2c_check_timer, 0); 1376 1377 i2c->bitrate = timings[0].max_bitrate; 1378 if (!of_property_read_u32(node, "clock-frequency", &val)) 1379 i2c->bitrate = val; 1380 1381 i2c_set_adapdata(&i2c->adap, i2c); 1382 i2c->adap.dev.parent = &pdev->dev; 1383 i2c->adap.dev.of_node = node; 1384 i2c->adap.owner = THIS_MODULE; 1385 i2c->adap.algo = &img_i2c_algo; 1386 i2c->adap.retries = 5; 1387 i2c->adap.nr = pdev->id; 1388 snprintf(i2c->adap.name, sizeof(i2c->adap.name), "IMG SCB I2C"); 1389 1390 img_i2c_switch_mode(i2c, MODE_INACTIVE); 1391 spin_lock_init(&i2c->lock); 1392 init_completion(&i2c->msg_complete); 1393 1394 platform_set_drvdata(pdev, i2c); 1395 1396 pm_runtime_set_autosuspend_delay(&pdev->dev, IMG_I2C_PM_TIMEOUT); 1397 pm_runtime_use_autosuspend(&pdev->dev); 1398 pm_runtime_enable(&pdev->dev); 1399 if (!pm_runtime_enabled(&pdev->dev)) { 1400 ret = img_i2c_runtime_resume(&pdev->dev); 1401 if (ret) 1402 return ret; 1403 } 1404 1405 ret = img_i2c_init(i2c); 1406 if (ret) 1407 goto rpm_disable; 1408 1409 ret = i2c_add_numbered_adapter(&i2c->adap); 1410 if (ret < 0) 1411 goto rpm_disable; 1412 1413 return 0; 1414 1415 rpm_disable: 1416 if (!pm_runtime_enabled(&pdev->dev)) 1417 img_i2c_runtime_suspend(&pdev->dev); 1418 pm_runtime_disable(&pdev->dev); 1419 pm_runtime_dont_use_autosuspend(&pdev->dev); 1420 return ret; 1421 } 1422 1423 static int img_i2c_remove(struct platform_device *dev) 1424 { 1425 struct img_i2c *i2c = platform_get_drvdata(dev); 1426 1427 i2c_del_adapter(&i2c->adap); 1428 pm_runtime_disable(&dev->dev); 1429 if (!pm_runtime_status_suspended(&dev->dev)) 1430 img_i2c_runtime_suspend(&dev->dev); 1431 1432 return 0; 1433 } 1434 1435 static int img_i2c_runtime_suspend(struct device *dev) 1436 { 1437 struct img_i2c *i2c = dev_get_drvdata(dev); 1438 1439 clk_disable_unprepare(i2c->scb_clk); 1440 clk_disable_unprepare(i2c->sys_clk); 1441 1442 return 0; 1443 } 1444 1445 static int img_i2c_runtime_resume(struct device *dev) 1446 { 1447 struct img_i2c *i2c = dev_get_drvdata(dev); 1448 int ret; 1449 1450 ret = clk_prepare_enable(i2c->sys_clk); 1451 if (ret) { 1452 dev_err(dev, "Unable to enable sys clock\n"); 1453 return ret; 1454 } 1455 1456 ret = clk_prepare_enable(i2c->scb_clk); 1457 if (ret) { 1458 dev_err(dev, "Unable to enable scb clock\n"); 1459 clk_disable_unprepare(i2c->sys_clk); 1460 return ret; 1461 } 1462 1463 return 0; 1464 } 1465 1466 #ifdef CONFIG_PM_SLEEP 1467 static int img_i2c_suspend(struct device *dev) 1468 { 1469 struct img_i2c *i2c = dev_get_drvdata(dev); 1470 int ret; 1471 1472 ret = pm_runtime_force_suspend(dev); 1473 if (ret) 1474 return ret; 1475 1476 img_i2c_switch_mode(i2c, MODE_SUSPEND); 1477 1478 return 0; 1479 } 1480 1481 static int img_i2c_resume(struct device *dev) 1482 { 1483 struct img_i2c *i2c = dev_get_drvdata(dev); 1484 int ret; 1485 1486 ret = pm_runtime_force_resume(dev); 1487 if (ret) 1488 return ret; 1489 1490 img_i2c_init(i2c); 1491 1492 return 0; 1493 } 1494 #endif /* CONFIG_PM_SLEEP */ 1495 1496 static const struct dev_pm_ops img_i2c_pm = { 1497 SET_RUNTIME_PM_OPS(img_i2c_runtime_suspend, 1498 img_i2c_runtime_resume, 1499 NULL) 1500 SET_SYSTEM_SLEEP_PM_OPS(img_i2c_suspend, img_i2c_resume) 1501 }; 1502 1503 static const struct of_device_id img_scb_i2c_match[] = { 1504 { .compatible = "img,scb-i2c" }, 1505 { } 1506 }; 1507 MODULE_DEVICE_TABLE(of, img_scb_i2c_match); 1508 1509 static struct platform_driver img_scb_i2c_driver = { 1510 .driver = { 1511 .name = "img-i2c-scb", 1512 .of_match_table = img_scb_i2c_match, 1513 .pm = &img_i2c_pm, 1514 }, 1515 .probe = img_i2c_probe, 1516 .remove = img_i2c_remove, 1517 }; 1518 module_platform_driver(img_scb_i2c_driver); 1519 1520 MODULE_AUTHOR("James Hogan <jhogan@kernel.org>"); 1521 MODULE_DESCRIPTION("IMG host I2C driver"); 1522 MODULE_LICENSE("GPL v2"); 1523