1 /* 2 * drivers/i2c/busses/i2c-ibm_iic.c 3 * 4 * Support for the IIC peripheral on IBM PPC 4xx 5 * 6 * Copyright (c) 2003, 2004 Zultys Technologies. 7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net> 8 * 9 * Copyright (c) 2008 PIKA Technologies 10 * Sean MacLennan <smaclennan@pikatech.com> 11 * 12 * Based on original work by 13 * Ian DaSilva <idasilva@mvista.com> 14 * Armin Kuster <akuster@mvista.com> 15 * Matt Porter <mporter@mvista.com> 16 * 17 * Copyright 2000-2003 MontaVista Software Inc. 18 * 19 * Original driver version was highly leveraged from i2c-elektor.c 20 * 21 * Copyright 1995-97 Simon G. Vogl 22 * 1998-99 Hans Berglund 23 * 24 * With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi> 25 * and even Frodo Looijaard <frodol@dds.nl> 26 * 27 * This program is free software; you can redistribute it and/or modify it 28 * under the terms of the GNU General Public License as published by the 29 * Free Software Foundation; either version 2 of the License, or (at your 30 * option) any later version. 31 * 32 */ 33 34 #include <linux/module.h> 35 #include <linux/kernel.h> 36 #include <linux/ioport.h> 37 #include <linux/delay.h> 38 #include <linux/slab.h> 39 #include <linux/init.h> 40 #include <linux/interrupt.h> 41 #include <asm/irq.h> 42 #include <linux/io.h> 43 #include <linux/i2c.h> 44 #include <linux/of_platform.h> 45 46 #include "i2c-ibm_iic.h" 47 48 #define DRIVER_VERSION "2.2" 49 50 MODULE_DESCRIPTION("IBM IIC driver v" DRIVER_VERSION); 51 MODULE_LICENSE("GPL"); 52 53 static bool iic_force_poll; 54 module_param(iic_force_poll, bool, 0); 55 MODULE_PARM_DESC(iic_force_poll, "Force polling mode"); 56 57 static bool iic_force_fast; 58 module_param(iic_force_fast, bool, 0); 59 MODULE_PARM_DESC(iic_force_fast, "Force fast mode (400 kHz)"); 60 61 #define DBG_LEVEL 0 62 63 #ifdef DBG 64 #undef DBG 65 #endif 66 67 #ifdef DBG2 68 #undef DBG2 69 #endif 70 71 #if DBG_LEVEL > 0 72 # define DBG(f,x...) printk(KERN_DEBUG "ibm-iic" f, ##x) 73 #else 74 # define DBG(f,x...) ((void)0) 75 #endif 76 #if DBG_LEVEL > 1 77 # define DBG2(f,x...) DBG(f, ##x) 78 #else 79 # define DBG2(f,x...) ((void)0) 80 #endif 81 #if DBG_LEVEL > 2 82 static void dump_iic_regs(const char* header, struct ibm_iic_private* dev) 83 { 84 volatile struct iic_regs __iomem *iic = dev->vaddr; 85 printk(KERN_DEBUG "ibm-iic%d: %s\n", dev->idx, header); 86 printk(KERN_DEBUG 87 " cntl = 0x%02x, mdcntl = 0x%02x\n" 88 " sts = 0x%02x, extsts = 0x%02x\n" 89 " clkdiv = 0x%02x, xfrcnt = 0x%02x\n" 90 " xtcntlss = 0x%02x, directcntl = 0x%02x\n", 91 in_8(&iic->cntl), in_8(&iic->mdcntl), in_8(&iic->sts), 92 in_8(&iic->extsts), in_8(&iic->clkdiv), in_8(&iic->xfrcnt), 93 in_8(&iic->xtcntlss), in_8(&iic->directcntl)); 94 } 95 # define DUMP_REGS(h,dev) dump_iic_regs((h),(dev)) 96 #else 97 # define DUMP_REGS(h,dev) ((void)0) 98 #endif 99 100 /* Bus timings (in ns) for bit-banging */ 101 static struct i2c_timings { 102 unsigned int hd_sta; 103 unsigned int su_sto; 104 unsigned int low; 105 unsigned int high; 106 unsigned int buf; 107 } timings [] = { 108 /* Standard mode (100 KHz) */ 109 { 110 .hd_sta = 4000, 111 .su_sto = 4000, 112 .low = 4700, 113 .high = 4000, 114 .buf = 4700, 115 }, 116 /* Fast mode (400 KHz) */ 117 { 118 .hd_sta = 600, 119 .su_sto = 600, 120 .low = 1300, 121 .high = 600, 122 .buf = 1300, 123 }}; 124 125 /* Enable/disable interrupt generation */ 126 static inline void iic_interrupt_mode(struct ibm_iic_private* dev, int enable) 127 { 128 out_8(&dev->vaddr->intmsk, enable ? INTRMSK_EIMTC : 0); 129 } 130 131 /* 132 * Initialize IIC interface. 133 */ 134 static void iic_dev_init(struct ibm_iic_private* dev) 135 { 136 volatile struct iic_regs __iomem *iic = dev->vaddr; 137 138 DBG("%d: init\n", dev->idx); 139 140 /* Clear master address */ 141 out_8(&iic->lmadr, 0); 142 out_8(&iic->hmadr, 0); 143 144 /* Clear slave address */ 145 out_8(&iic->lsadr, 0); 146 out_8(&iic->hsadr, 0); 147 148 /* Clear status & extended status */ 149 out_8(&iic->sts, STS_SCMP | STS_IRQA); 150 out_8(&iic->extsts, EXTSTS_IRQP | EXTSTS_IRQD | EXTSTS_LA 151 | EXTSTS_ICT | EXTSTS_XFRA); 152 153 /* Set clock divider */ 154 out_8(&iic->clkdiv, dev->clckdiv); 155 156 /* Clear transfer count */ 157 out_8(&iic->xfrcnt, 0); 158 159 /* Clear extended control and status */ 160 out_8(&iic->xtcntlss, XTCNTLSS_SRC | XTCNTLSS_SRS | XTCNTLSS_SWC 161 | XTCNTLSS_SWS); 162 163 /* Clear control register */ 164 out_8(&iic->cntl, 0); 165 166 /* Enable interrupts if possible */ 167 iic_interrupt_mode(dev, dev->irq >= 0); 168 169 /* Set mode control */ 170 out_8(&iic->mdcntl, MDCNTL_FMDB | MDCNTL_EINT | MDCNTL_EUBS 171 | (dev->fast_mode ? MDCNTL_FSM : 0)); 172 173 DUMP_REGS("iic_init", dev); 174 } 175 176 /* 177 * Reset IIC interface 178 */ 179 static void iic_dev_reset(struct ibm_iic_private* dev) 180 { 181 volatile struct iic_regs __iomem *iic = dev->vaddr; 182 int i; 183 u8 dc; 184 185 DBG("%d: soft reset\n", dev->idx); 186 DUMP_REGS("reset", dev); 187 188 /* Place chip in the reset state */ 189 out_8(&iic->xtcntlss, XTCNTLSS_SRST); 190 191 /* Check if bus is free */ 192 dc = in_8(&iic->directcntl); 193 if (!DIRCTNL_FREE(dc)){ 194 DBG("%d: trying to regain bus control\n", dev->idx); 195 196 /* Try to set bus free state */ 197 out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC); 198 199 /* Wait until we regain bus control */ 200 for (i = 0; i < 100; ++i){ 201 dc = in_8(&iic->directcntl); 202 if (DIRCTNL_FREE(dc)) 203 break; 204 205 /* Toggle SCL line */ 206 dc ^= DIRCNTL_SCC; 207 out_8(&iic->directcntl, dc); 208 udelay(10); 209 dc ^= DIRCNTL_SCC; 210 out_8(&iic->directcntl, dc); 211 212 /* be nice */ 213 cond_resched(); 214 } 215 } 216 217 /* Remove reset */ 218 out_8(&iic->xtcntlss, 0); 219 220 /* Reinitialize interface */ 221 iic_dev_init(dev); 222 } 223 224 /* 225 * Do 0-length transaction using bit-banging through IIC_DIRECTCNTL register. 226 */ 227 228 /* Wait for SCL and/or SDA to be high */ 229 static int iic_dc_wait(volatile struct iic_regs __iomem *iic, u8 mask) 230 { 231 unsigned long x = jiffies + HZ / 28 + 2; 232 while ((in_8(&iic->directcntl) & mask) != mask){ 233 if (unlikely(time_after(jiffies, x))) 234 return -1; 235 cond_resched(); 236 } 237 return 0; 238 } 239 240 static int iic_smbus_quick(struct ibm_iic_private* dev, const struct i2c_msg* p) 241 { 242 volatile struct iic_regs __iomem *iic = dev->vaddr; 243 const struct i2c_timings* t = &timings[dev->fast_mode ? 1 : 0]; 244 u8 mask, v, sda; 245 int i, res; 246 247 /* Only 7-bit addresses are supported */ 248 if (unlikely(p->flags & I2C_M_TEN)){ 249 DBG("%d: smbus_quick - 10 bit addresses are not supported\n", 250 dev->idx); 251 return -EINVAL; 252 } 253 254 DBG("%d: smbus_quick(0x%02x)\n", dev->idx, p->addr); 255 256 /* Reset IIC interface */ 257 out_8(&iic->xtcntlss, XTCNTLSS_SRST); 258 259 /* Wait for bus to become free */ 260 out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC); 261 if (unlikely(iic_dc_wait(iic, DIRCNTL_MSDA | DIRCNTL_MSC))) 262 goto err; 263 ndelay(t->buf); 264 265 /* START */ 266 out_8(&iic->directcntl, DIRCNTL_SCC); 267 sda = 0; 268 ndelay(t->hd_sta); 269 270 /* Send address */ 271 v = (u8)((p->addr << 1) | ((p->flags & I2C_M_RD) ? 1 : 0)); 272 for (i = 0, mask = 0x80; i < 8; ++i, mask >>= 1){ 273 out_8(&iic->directcntl, sda); 274 ndelay(t->low / 2); 275 sda = (v & mask) ? DIRCNTL_SDAC : 0; 276 out_8(&iic->directcntl, sda); 277 ndelay(t->low / 2); 278 279 out_8(&iic->directcntl, DIRCNTL_SCC | sda); 280 if (unlikely(iic_dc_wait(iic, DIRCNTL_MSC))) 281 goto err; 282 ndelay(t->high); 283 } 284 285 /* ACK */ 286 out_8(&iic->directcntl, sda); 287 ndelay(t->low / 2); 288 out_8(&iic->directcntl, DIRCNTL_SDAC); 289 ndelay(t->low / 2); 290 out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC); 291 if (unlikely(iic_dc_wait(iic, DIRCNTL_MSC))) 292 goto err; 293 res = (in_8(&iic->directcntl) & DIRCNTL_MSDA) ? -EREMOTEIO : 1; 294 ndelay(t->high); 295 296 /* STOP */ 297 out_8(&iic->directcntl, 0); 298 ndelay(t->low); 299 out_8(&iic->directcntl, DIRCNTL_SCC); 300 if (unlikely(iic_dc_wait(iic, DIRCNTL_MSC))) 301 goto err; 302 ndelay(t->su_sto); 303 out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC); 304 305 ndelay(t->buf); 306 307 DBG("%d: smbus_quick -> %s\n", dev->idx, res ? "NACK" : "ACK"); 308 out: 309 /* Remove reset */ 310 out_8(&iic->xtcntlss, 0); 311 312 /* Reinitialize interface */ 313 iic_dev_init(dev); 314 315 return res; 316 err: 317 DBG("%d: smbus_quick - bus is stuck\n", dev->idx); 318 res = -EREMOTEIO; 319 goto out; 320 } 321 322 /* 323 * IIC interrupt handler 324 */ 325 static irqreturn_t iic_handler(int irq, void *dev_id) 326 { 327 struct ibm_iic_private* dev = (struct ibm_iic_private*)dev_id; 328 volatile struct iic_regs __iomem *iic = dev->vaddr; 329 330 DBG2("%d: irq handler, STS = 0x%02x, EXTSTS = 0x%02x\n", 331 dev->idx, in_8(&iic->sts), in_8(&iic->extsts)); 332 333 /* Acknowledge IRQ and wakeup iic_wait_for_tc */ 334 out_8(&iic->sts, STS_IRQA | STS_SCMP); 335 wake_up_interruptible(&dev->wq); 336 337 return IRQ_HANDLED; 338 } 339 340 /* 341 * Get master transfer result and clear errors if any. 342 * Returns the number of actually transferred bytes or error (<0) 343 */ 344 static int iic_xfer_result(struct ibm_iic_private* dev) 345 { 346 volatile struct iic_regs __iomem *iic = dev->vaddr; 347 348 if (unlikely(in_8(&iic->sts) & STS_ERR)){ 349 DBG("%d: xfer error, EXTSTS = 0x%02x\n", dev->idx, 350 in_8(&iic->extsts)); 351 352 /* Clear errors and possible pending IRQs */ 353 out_8(&iic->extsts, EXTSTS_IRQP | EXTSTS_IRQD | 354 EXTSTS_LA | EXTSTS_ICT | EXTSTS_XFRA); 355 356 /* Flush master data buffer */ 357 out_8(&iic->mdcntl, in_8(&iic->mdcntl) | MDCNTL_FMDB); 358 359 /* Is bus free? 360 * If error happened during combined xfer 361 * IIC interface is usually stuck in some strange 362 * state, the only way out - soft reset. 363 */ 364 if ((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE){ 365 DBG("%d: bus is stuck, resetting\n", dev->idx); 366 iic_dev_reset(dev); 367 } 368 return -EREMOTEIO; 369 } 370 else 371 return in_8(&iic->xfrcnt) & XFRCNT_MTC_MASK; 372 } 373 374 /* 375 * Try to abort active transfer. 376 */ 377 static void iic_abort_xfer(struct ibm_iic_private* dev) 378 { 379 volatile struct iic_regs __iomem *iic = dev->vaddr; 380 unsigned long x; 381 382 DBG("%d: iic_abort_xfer\n", dev->idx); 383 384 out_8(&iic->cntl, CNTL_HMT); 385 386 /* 387 * Wait for the abort command to complete. 388 * It's not worth to be optimized, just poll (timeout >= 1 tick) 389 */ 390 x = jiffies + 2; 391 while ((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE){ 392 if (time_after(jiffies, x)){ 393 DBG("%d: abort timeout, resetting...\n", dev->idx); 394 iic_dev_reset(dev); 395 return; 396 } 397 schedule(); 398 } 399 400 /* Just to clear errors */ 401 iic_xfer_result(dev); 402 } 403 404 /* 405 * Wait for master transfer to complete. 406 * It puts current process to sleep until we get interrupt or timeout expires. 407 * Returns the number of transferred bytes or error (<0) 408 */ 409 static int iic_wait_for_tc(struct ibm_iic_private* dev){ 410 411 volatile struct iic_regs __iomem *iic = dev->vaddr; 412 int ret = 0; 413 414 if (dev->irq >= 0){ 415 /* Interrupt mode */ 416 ret = wait_event_interruptible_timeout(dev->wq, 417 !(in_8(&iic->sts) & STS_PT), dev->adap.timeout); 418 419 if (unlikely(ret < 0)) 420 DBG("%d: wait interrupted\n", dev->idx); 421 else if (unlikely(in_8(&iic->sts) & STS_PT)){ 422 DBG("%d: wait timeout\n", dev->idx); 423 ret = -ETIMEDOUT; 424 } 425 } 426 else { 427 /* Polling mode */ 428 unsigned long x = jiffies + dev->adap.timeout; 429 430 while (in_8(&iic->sts) & STS_PT){ 431 if (unlikely(time_after(jiffies, x))){ 432 DBG("%d: poll timeout\n", dev->idx); 433 ret = -ETIMEDOUT; 434 break; 435 } 436 437 if (unlikely(signal_pending(current))){ 438 DBG("%d: poll interrupted\n", dev->idx); 439 ret = -ERESTARTSYS; 440 break; 441 } 442 schedule(); 443 } 444 } 445 446 if (unlikely(ret < 0)) 447 iic_abort_xfer(dev); 448 else 449 ret = iic_xfer_result(dev); 450 451 DBG2("%d: iic_wait_for_tc -> %d\n", dev->idx, ret); 452 453 return ret; 454 } 455 456 /* 457 * Low level master transfer routine 458 */ 459 static int iic_xfer_bytes(struct ibm_iic_private* dev, struct i2c_msg* pm, 460 int combined_xfer) 461 { 462 volatile struct iic_regs __iomem *iic = dev->vaddr; 463 char* buf = pm->buf; 464 int i, j, loops, ret = 0; 465 int len = pm->len; 466 467 u8 cntl = (in_8(&iic->cntl) & CNTL_AMD) | CNTL_PT; 468 if (pm->flags & I2C_M_RD) 469 cntl |= CNTL_RW; 470 471 loops = (len + 3) / 4; 472 for (i = 0; i < loops; ++i, len -= 4){ 473 int count = len > 4 ? 4 : len; 474 u8 cmd = cntl | ((count - 1) << CNTL_TCT_SHIFT); 475 476 if (!(cntl & CNTL_RW)) 477 for (j = 0; j < count; ++j) 478 out_8((void __iomem *)&iic->mdbuf, *buf++); 479 480 if (i < loops - 1) 481 cmd |= CNTL_CHT; 482 else if (combined_xfer) 483 cmd |= CNTL_RPST; 484 485 DBG2("%d: xfer_bytes, %d, CNTL = 0x%02x\n", dev->idx, count, cmd); 486 487 /* Start transfer */ 488 out_8(&iic->cntl, cmd); 489 490 /* Wait for completion */ 491 ret = iic_wait_for_tc(dev); 492 493 if (unlikely(ret < 0)) 494 break; 495 else if (unlikely(ret != count)){ 496 DBG("%d: xfer_bytes, requested %d, transferred %d\n", 497 dev->idx, count, ret); 498 499 /* If it's not a last part of xfer, abort it */ 500 if (combined_xfer || (i < loops - 1)) 501 iic_abort_xfer(dev); 502 503 ret = -EREMOTEIO; 504 break; 505 } 506 507 if (cntl & CNTL_RW) 508 for (j = 0; j < count; ++j) 509 *buf++ = in_8((void __iomem *)&iic->mdbuf); 510 } 511 512 return ret > 0 ? 0 : ret; 513 } 514 515 /* 516 * Set target slave address for master transfer 517 */ 518 static inline void iic_address(struct ibm_iic_private* dev, struct i2c_msg* msg) 519 { 520 volatile struct iic_regs __iomem *iic = dev->vaddr; 521 u16 addr = msg->addr; 522 523 DBG2("%d: iic_address, 0x%03x (%d-bit)\n", dev->idx, 524 addr, msg->flags & I2C_M_TEN ? 10 : 7); 525 526 if (msg->flags & I2C_M_TEN){ 527 out_8(&iic->cntl, CNTL_AMD); 528 out_8(&iic->lmadr, addr); 529 out_8(&iic->hmadr, 0xf0 | ((addr >> 7) & 0x06)); 530 } 531 else { 532 out_8(&iic->cntl, 0); 533 out_8(&iic->lmadr, addr << 1); 534 } 535 } 536 537 static inline int iic_invalid_address(const struct i2c_msg* p) 538 { 539 return (p->addr > 0x3ff) || (!(p->flags & I2C_M_TEN) && (p->addr > 0x7f)); 540 } 541 542 static inline int iic_address_neq(const struct i2c_msg* p1, 543 const struct i2c_msg* p2) 544 { 545 return (p1->addr != p2->addr) 546 || ((p1->flags & I2C_M_TEN) != (p2->flags & I2C_M_TEN)); 547 } 548 549 /* 550 * Generic master transfer entrypoint. 551 * Returns the number of processed messages or error (<0) 552 */ 553 static int iic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 554 { 555 struct ibm_iic_private* dev = (struct ibm_iic_private*)(i2c_get_adapdata(adap)); 556 volatile struct iic_regs __iomem *iic = dev->vaddr; 557 int i, ret = 0; 558 559 DBG2("%d: iic_xfer, %d msg(s)\n", dev->idx, num); 560 561 if (!num) 562 return 0; 563 564 /* Check the sanity of the passed messages. 565 * Uhh, generic i2c layer is more suitable place for such code... 566 */ 567 if (unlikely(iic_invalid_address(&msgs[0]))){ 568 DBG("%d: invalid address 0x%03x (%d-bit)\n", dev->idx, 569 msgs[0].addr, msgs[0].flags & I2C_M_TEN ? 10 : 7); 570 return -EINVAL; 571 } 572 for (i = 0; i < num; ++i){ 573 if (unlikely(msgs[i].len <= 0)){ 574 if (num == 1 && !msgs[0].len){ 575 /* Special case for I2C_SMBUS_QUICK emulation. 576 * IBM IIC doesn't support 0-length transactions 577 * so we have to emulate them using bit-banging. 578 */ 579 return iic_smbus_quick(dev, &msgs[0]); 580 } 581 DBG("%d: invalid len %d in msg[%d]\n", dev->idx, 582 msgs[i].len, i); 583 return -EINVAL; 584 } 585 if (unlikely(iic_address_neq(&msgs[0], &msgs[i]))){ 586 DBG("%d: invalid addr in msg[%d]\n", dev->idx, i); 587 return -EINVAL; 588 } 589 } 590 591 /* Check bus state */ 592 if (unlikely((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE)){ 593 DBG("%d: iic_xfer, bus is not free\n", dev->idx); 594 595 /* Usually it means something serious has happened. 596 * We *cannot* have unfinished previous transfer 597 * so it doesn't make any sense to try to stop it. 598 * Probably we were not able to recover from the 599 * previous error. 600 * The only *reasonable* thing I can think of here 601 * is soft reset. --ebs 602 */ 603 iic_dev_reset(dev); 604 605 if ((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE){ 606 DBG("%d: iic_xfer, bus is still not free\n", dev->idx); 607 return -EREMOTEIO; 608 } 609 } 610 else { 611 /* Flush master data buffer (just in case) */ 612 out_8(&iic->mdcntl, in_8(&iic->mdcntl) | MDCNTL_FMDB); 613 } 614 615 /* Load slave address */ 616 iic_address(dev, &msgs[0]); 617 618 /* Do real transfer */ 619 for (i = 0; i < num && !ret; ++i) 620 ret = iic_xfer_bytes(dev, &msgs[i], i < num - 1); 621 622 return ret < 0 ? ret : num; 623 } 624 625 static u32 iic_func(struct i2c_adapter *adap) 626 { 627 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR; 628 } 629 630 static const struct i2c_algorithm iic_algo = { 631 .master_xfer = iic_xfer, 632 .functionality = iic_func 633 }; 634 635 /* 636 * Calculates IICx_CLCKDIV value for a specific OPB clock frequency 637 */ 638 static inline u8 iic_clckdiv(unsigned int opb) 639 { 640 /* Compatibility kludge, should go away after all cards 641 * are fixed to fill correct value for opbfreq. 642 * Previous driver version used hardcoded divider value 4, 643 * it corresponds to OPB frequency from the range (40, 50] MHz 644 */ 645 if (!opb){ 646 printk(KERN_WARNING "ibm-iic: using compatibility value for OPB freq," 647 " fix your board specific setup\n"); 648 opb = 50000000; 649 } 650 651 /* Convert to MHz */ 652 opb /= 1000000; 653 654 if (opb < 20 || opb > 150){ 655 printk(KERN_WARNING "ibm-iic: invalid OPB clock frequency %u MHz\n", 656 opb); 657 opb = opb < 20 ? 20 : 150; 658 } 659 return (u8)((opb + 9) / 10 - 1); 660 } 661 662 static int iic_request_irq(struct platform_device *ofdev, 663 struct ibm_iic_private *dev) 664 { 665 struct device_node *np = ofdev->dev.of_node; 666 int irq; 667 668 if (iic_force_poll) 669 return 0; 670 671 irq = irq_of_parse_and_map(np, 0); 672 if (!irq) { 673 dev_err(&ofdev->dev, "irq_of_parse_and_map failed\n"); 674 return 0; 675 } 676 677 /* Disable interrupts until we finish initialization, assumes 678 * level-sensitive IRQ setup... 679 */ 680 iic_interrupt_mode(dev, 0); 681 if (request_irq(irq, iic_handler, 0, "IBM IIC", dev)) { 682 dev_err(&ofdev->dev, "request_irq %d failed\n", irq); 683 /* Fallback to the polling mode */ 684 return 0; 685 } 686 687 return irq; 688 } 689 690 /* 691 * Register single IIC interface 692 */ 693 static int iic_probe(struct platform_device *ofdev) 694 { 695 struct device_node *np = ofdev->dev.of_node; 696 struct ibm_iic_private *dev; 697 struct i2c_adapter *adap; 698 const u32 *freq; 699 int ret; 700 701 dev = kzalloc(sizeof(*dev), GFP_KERNEL); 702 if (!dev) { 703 dev_err(&ofdev->dev, "failed to allocate device data\n"); 704 return -ENOMEM; 705 } 706 707 platform_set_drvdata(ofdev, dev); 708 709 dev->vaddr = of_iomap(np, 0); 710 if (dev->vaddr == NULL) { 711 dev_err(&ofdev->dev, "failed to iomap device\n"); 712 ret = -ENXIO; 713 goto error_cleanup; 714 } 715 716 init_waitqueue_head(&dev->wq); 717 718 dev->irq = iic_request_irq(ofdev, dev); 719 if (!dev->irq) 720 dev_warn(&ofdev->dev, "using polling mode\n"); 721 722 /* Board specific settings */ 723 if (iic_force_fast || of_get_property(np, "fast-mode", NULL)) 724 dev->fast_mode = 1; 725 726 freq = of_get_property(np, "clock-frequency", NULL); 727 if (freq == NULL) { 728 freq = of_get_property(np->parent, "clock-frequency", NULL); 729 if (freq == NULL) { 730 dev_err(&ofdev->dev, "Unable to get bus frequency\n"); 731 ret = -EINVAL; 732 goto error_cleanup; 733 } 734 } 735 736 dev->clckdiv = iic_clckdiv(*freq); 737 dev_dbg(&ofdev->dev, "clckdiv = %d\n", dev->clckdiv); 738 739 /* Initialize IIC interface */ 740 iic_dev_init(dev); 741 742 /* Register it with i2c layer */ 743 adap = &dev->adap; 744 adap->dev.parent = &ofdev->dev; 745 adap->dev.of_node = of_node_get(np); 746 strlcpy(adap->name, "IBM IIC", sizeof(adap->name)); 747 i2c_set_adapdata(adap, dev); 748 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 749 adap->algo = &iic_algo; 750 adap->timeout = HZ; 751 752 ret = i2c_add_adapter(adap); 753 if (ret < 0) { 754 dev_err(&ofdev->dev, "failed to register i2c adapter\n"); 755 goto error_cleanup; 756 } 757 758 dev_info(&ofdev->dev, "using %s mode\n", 759 dev->fast_mode ? "fast (400 kHz)" : "standard (100 kHz)"); 760 761 return 0; 762 763 error_cleanup: 764 if (dev->irq) { 765 iic_interrupt_mode(dev, 0); 766 free_irq(dev->irq, dev); 767 } 768 769 if (dev->vaddr) 770 iounmap(dev->vaddr); 771 772 kfree(dev); 773 return ret; 774 } 775 776 /* 777 * Cleanup initialized IIC interface 778 */ 779 static int iic_remove(struct platform_device *ofdev) 780 { 781 struct ibm_iic_private *dev = platform_get_drvdata(ofdev); 782 783 i2c_del_adapter(&dev->adap); 784 785 if (dev->irq) { 786 iic_interrupt_mode(dev, 0); 787 free_irq(dev->irq, dev); 788 } 789 790 iounmap(dev->vaddr); 791 kfree(dev); 792 793 return 0; 794 } 795 796 static const struct of_device_id ibm_iic_match[] = { 797 { .compatible = "ibm,iic", }, 798 {} 799 }; 800 801 static struct platform_driver ibm_iic_driver = { 802 .driver = { 803 .name = "ibm-iic", 804 .owner = THIS_MODULE, 805 .of_match_table = ibm_iic_match, 806 }, 807 .probe = iic_probe, 808 .remove = iic_remove, 809 }; 810 811 module_platform_driver(ibm_iic_driver); 812