1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, 4 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker 5 <mdsxyz123@yahoo.com> 6 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de> 7 Copyright (C) 2010 Intel Corporation, 8 David Woodhouse <dwmw2@infradead.org> 9 10 */ 11 12 /* 13 * Supports the following Intel I/O Controller Hubs (ICH): 14 * 15 * I/O Block I2C 16 * region SMBus Block proc. block 17 * Chip name PCI ID size PEC buffer call read 18 * --------------------------------------------------------------------------- 19 * 82801AA (ICH) 0x2413 16 no no no no 20 * 82801AB (ICH0) 0x2423 16 no no no no 21 * 82801BA (ICH2) 0x2443 16 no no no no 22 * 82801CA (ICH3) 0x2483 32 soft no no no 23 * 82801DB (ICH4) 0x24c3 32 hard yes no no 24 * 82801E (ICH5) 0x24d3 32 hard yes yes yes 25 * 6300ESB 0x25a4 32 hard yes yes yes 26 * 82801F (ICH6) 0x266a 32 hard yes yes yes 27 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes 28 * 82801G (ICH7) 0x27da 32 hard yes yes yes 29 * 82801H (ICH8) 0x283e 32 hard yes yes yes 30 * 82801I (ICH9) 0x2930 32 hard yes yes yes 31 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes 32 * ICH10 0x3a30 32 hard yes yes yes 33 * ICH10 0x3a60 32 hard yes yes yes 34 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes 35 * 6 Series (PCH) 0x1c22 32 hard yes yes yes 36 * Patsburg (PCH) 0x1d22 32 hard yes yes yes 37 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes 38 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes 39 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes 40 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes 41 * Panther Point (PCH) 0x1e22 32 hard yes yes yes 42 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes 43 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes 44 * Avoton (SOC) 0x1f3c 32 hard yes yes yes 45 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes 46 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes 47 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes 48 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes 49 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes 50 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes 51 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes 52 * BayTrail (SOC) 0x0f12 32 hard yes yes yes 53 * Braswell (SOC) 0x2292 32 hard yes yes yes 54 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes 55 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes 56 * DNV (SOC) 0x19df 32 hard yes yes yes 57 * Emmitsburg (PCH) 0x1bc9 32 hard yes yes yes 58 * Broxton (SOC) 0x5ad4 32 hard yes yes yes 59 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes 60 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes 61 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes 62 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes 63 * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes 64 * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes 65 * Cedar Fork (PCH) 0x18df 32 hard yes yes yes 66 * Ice Lake-LP (PCH) 0x34a3 32 hard yes yes yes 67 * Ice Lake-N (PCH) 0x38a3 32 hard yes yes yes 68 * Comet Lake (PCH) 0x02a3 32 hard yes yes yes 69 * Comet Lake-H (PCH) 0x06a3 32 hard yes yes yes 70 * Elkhart Lake (PCH) 0x4b23 32 hard yes yes yes 71 * Tiger Lake-LP (PCH) 0xa0a3 32 hard yes yes yes 72 * Tiger Lake-H (PCH) 0x43a3 32 hard yes yes yes 73 * Jasper Lake (SOC) 0x4da3 32 hard yes yes yes 74 * Comet Lake-V (PCH) 0xa3a3 32 hard yes yes yes 75 * Alder Lake-S (PCH) 0x7aa3 32 hard yes yes yes 76 * Alder Lake-P (PCH) 0x51a3 32 hard yes yes yes 77 * Alder Lake-M (PCH) 0x54a3 32 hard yes yes yes 78 * Raptor Lake-S (PCH) 0x7a23 32 hard yes yes yes 79 * Meteor Lake-P (SOC) 0x7e22 32 hard yes yes yes 80 * 81 * Features supported by this driver: 82 * Software PEC no 83 * Hardware PEC yes 84 * Block buffer yes 85 * Block process call transaction yes 86 * I2C block read transaction yes (doesn't use the block buffer) 87 * Slave mode no 88 * SMBus Host Notify yes 89 * Interrupt processing yes 90 * 91 * See the file Documentation/i2c/busses/i2c-i801.rst for details. 92 */ 93 94 #define DRV_NAME "i801_smbus" 95 96 #include <linux/interrupt.h> 97 #include <linux/module.h> 98 #include <linux/pci.h> 99 #include <linux/kernel.h> 100 #include <linux/stddef.h> 101 #include <linux/delay.h> 102 #include <linux/ioport.h> 103 #include <linux/init.h> 104 #include <linux/i2c.h> 105 #include <linux/i2c-smbus.h> 106 #include <linux/acpi.h> 107 #include <linux/io.h> 108 #include <linux/dmi.h> 109 #include <linux/slab.h> 110 #include <linux/string.h> 111 #include <linux/completion.h> 112 #include <linux/err.h> 113 #include <linux/platform_device.h> 114 #include <linux/platform_data/itco_wdt.h> 115 #include <linux/platform_data/x86/p2sb.h> 116 #include <linux/pm_runtime.h> 117 #include <linux/mutex.h> 118 119 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 120 #include <linux/gpio/machine.h> 121 #include <linux/platform_data/i2c-mux-gpio.h> 122 #endif 123 124 /* I801 SMBus address offsets */ 125 #define SMBHSTSTS(p) (0 + (p)->smba) 126 #define SMBHSTCNT(p) (2 + (p)->smba) 127 #define SMBHSTCMD(p) (3 + (p)->smba) 128 #define SMBHSTADD(p) (4 + (p)->smba) 129 #define SMBHSTDAT0(p) (5 + (p)->smba) 130 #define SMBHSTDAT1(p) (6 + (p)->smba) 131 #define SMBBLKDAT(p) (7 + (p)->smba) 132 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */ 133 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */ 134 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */ 135 #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */ 136 #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */ 137 #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */ 138 139 /* PCI Address Constants */ 140 #define SMBBAR 4 141 #define SMBHSTCFG 0x040 142 #define TCOBASE 0x050 143 #define TCOCTL 0x054 144 145 #define SBREG_SMBCTRL 0xc6000c 146 #define SBREG_SMBCTRL_DNV 0xcf000c 147 148 /* Host configuration bits for SMBHSTCFG */ 149 #define SMBHSTCFG_HST_EN BIT(0) 150 #define SMBHSTCFG_SMB_SMI_EN BIT(1) 151 #define SMBHSTCFG_I2C_EN BIT(2) 152 #define SMBHSTCFG_SPD_WD BIT(4) 153 154 /* TCO configuration bits for TCOCTL */ 155 #define TCOCTL_EN BIT(8) 156 157 /* Auxiliary status register bits, ICH4+ only */ 158 #define SMBAUXSTS_CRCE BIT(0) 159 #define SMBAUXSTS_STCO BIT(1) 160 161 /* Auxiliary control register bits, ICH4+ only */ 162 #define SMBAUXCTL_CRC BIT(0) 163 #define SMBAUXCTL_E32B BIT(1) 164 165 /* I801 command constants */ 166 #define I801_QUICK 0x00 167 #define I801_BYTE 0x04 168 #define I801_BYTE_DATA 0x08 169 #define I801_WORD_DATA 0x0C 170 #define I801_PROC_CALL 0x10 171 #define I801_BLOCK_DATA 0x14 172 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ 173 #define I801_BLOCK_PROC_CALL 0x1C 174 175 /* I801 Host Control register bits */ 176 #define SMBHSTCNT_INTREN BIT(0) 177 #define SMBHSTCNT_KILL BIT(1) 178 #define SMBHSTCNT_LAST_BYTE BIT(5) 179 #define SMBHSTCNT_START BIT(6) 180 #define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */ 181 182 /* I801 Hosts Status register bits */ 183 #define SMBHSTSTS_BYTE_DONE BIT(7) 184 #define SMBHSTSTS_INUSE_STS BIT(6) 185 #define SMBHSTSTS_SMBALERT_STS BIT(5) 186 #define SMBHSTSTS_FAILED BIT(4) 187 #define SMBHSTSTS_BUS_ERR BIT(3) 188 #define SMBHSTSTS_DEV_ERR BIT(2) 189 #define SMBHSTSTS_INTR BIT(1) 190 #define SMBHSTSTS_HOST_BUSY BIT(0) 191 192 /* Host Notify Status register bits */ 193 #define SMBSLVSTS_HST_NTFY_STS BIT(0) 194 195 /* Host Notify Command register bits */ 196 #define SMBSLVCMD_SMBALERT_DISABLE BIT(2) 197 #define SMBSLVCMD_HST_NTFY_INTREN BIT(0) 198 199 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \ 200 SMBHSTSTS_DEV_ERR) 201 202 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \ 203 STATUS_ERROR_FLAGS) 204 205 /* Older devices have their ID defined in <linux/pci_ids.h> */ 206 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS 0x02a3 207 #define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS 0x06a3 208 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12 209 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df 210 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df 211 #define PCI_DEVICE_ID_INTEL_EBG_SMBUS 0x1bc9 212 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 213 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 214 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */ 215 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70 216 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71 217 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72 218 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 219 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c 220 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292 221 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 222 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0 223 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4 224 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS 0x34a3 225 #define PCI_DEVICE_ID_INTEL_ICELAKE_N_SMBUS 0x38a3 226 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 227 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS 0x43a3 228 #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS 0x4b23 229 #define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS 0x4da3 230 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS 0x51a3 231 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS 0x54a3 232 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4 233 #define PCI_DEVICE_ID_INTEL_RAPTOR_LAKE_S_SMBUS 0x7a23 234 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS 0x7aa3 235 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_P_SMBUS 0x7e22 236 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 237 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2 238 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22 239 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d 240 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e 241 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f 242 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22 243 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2 244 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23 245 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3 246 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS 0xa0a3 247 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123 248 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3 249 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223 250 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3 251 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323 252 #define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS 0xa3a3 253 254 struct i801_mux_config { 255 char *gpio_chip; 256 unsigned values[3]; 257 int n_values; 258 unsigned classes[3]; 259 unsigned gpios[2]; /* Relative to gpio_chip->base */ 260 int n_gpios; 261 }; 262 263 struct i801_priv { 264 struct i2c_adapter adapter; 265 unsigned long smba; 266 unsigned char original_hstcfg; 267 unsigned char original_hstcnt; 268 unsigned char original_slvcmd; 269 struct pci_dev *pci_dev; 270 unsigned int features; 271 272 /* isr processing */ 273 struct completion done; 274 u8 status; 275 276 /* Command state used by isr for byte-by-byte block transactions */ 277 u8 cmd; 278 bool is_read; 279 int count; 280 int len; 281 u8 *data; 282 283 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 284 const struct i801_mux_config *mux_drvdata; 285 struct platform_device *mux_pdev; 286 struct gpiod_lookup_table *lookup; 287 #endif 288 struct platform_device *tco_pdev; 289 290 /* 291 * If set to true the host controller registers are reserved for 292 * ACPI AML use. Protected by acpi_lock. 293 */ 294 bool acpi_reserved; 295 struct mutex acpi_lock; 296 }; 297 298 #define FEATURE_SMBUS_PEC BIT(0) 299 #define FEATURE_BLOCK_BUFFER BIT(1) 300 #define FEATURE_BLOCK_PROC BIT(2) 301 #define FEATURE_I2C_BLOCK_READ BIT(3) 302 #define FEATURE_IRQ BIT(4) 303 #define FEATURE_HOST_NOTIFY BIT(5) 304 /* Not really a feature, but it's convenient to handle it as such */ 305 #define FEATURE_IDF BIT(15) 306 #define FEATURE_TCO_SPT BIT(16) 307 #define FEATURE_TCO_CNL BIT(17) 308 309 static const char *i801_feature_names[] = { 310 "SMBus PEC", 311 "Block buffer", 312 "Block process call", 313 "I2C block read", 314 "Interrupt", 315 "SMBus Host Notify", 316 }; 317 318 static unsigned int disable_features; 319 module_param(disable_features, uint, S_IRUGO | S_IWUSR); 320 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n" 321 "\t\t 0x01 disable SMBus PEC\n" 322 "\t\t 0x02 disable the block buffer\n" 323 "\t\t 0x08 disable the I2C block read functionality\n" 324 "\t\t 0x10 don't use interrupts\n" 325 "\t\t 0x20 disable SMBus Host Notify "); 326 327 /* Make sure the SMBus host is ready to start transmitting. 328 Return 0 if it is, -EBUSY if it is not. */ 329 static int i801_check_pre(struct i801_priv *priv) 330 { 331 int status; 332 333 status = inb_p(SMBHSTSTS(priv)); 334 if (status & SMBHSTSTS_HOST_BUSY) { 335 pci_err(priv->pci_dev, "SMBus is busy, can't use it!\n"); 336 return -EBUSY; 337 } 338 339 status &= STATUS_FLAGS; 340 if (status) { 341 pci_dbg(priv->pci_dev, "Clearing status flags (%02x)\n", status); 342 outb_p(status, SMBHSTSTS(priv)); 343 } 344 345 /* 346 * Clear CRC status if needed. 347 * During normal operation, i801_check_post() takes care 348 * of it after every operation. We do it here only in case 349 * the hardware was already in this state when the driver 350 * started. 351 */ 352 if (priv->features & FEATURE_SMBUS_PEC) { 353 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE; 354 if (status) { 355 pci_dbg(priv->pci_dev, "Clearing aux status flags (%02x)\n", status); 356 outb_p(status, SMBAUXSTS(priv)); 357 } 358 } 359 360 return 0; 361 } 362 363 static int i801_check_post(struct i801_priv *priv, int status) 364 { 365 int result = 0; 366 367 /* 368 * If the SMBus is still busy, we give up 369 */ 370 if (unlikely(status < 0)) { 371 dev_err(&priv->pci_dev->dev, "Transaction timeout\n"); 372 /* try to stop the current command */ 373 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n"); 374 outb_p(SMBHSTCNT_KILL, SMBHSTCNT(priv)); 375 usleep_range(1000, 2000); 376 outb_p(0, SMBHSTCNT(priv)); 377 378 /* Check if it worked */ 379 status = inb_p(SMBHSTSTS(priv)); 380 if ((status & SMBHSTSTS_HOST_BUSY) || 381 !(status & SMBHSTSTS_FAILED)) 382 dev_err(&priv->pci_dev->dev, 383 "Failed terminating the transaction\n"); 384 return -ETIMEDOUT; 385 } 386 387 if (status & SMBHSTSTS_FAILED) { 388 result = -EIO; 389 dev_err(&priv->pci_dev->dev, "Transaction failed\n"); 390 } 391 if (status & SMBHSTSTS_DEV_ERR) { 392 /* 393 * This may be a PEC error, check and clear it. 394 * 395 * AUXSTS is handled differently from HSTSTS. 396 * For HSTSTS, i801_isr() or i801_wait_intr() 397 * has already cleared the error bits in hardware, 398 * and we are passed a copy of the original value 399 * in "status". 400 * For AUXSTS, the hardware register is left 401 * for us to handle here. 402 * This is asymmetric, slightly iffy, but safe, 403 * since all this code is serialized and the CRCE 404 * bit is harmless as long as it's cleared before 405 * the next operation. 406 */ 407 if ((priv->features & FEATURE_SMBUS_PEC) && 408 (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) { 409 outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv)); 410 result = -EBADMSG; 411 dev_dbg(&priv->pci_dev->dev, "PEC error\n"); 412 } else { 413 result = -ENXIO; 414 dev_dbg(&priv->pci_dev->dev, "No response\n"); 415 } 416 } 417 if (status & SMBHSTSTS_BUS_ERR) { 418 result = -EAGAIN; 419 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n"); 420 } 421 422 return result; 423 } 424 425 /* Wait for BUSY being cleared and either INTR or an error flag being set */ 426 static int i801_wait_intr(struct i801_priv *priv) 427 { 428 unsigned long timeout = jiffies + priv->adapter.timeout; 429 int status, busy; 430 431 do { 432 usleep_range(250, 500); 433 status = inb_p(SMBHSTSTS(priv)); 434 busy = status & SMBHSTSTS_HOST_BUSY; 435 status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR; 436 if (!busy && status) 437 return status & STATUS_ERROR_FLAGS; 438 } while (time_is_after_eq_jiffies(timeout)); 439 440 return -ETIMEDOUT; 441 } 442 443 /* Wait for either BYTE_DONE or an error flag being set */ 444 static int i801_wait_byte_done(struct i801_priv *priv) 445 { 446 unsigned long timeout = jiffies + priv->adapter.timeout; 447 int status; 448 449 do { 450 usleep_range(250, 500); 451 status = inb_p(SMBHSTSTS(priv)); 452 if (status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) 453 return status & STATUS_ERROR_FLAGS; 454 } while (time_is_after_eq_jiffies(timeout)); 455 456 return -ETIMEDOUT; 457 } 458 459 static int i801_transaction(struct i801_priv *priv, int xact) 460 { 461 unsigned long result; 462 const struct i2c_adapter *adap = &priv->adapter; 463 464 if (priv->features & FEATURE_IRQ) { 465 reinit_completion(&priv->done); 466 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START, 467 SMBHSTCNT(priv)); 468 result = wait_for_completion_timeout(&priv->done, adap->timeout); 469 return result ? priv->status : -ETIMEDOUT; 470 } 471 472 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv)); 473 474 return i801_wait_intr(priv); 475 } 476 477 static int i801_block_transaction_by_block(struct i801_priv *priv, 478 union i2c_smbus_data *data, 479 char read_write, int command) 480 { 481 int i, len, status, xact; 482 483 switch (command) { 484 case I2C_SMBUS_BLOCK_PROC_CALL: 485 xact = I801_BLOCK_PROC_CALL; 486 break; 487 case I2C_SMBUS_BLOCK_DATA: 488 xact = I801_BLOCK_DATA; 489 break; 490 default: 491 return -EOPNOTSUPP; 492 } 493 494 /* Set block buffer mode */ 495 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv)); 496 497 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ 498 499 if (read_write == I2C_SMBUS_WRITE) { 500 len = data->block[0]; 501 outb_p(len, SMBHSTDAT0(priv)); 502 for (i = 0; i < len; i++) 503 outb_p(data->block[i+1], SMBBLKDAT(priv)); 504 } 505 506 status = i801_transaction(priv, xact); 507 if (status) 508 goto out; 509 510 if (read_write == I2C_SMBUS_READ || 511 command == I2C_SMBUS_BLOCK_PROC_CALL) { 512 len = inb_p(SMBHSTDAT0(priv)); 513 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { 514 status = -EPROTO; 515 goto out; 516 } 517 518 data->block[0] = len; 519 for (i = 0; i < len; i++) 520 data->block[i + 1] = inb_p(SMBBLKDAT(priv)); 521 } 522 out: 523 outb_p(inb_p(SMBAUXCTL(priv)) & ~SMBAUXCTL_E32B, SMBAUXCTL(priv)); 524 return status; 525 } 526 527 static void i801_isr_byte_done(struct i801_priv *priv) 528 { 529 if (priv->is_read) { 530 /* For SMBus block reads, length is received with first byte */ 531 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) && 532 (priv->count == 0)) { 533 priv->len = inb_p(SMBHSTDAT0(priv)); 534 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) { 535 dev_err(&priv->pci_dev->dev, 536 "Illegal SMBus block read size %d\n", 537 priv->len); 538 /* FIXME: Recover */ 539 priv->len = I2C_SMBUS_BLOCK_MAX; 540 } 541 priv->data[-1] = priv->len; 542 } 543 544 /* Read next byte */ 545 if (priv->count < priv->len) 546 priv->data[priv->count++] = inb(SMBBLKDAT(priv)); 547 else 548 dev_dbg(&priv->pci_dev->dev, 549 "Discarding extra byte on block read\n"); 550 551 /* Set LAST_BYTE for last byte of read transaction */ 552 if (priv->count == priv->len - 1) 553 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE, 554 SMBHSTCNT(priv)); 555 } else if (priv->count < priv->len - 1) { 556 /* Write next byte, except for IRQ after last byte */ 557 outb_p(priv->data[++priv->count], SMBBLKDAT(priv)); 558 } 559 } 560 561 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv) 562 { 563 unsigned short addr; 564 565 addr = inb_p(SMBNTFDADD(priv)) >> 1; 566 567 /* 568 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba) 569 * always returns 0. Our current implementation doesn't provide 570 * data, so we just ignore it. 571 */ 572 i2c_handle_smbus_host_notify(&priv->adapter, addr); 573 574 /* clear Host Notify bit and return */ 575 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 576 return IRQ_HANDLED; 577 } 578 579 /* 580 * There are three kinds of interrupts: 581 * 582 * 1) i801 signals transaction completion with one of these interrupts: 583 * INTR - Success 584 * DEV_ERR - Invalid command, NAK or communication timeout 585 * BUS_ERR - SMI# transaction collision 586 * FAILED - transaction was canceled due to a KILL request 587 * When any of these occur, update ->status and signal completion. 588 * 589 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt 590 * occurs for each byte of a byte-by-byte to prepare the next byte. 591 * 592 * 3) Host Notify interrupts 593 */ 594 static irqreturn_t i801_isr(int irq, void *dev_id) 595 { 596 struct i801_priv *priv = dev_id; 597 u16 pcists; 598 u8 status; 599 600 /* Confirm this is our interrupt */ 601 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists); 602 if (!(pcists & PCI_STATUS_INTERRUPT)) 603 return IRQ_NONE; 604 605 if (priv->features & FEATURE_HOST_NOTIFY) { 606 status = inb_p(SMBSLVSTS(priv)); 607 if (status & SMBSLVSTS_HST_NTFY_STS) 608 return i801_host_notify_isr(priv); 609 } 610 611 status = inb_p(SMBHSTSTS(priv)); 612 if ((status & (SMBHSTSTS_BYTE_DONE | STATUS_ERROR_FLAGS)) == SMBHSTSTS_BYTE_DONE) 613 i801_isr_byte_done(priv); 614 615 /* 616 * Clear IRQ sources: SMB_ALERT status is set after signal assertion 617 * independently of the interrupt generation being blocked or not 618 * so clear it always when the status is set. 619 */ 620 status &= STATUS_FLAGS | SMBHSTSTS_SMBALERT_STS; 621 outb_p(status, SMBHSTSTS(priv)); 622 623 status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR; 624 if (status) { 625 priv->status = status & STATUS_ERROR_FLAGS; 626 complete(&priv->done); 627 } 628 629 return IRQ_HANDLED; 630 } 631 632 /* 633 * For "byte-by-byte" block transactions: 634 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1 635 * I2C read uses cmd=I801_I2C_BLOCK_DATA 636 */ 637 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, 638 union i2c_smbus_data *data, 639 char read_write, int command) 640 { 641 int i, len; 642 int smbcmd; 643 int status; 644 unsigned long result; 645 const struct i2c_adapter *adap = &priv->adapter; 646 647 if (command == I2C_SMBUS_BLOCK_PROC_CALL) 648 return -EOPNOTSUPP; 649 650 len = data->block[0]; 651 652 if (read_write == I2C_SMBUS_WRITE) { 653 outb_p(len, SMBHSTDAT0(priv)); 654 outb_p(data->block[1], SMBBLKDAT(priv)); 655 } 656 657 if (command == I2C_SMBUS_I2C_BLOCK_DATA && 658 read_write == I2C_SMBUS_READ) 659 smbcmd = I801_I2C_BLOCK_DATA; 660 else 661 smbcmd = I801_BLOCK_DATA; 662 663 if (priv->features & FEATURE_IRQ) { 664 priv->is_read = (read_write == I2C_SMBUS_READ); 665 if (len == 1 && priv->is_read) 666 smbcmd |= SMBHSTCNT_LAST_BYTE; 667 priv->cmd = smbcmd | SMBHSTCNT_INTREN; 668 priv->len = len; 669 priv->count = 0; 670 priv->data = &data->block[1]; 671 672 reinit_completion(&priv->done); 673 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv)); 674 result = wait_for_completion_timeout(&priv->done, adap->timeout); 675 return result ? priv->status : -ETIMEDOUT; 676 } 677 678 for (i = 1; i <= len; i++) { 679 if (i == len && read_write == I2C_SMBUS_READ) 680 smbcmd |= SMBHSTCNT_LAST_BYTE; 681 outb_p(smbcmd, SMBHSTCNT(priv)); 682 683 if (i == 1) 684 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START, 685 SMBHSTCNT(priv)); 686 687 status = i801_wait_byte_done(priv); 688 if (status) 689 return status; 690 691 if (i == 1 && read_write == I2C_SMBUS_READ 692 && command != I2C_SMBUS_I2C_BLOCK_DATA) { 693 len = inb_p(SMBHSTDAT0(priv)); 694 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { 695 dev_err(&priv->pci_dev->dev, 696 "Illegal SMBus block read size %d\n", 697 len); 698 /* Recover */ 699 while (inb_p(SMBHSTSTS(priv)) & 700 SMBHSTSTS_HOST_BUSY) 701 outb_p(SMBHSTSTS_BYTE_DONE, 702 SMBHSTSTS(priv)); 703 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); 704 return -EPROTO; 705 } 706 data->block[0] = len; 707 } 708 709 /* Retrieve/store value in SMBBLKDAT */ 710 if (read_write == I2C_SMBUS_READ) 711 data->block[i] = inb_p(SMBBLKDAT(priv)); 712 if (read_write == I2C_SMBUS_WRITE && i+1 <= len) 713 outb_p(data->block[i+1], SMBBLKDAT(priv)); 714 715 /* signals SMBBLKDAT ready */ 716 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 717 } 718 719 return i801_wait_intr(priv); 720 } 721 722 static void i801_set_hstadd(struct i801_priv *priv, u8 addr, char read_write) 723 { 724 outb_p((addr << 1) | (read_write & 0x01), SMBHSTADD(priv)); 725 } 726 727 /* Single value transaction function */ 728 static int i801_simple_transaction(struct i801_priv *priv, union i2c_smbus_data *data, 729 u8 addr, u8 hstcmd, char read_write, int command) 730 { 731 int xact, ret; 732 733 switch (command) { 734 case I2C_SMBUS_QUICK: 735 i801_set_hstadd(priv, addr, read_write); 736 xact = I801_QUICK; 737 break; 738 case I2C_SMBUS_BYTE: 739 i801_set_hstadd(priv, addr, read_write); 740 if (read_write == I2C_SMBUS_WRITE) 741 outb_p(hstcmd, SMBHSTCMD(priv)); 742 xact = I801_BYTE; 743 break; 744 case I2C_SMBUS_BYTE_DATA: 745 i801_set_hstadd(priv, addr, read_write); 746 if (read_write == I2C_SMBUS_WRITE) 747 outb_p(data->byte, SMBHSTDAT0(priv)); 748 outb_p(hstcmd, SMBHSTCMD(priv)); 749 xact = I801_BYTE_DATA; 750 break; 751 case I2C_SMBUS_WORD_DATA: 752 i801_set_hstadd(priv, addr, read_write); 753 if (read_write == I2C_SMBUS_WRITE) { 754 outb_p(data->word & 0xff, SMBHSTDAT0(priv)); 755 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); 756 } 757 outb_p(hstcmd, SMBHSTCMD(priv)); 758 xact = I801_WORD_DATA; 759 break; 760 case I2C_SMBUS_PROC_CALL: 761 i801_set_hstadd(priv, addr, I2C_SMBUS_WRITE); 762 outb_p(data->word & 0xff, SMBHSTDAT0(priv)); 763 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); 764 outb_p(hstcmd, SMBHSTCMD(priv)); 765 read_write = I2C_SMBUS_READ; 766 xact = I801_PROC_CALL; 767 break; 768 default: 769 pci_err(priv->pci_dev, "Unsupported transaction %d\n", command); 770 return -EOPNOTSUPP; 771 } 772 773 ret = i801_transaction(priv, xact); 774 if (ret || read_write == I2C_SMBUS_WRITE) 775 return ret; 776 777 switch (command) { 778 case I2C_SMBUS_BYTE: 779 case I2C_SMBUS_BYTE_DATA: 780 data->byte = inb_p(SMBHSTDAT0(priv)); 781 break; 782 case I2C_SMBUS_WORD_DATA: 783 case I2C_SMBUS_PROC_CALL: 784 data->word = inb_p(SMBHSTDAT0(priv)) + 785 (inb_p(SMBHSTDAT1(priv)) << 8); 786 break; 787 } 788 789 return 0; 790 } 791 792 /* Block transaction function */ 793 static int i801_block_transaction(struct i801_priv *priv, union i2c_smbus_data *data, 794 u8 addr, u8 hstcmd, char read_write, int command) 795 { 796 int result = 0; 797 unsigned char hostc; 798 799 if (read_write == I2C_SMBUS_READ && command == I2C_SMBUS_BLOCK_DATA) 800 data->block[0] = I2C_SMBUS_BLOCK_MAX; 801 else if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX) 802 return -EPROTO; 803 804 switch (command) { 805 case I2C_SMBUS_BLOCK_DATA: 806 i801_set_hstadd(priv, addr, read_write); 807 outb_p(hstcmd, SMBHSTCMD(priv)); 808 break; 809 case I2C_SMBUS_I2C_BLOCK_DATA: 810 /* 811 * NB: page 240 of ICH5 datasheet shows that the R/#W 812 * bit should be cleared here, even when reading. 813 * However if SPD Write Disable is set (Lynx Point and later), 814 * the read will fail if we don't set the R/#W bit. 815 */ 816 i801_set_hstadd(priv, addr, 817 priv->original_hstcfg & SMBHSTCFG_SPD_WD ? 818 read_write : I2C_SMBUS_WRITE); 819 if (read_write == I2C_SMBUS_READ) { 820 /* NB: page 240 of ICH5 datasheet also shows 821 * that DATA1 is the cmd field when reading 822 */ 823 outb_p(hstcmd, SMBHSTDAT1(priv)); 824 } else 825 outb_p(hstcmd, SMBHSTCMD(priv)); 826 827 if (read_write == I2C_SMBUS_WRITE) { 828 /* set I2C_EN bit in configuration register */ 829 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc); 830 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, 831 hostc | SMBHSTCFG_I2C_EN); 832 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) { 833 dev_err(&priv->pci_dev->dev, 834 "I2C block read is unsupported!\n"); 835 return -EOPNOTSUPP; 836 } 837 break; 838 case I2C_SMBUS_BLOCK_PROC_CALL: 839 /* Needs to be flagged as write transaction */ 840 i801_set_hstadd(priv, addr, I2C_SMBUS_WRITE); 841 outb_p(hstcmd, SMBHSTCMD(priv)); 842 break; 843 } 844 845 /* Experience has shown that the block buffer can only be used for 846 SMBus (not I2C) block transactions, even though the datasheet 847 doesn't mention this limitation. */ 848 if ((priv->features & FEATURE_BLOCK_BUFFER) && 849 command != I2C_SMBUS_I2C_BLOCK_DATA) 850 result = i801_block_transaction_by_block(priv, data, 851 read_write, 852 command); 853 else 854 result = i801_block_transaction_byte_by_byte(priv, data, 855 read_write, 856 command); 857 858 if (command == I2C_SMBUS_I2C_BLOCK_DATA 859 && read_write == I2C_SMBUS_WRITE) { 860 /* restore saved configuration register value */ 861 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc); 862 } 863 return result; 864 } 865 866 /* Return negative errno on error. */ 867 static s32 i801_access(struct i2c_adapter *adap, u16 addr, 868 unsigned short flags, char read_write, u8 command, 869 int size, union i2c_smbus_data *data) 870 { 871 int hwpec, ret; 872 struct i801_priv *priv = i2c_get_adapdata(adap); 873 874 mutex_lock(&priv->acpi_lock); 875 if (priv->acpi_reserved) { 876 mutex_unlock(&priv->acpi_lock); 877 return -EBUSY; 878 } 879 880 pm_runtime_get_sync(&priv->pci_dev->dev); 881 882 ret = i801_check_pre(priv); 883 if (ret) 884 goto out; 885 886 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) 887 && size != I2C_SMBUS_QUICK 888 && size != I2C_SMBUS_I2C_BLOCK_DATA; 889 890 if (hwpec) /* enable/disable hardware PEC */ 891 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv)); 892 else 893 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC), 894 SMBAUXCTL(priv)); 895 896 if (size == I2C_SMBUS_BLOCK_DATA || 897 size == I2C_SMBUS_I2C_BLOCK_DATA || 898 size == I2C_SMBUS_BLOCK_PROC_CALL) 899 ret = i801_block_transaction(priv, data, addr, command, read_write, size); 900 else 901 ret = i801_simple_transaction(priv, data, addr, command, read_write, size); 902 903 ret = i801_check_post(priv, ret); 904 905 /* Some BIOSes don't like it when PEC is enabled at reboot or resume 906 * time, so we forcibly disable it after every transaction. 907 */ 908 if (hwpec) 909 outb_p(inb_p(SMBAUXCTL(priv)) & ~SMBAUXCTL_CRC, SMBAUXCTL(priv)); 910 out: 911 /* 912 * Unlock the SMBus device for use by BIOS/ACPI, 913 * and clear status flags if not done already. 914 */ 915 outb_p(SMBHSTSTS_INUSE_STS | STATUS_FLAGS, SMBHSTSTS(priv)); 916 917 pm_runtime_mark_last_busy(&priv->pci_dev->dev); 918 pm_runtime_put_autosuspend(&priv->pci_dev->dev); 919 mutex_unlock(&priv->acpi_lock); 920 return ret; 921 } 922 923 924 static u32 i801_func(struct i2c_adapter *adapter) 925 { 926 struct i801_priv *priv = i2c_get_adapdata(adapter); 927 928 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 929 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 930 I2C_FUNC_SMBUS_PROC_CALL | 931 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | 932 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | 933 ((priv->features & FEATURE_BLOCK_PROC) ? 934 I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) | 935 ((priv->features & FEATURE_I2C_BLOCK_READ) ? 936 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) | 937 ((priv->features & FEATURE_HOST_NOTIFY) ? 938 I2C_FUNC_SMBUS_HOST_NOTIFY : 0); 939 } 940 941 static void i801_enable_host_notify(struct i2c_adapter *adapter) 942 { 943 struct i801_priv *priv = i2c_get_adapdata(adapter); 944 945 if (!(priv->features & FEATURE_HOST_NOTIFY)) 946 return; 947 948 /* 949 * Enable host notify interrupt and block the generation of interrupt 950 * from the SMB_ALERT signal because the driver does not support 951 * SMBus Alert. 952 */ 953 outb_p(SMBSLVCMD_HST_NTFY_INTREN | SMBSLVCMD_SMBALERT_DISABLE | 954 priv->original_slvcmd, SMBSLVCMD(priv)); 955 956 /* clear Host Notify bit to allow a new notification */ 957 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 958 } 959 960 static void i801_disable_host_notify(struct i801_priv *priv) 961 { 962 if (!(priv->features & FEATURE_HOST_NOTIFY)) 963 return; 964 965 outb_p(priv->original_slvcmd, SMBSLVCMD(priv)); 966 } 967 968 static const struct i2c_algorithm smbus_algorithm = { 969 .smbus_xfer = i801_access, 970 .functionality = i801_func, 971 }; 972 973 #define FEATURES_ICH5 (FEATURE_BLOCK_PROC | FEATURE_I2C_BLOCK_READ | \ 974 FEATURE_IRQ | FEATURE_SMBUS_PEC | \ 975 FEATURE_BLOCK_BUFFER | FEATURE_HOST_NOTIFY) 976 #define FEATURES_ICH4 (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER | \ 977 FEATURE_HOST_NOTIFY) 978 979 static const struct pci_device_id i801_ids[] = { 980 { PCI_DEVICE_DATA(INTEL, 82801AA_3, 0) }, 981 { PCI_DEVICE_DATA(INTEL, 82801AB_3, 0) }, 982 { PCI_DEVICE_DATA(INTEL, 82801BA_2, 0) }, 983 { PCI_DEVICE_DATA(INTEL, 82801CA_3, FEATURE_HOST_NOTIFY) }, 984 { PCI_DEVICE_DATA(INTEL, 82801DB_3, FEATURES_ICH4) }, 985 { PCI_DEVICE_DATA(INTEL, 82801EB_3, FEATURES_ICH5) }, 986 { PCI_DEVICE_DATA(INTEL, ESB_4, FEATURES_ICH5) }, 987 { PCI_DEVICE_DATA(INTEL, ICH6_16, FEATURES_ICH5) }, 988 { PCI_DEVICE_DATA(INTEL, ICH7_17, FEATURES_ICH5) }, 989 { PCI_DEVICE_DATA(INTEL, ESB2_17, FEATURES_ICH5) }, 990 { PCI_DEVICE_DATA(INTEL, ICH8_5, FEATURES_ICH5) }, 991 { PCI_DEVICE_DATA(INTEL, ICH9_6, FEATURES_ICH5) }, 992 { PCI_DEVICE_DATA(INTEL, EP80579_1, FEATURES_ICH5) }, 993 { PCI_DEVICE_DATA(INTEL, ICH10_4, FEATURES_ICH5) }, 994 { PCI_DEVICE_DATA(INTEL, ICH10_5, FEATURES_ICH5) }, 995 { PCI_DEVICE_DATA(INTEL, 5_3400_SERIES_SMBUS, FEATURES_ICH5) }, 996 { PCI_DEVICE_DATA(INTEL, COUGARPOINT_SMBUS, FEATURES_ICH5) }, 997 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS, FEATURES_ICH5) }, 998 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF0, FEATURES_ICH5 | FEATURE_IDF) }, 999 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF1, FEATURES_ICH5 | FEATURE_IDF) }, 1000 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF2, FEATURES_ICH5 | FEATURE_IDF) }, 1001 { PCI_DEVICE_DATA(INTEL, DH89XXCC_SMBUS, FEATURES_ICH5) }, 1002 { PCI_DEVICE_DATA(INTEL, PANTHERPOINT_SMBUS, FEATURES_ICH5) }, 1003 { PCI_DEVICE_DATA(INTEL, LYNXPOINT_SMBUS, FEATURES_ICH5) }, 1004 { PCI_DEVICE_DATA(INTEL, LYNXPOINT_LP_SMBUS, FEATURES_ICH5) }, 1005 { PCI_DEVICE_DATA(INTEL, AVOTON_SMBUS, FEATURES_ICH5) }, 1006 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS, FEATURES_ICH5) }, 1007 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS0, FEATURES_ICH5 | FEATURE_IDF) }, 1008 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS1, FEATURES_ICH5 | FEATURE_IDF) }, 1009 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS2, FEATURES_ICH5 | FEATURE_IDF) }, 1010 { PCI_DEVICE_DATA(INTEL, COLETOCREEK_SMBUS, FEATURES_ICH5) }, 1011 { PCI_DEVICE_DATA(INTEL, GEMINILAKE_SMBUS, FEATURES_ICH5) }, 1012 { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_SMBUS, FEATURES_ICH5) }, 1013 { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_LP_SMBUS, FEATURES_ICH5) }, 1014 { PCI_DEVICE_DATA(INTEL, BAYTRAIL_SMBUS, FEATURES_ICH5) }, 1015 { PCI_DEVICE_DATA(INTEL, BRASWELL_SMBUS, FEATURES_ICH5) }, 1016 { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1017 { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1018 { PCI_DEVICE_DATA(INTEL, CDF_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1019 { PCI_DEVICE_DATA(INTEL, DNV_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1020 { PCI_DEVICE_DATA(INTEL, EBG_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1021 { PCI_DEVICE_DATA(INTEL, BROXTON_SMBUS, FEATURES_ICH5) }, 1022 { PCI_DEVICE_DATA(INTEL, LEWISBURG_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1023 { PCI_DEVICE_DATA(INTEL, LEWISBURG_SSKU_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1024 { PCI_DEVICE_DATA(INTEL, KABYLAKE_PCH_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1025 { PCI_DEVICE_DATA(INTEL, CANNONLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1026 { PCI_DEVICE_DATA(INTEL, CANNONLAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1027 { PCI_DEVICE_DATA(INTEL, ICELAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1028 { PCI_DEVICE_DATA(INTEL, ICELAKE_N_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1029 { PCI_DEVICE_DATA(INTEL, COMETLAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1030 { PCI_DEVICE_DATA(INTEL, COMETLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1031 { PCI_DEVICE_DATA(INTEL, COMETLAKE_V_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1032 { PCI_DEVICE_DATA(INTEL, ELKHART_LAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1033 { PCI_DEVICE_DATA(INTEL, TIGERLAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1034 { PCI_DEVICE_DATA(INTEL, TIGERLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1035 { PCI_DEVICE_DATA(INTEL, JASPER_LAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1036 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1037 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1038 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_M_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1039 { PCI_DEVICE_DATA(INTEL, RAPTOR_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1040 { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1041 { 0, } 1042 }; 1043 1044 MODULE_DEVICE_TABLE(pci, i801_ids); 1045 1046 #if defined CONFIG_X86 && defined CONFIG_DMI 1047 static unsigned char apanel_addr; 1048 1049 /* Scan the system ROM for the signature "FJKEYINF" */ 1050 static __init const void __iomem *bios_signature(const void __iomem *bios) 1051 { 1052 ssize_t offset; 1053 const unsigned char signature[] = "FJKEYINF"; 1054 1055 for (offset = 0; offset < 0x10000; offset += 0x10) { 1056 if (check_signature(bios + offset, signature, 1057 sizeof(signature)-1)) 1058 return bios + offset; 1059 } 1060 return NULL; 1061 } 1062 1063 static void __init input_apanel_init(void) 1064 { 1065 void __iomem *bios; 1066 const void __iomem *p; 1067 1068 bios = ioremap(0xF0000, 0x10000); /* Can't fail */ 1069 p = bios_signature(bios); 1070 if (p) { 1071 /* just use the first address */ 1072 apanel_addr = readb(p + 8 + 3) >> 1; 1073 } 1074 iounmap(bios); 1075 } 1076 1077 struct dmi_onboard_device_info { 1078 const char *name; 1079 u8 type; 1080 unsigned short i2c_addr; 1081 const char *i2c_type; 1082 }; 1083 1084 static const struct dmi_onboard_device_info dmi_devices[] = { 1085 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" }, 1086 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" }, 1087 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" }, 1088 }; 1089 1090 static void dmi_check_onboard_device(u8 type, const char *name, 1091 struct i2c_adapter *adap) 1092 { 1093 int i; 1094 struct i2c_board_info info; 1095 1096 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) { 1097 /* & ~0x80, ignore enabled/disabled bit */ 1098 if ((type & ~0x80) != dmi_devices[i].type) 1099 continue; 1100 if (strcasecmp(name, dmi_devices[i].name)) 1101 continue; 1102 1103 memset(&info, 0, sizeof(struct i2c_board_info)); 1104 info.addr = dmi_devices[i].i2c_addr; 1105 strscpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); 1106 i2c_new_client_device(adap, &info); 1107 break; 1108 } 1109 } 1110 1111 /* We use our own function to check for onboard devices instead of 1112 dmi_find_device() as some buggy BIOS's have the devices we are interested 1113 in marked as disabled */ 1114 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap) 1115 { 1116 int i, count; 1117 1118 if (dm->type != 10) 1119 return; 1120 1121 count = (dm->length - sizeof(struct dmi_header)) / 2; 1122 for (i = 0; i < count; i++) { 1123 const u8 *d = (char *)(dm + 1) + (i * 2); 1124 const char *name = ((char *) dm) + dm->length; 1125 u8 type = d[0]; 1126 u8 s = d[1]; 1127 1128 if (!s) 1129 continue; 1130 s--; 1131 while (s > 0 && name[0]) { 1132 name += strlen(name) + 1; 1133 s--; 1134 } 1135 if (name[0] == 0) /* Bogus string reference */ 1136 continue; 1137 1138 dmi_check_onboard_device(type, name, adap); 1139 } 1140 } 1141 1142 /* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */ 1143 static const char *const acpi_smo8800_ids[] = { 1144 "SMO8800", 1145 "SMO8801", 1146 "SMO8810", 1147 "SMO8811", 1148 "SMO8820", 1149 "SMO8821", 1150 "SMO8830", 1151 "SMO8831", 1152 }; 1153 1154 static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle, 1155 u32 nesting_level, 1156 void *context, 1157 void **return_value) 1158 { 1159 struct acpi_device_info *info; 1160 acpi_status status; 1161 char *hid; 1162 int i; 1163 1164 status = acpi_get_object_info(obj_handle, &info); 1165 if (ACPI_FAILURE(status)) 1166 return AE_OK; 1167 1168 if (!(info->valid & ACPI_VALID_HID)) 1169 goto smo88xx_not_found; 1170 1171 hid = info->hardware_id.string; 1172 if (!hid) 1173 goto smo88xx_not_found; 1174 1175 i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid); 1176 if (i < 0) 1177 goto smo88xx_not_found; 1178 1179 kfree(info); 1180 1181 *return_value = NULL; 1182 return AE_CTRL_TERMINATE; 1183 1184 smo88xx_not_found: 1185 kfree(info); 1186 return AE_OK; 1187 } 1188 1189 static bool is_dell_system_with_lis3lv02d(void) 1190 { 1191 void *err = ERR_PTR(-ENOENT); 1192 1193 if (!dmi_match(DMI_SYS_VENDOR, "Dell Inc.")) 1194 return false; 1195 1196 /* 1197 * Check that ACPI device SMO88xx is present and is functioning. 1198 * Function acpi_get_devices() already filters all ACPI devices 1199 * which are not present or are not functioning. 1200 * ACPI device SMO88xx represents our ST microelectronics lis3lv02d 1201 * accelerometer but unfortunately ACPI does not provide any other 1202 * information (like I2C address). 1203 */ 1204 acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL, &err); 1205 1206 return !IS_ERR(err); 1207 } 1208 1209 /* 1210 * Accelerometer's I2C address is not specified in DMI nor ACPI, 1211 * so it is needed to define mapping table based on DMI product names. 1212 */ 1213 static const struct { 1214 const char *dmi_product_name; 1215 unsigned short i2c_addr; 1216 } dell_lis3lv02d_devices[] = { 1217 /* 1218 * Dell platform team told us that these Latitude devices have 1219 * ST microelectronics accelerometer at I2C address 0x29. 1220 */ 1221 { "Latitude E5250", 0x29 }, 1222 { "Latitude E5450", 0x29 }, 1223 { "Latitude E5550", 0x29 }, 1224 { "Latitude E6440", 0x29 }, 1225 { "Latitude E6440 ATG", 0x29 }, 1226 { "Latitude E6540", 0x29 }, 1227 /* 1228 * Additional individual entries were added after verification. 1229 */ 1230 { "Latitude 5480", 0x29 }, 1231 { "Vostro V131", 0x1d }, 1232 { "Vostro 5568", 0x29 }, 1233 }; 1234 1235 static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv) 1236 { 1237 struct i2c_board_info info; 1238 const char *dmi_product_name; 1239 int i; 1240 1241 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME); 1242 for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) { 1243 if (strcmp(dmi_product_name, 1244 dell_lis3lv02d_devices[i].dmi_product_name) == 0) 1245 break; 1246 } 1247 1248 if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) { 1249 dev_warn(&priv->pci_dev->dev, 1250 "Accelerometer lis3lv02d is present on SMBus but its" 1251 " address is unknown, skipping registration\n"); 1252 return; 1253 } 1254 1255 memset(&info, 0, sizeof(struct i2c_board_info)); 1256 info.addr = dell_lis3lv02d_devices[i].i2c_addr; 1257 strscpy(info.type, "lis3lv02d", I2C_NAME_SIZE); 1258 i2c_new_client_device(&priv->adapter, &info); 1259 } 1260 1261 /* Register optional slaves */ 1262 static void i801_probe_optional_slaves(struct i801_priv *priv) 1263 { 1264 /* Only register slaves on main SMBus channel */ 1265 if (priv->features & FEATURE_IDF) 1266 return; 1267 1268 if (apanel_addr) { 1269 struct i2c_board_info info = { 1270 .addr = apanel_addr, 1271 .type = "fujitsu_apanel", 1272 }; 1273 1274 i2c_new_client_device(&priv->adapter, &info); 1275 } 1276 1277 if (dmi_name_in_vendors("FUJITSU")) 1278 dmi_walk(dmi_check_onboard_devices, &priv->adapter); 1279 1280 if (is_dell_system_with_lis3lv02d()) 1281 register_dell_lis3lv02d_i2c_device(priv); 1282 1283 /* Instantiate SPD EEPROMs unless the SMBus is multiplexed */ 1284 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) 1285 if (!priv->mux_drvdata) 1286 #endif 1287 i2c_register_spd(&priv->adapter); 1288 } 1289 #else 1290 static void __init input_apanel_init(void) {} 1291 static void i801_probe_optional_slaves(struct i801_priv *priv) {} 1292 #endif /* CONFIG_X86 && CONFIG_DMI */ 1293 1294 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 1295 static struct i801_mux_config i801_mux_config_asus_z8_d12 = { 1296 .gpio_chip = "gpio_ich", 1297 .values = { 0x02, 0x03 }, 1298 .n_values = 2, 1299 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD }, 1300 .gpios = { 52, 53 }, 1301 .n_gpios = 2, 1302 }; 1303 1304 static struct i801_mux_config i801_mux_config_asus_z8_d18 = { 1305 .gpio_chip = "gpio_ich", 1306 .values = { 0x02, 0x03, 0x01 }, 1307 .n_values = 3, 1308 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD }, 1309 .gpios = { 52, 53 }, 1310 .n_gpios = 2, 1311 }; 1312 1313 static const struct dmi_system_id mux_dmi_table[] = { 1314 { 1315 .matches = { 1316 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1317 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"), 1318 }, 1319 .driver_data = &i801_mux_config_asus_z8_d12, 1320 }, 1321 { 1322 .matches = { 1323 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1324 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"), 1325 }, 1326 .driver_data = &i801_mux_config_asus_z8_d12, 1327 }, 1328 { 1329 .matches = { 1330 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1331 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"), 1332 }, 1333 .driver_data = &i801_mux_config_asus_z8_d12, 1334 }, 1335 { 1336 .matches = { 1337 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1338 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"), 1339 }, 1340 .driver_data = &i801_mux_config_asus_z8_d12, 1341 }, 1342 { 1343 .matches = { 1344 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1345 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"), 1346 }, 1347 .driver_data = &i801_mux_config_asus_z8_d12, 1348 }, 1349 { 1350 .matches = { 1351 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1352 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"), 1353 }, 1354 .driver_data = &i801_mux_config_asus_z8_d12, 1355 }, 1356 { 1357 .matches = { 1358 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1359 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"), 1360 }, 1361 .driver_data = &i801_mux_config_asus_z8_d18, 1362 }, 1363 { 1364 .matches = { 1365 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1366 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"), 1367 }, 1368 .driver_data = &i801_mux_config_asus_z8_d18, 1369 }, 1370 { 1371 .matches = { 1372 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1373 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"), 1374 }, 1375 .driver_data = &i801_mux_config_asus_z8_d12, 1376 }, 1377 { } 1378 }; 1379 1380 /* Setup multiplexing if needed */ 1381 static void i801_add_mux(struct i801_priv *priv) 1382 { 1383 struct device *dev = &priv->adapter.dev; 1384 const struct i801_mux_config *mux_config; 1385 struct i2c_mux_gpio_platform_data gpio_data; 1386 struct gpiod_lookup_table *lookup; 1387 int i; 1388 1389 if (!priv->mux_drvdata) 1390 return; 1391 mux_config = priv->mux_drvdata; 1392 1393 /* Prepare the platform data */ 1394 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data)); 1395 gpio_data.parent = priv->adapter.nr; 1396 gpio_data.values = mux_config->values; 1397 gpio_data.n_values = mux_config->n_values; 1398 gpio_data.classes = mux_config->classes; 1399 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE; 1400 1401 /* Register GPIO descriptor lookup table */ 1402 lookup = devm_kzalloc(dev, 1403 struct_size(lookup, table, mux_config->n_gpios + 1), 1404 GFP_KERNEL); 1405 if (!lookup) 1406 return; 1407 lookup->dev_id = "i2c-mux-gpio"; 1408 for (i = 0; i < mux_config->n_gpios; i++) 1409 lookup->table[i] = GPIO_LOOKUP(mux_config->gpio_chip, 1410 mux_config->gpios[i], "mux", 0); 1411 gpiod_add_lookup_table(lookup); 1412 priv->lookup = lookup; 1413 1414 /* 1415 * Register the mux device, we use PLATFORM_DEVID_NONE here 1416 * because since we are referring to the GPIO chip by name we are 1417 * anyways in deep trouble if there is more than one of these 1418 * devices, and there should likely only be one platform controller 1419 * hub. 1420 */ 1421 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio", 1422 PLATFORM_DEVID_NONE, &gpio_data, 1423 sizeof(struct i2c_mux_gpio_platform_data)); 1424 if (IS_ERR(priv->mux_pdev)) { 1425 gpiod_remove_lookup_table(lookup); 1426 dev_err(dev, "Failed to register i2c-mux-gpio device\n"); 1427 } 1428 } 1429 1430 static void i801_del_mux(struct i801_priv *priv) 1431 { 1432 platform_device_unregister(priv->mux_pdev); 1433 gpiod_remove_lookup_table(priv->lookup); 1434 } 1435 1436 static unsigned int i801_get_adapter_class(struct i801_priv *priv) 1437 { 1438 const struct dmi_system_id *id; 1439 const struct i801_mux_config *mux_config; 1440 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 1441 int i; 1442 1443 id = dmi_first_match(mux_dmi_table); 1444 if (id) { 1445 /* Remove branch classes from trunk */ 1446 mux_config = id->driver_data; 1447 for (i = 0; i < mux_config->n_values; i++) 1448 class &= ~mux_config->classes[i]; 1449 1450 /* Remember for later */ 1451 priv->mux_drvdata = mux_config; 1452 } 1453 1454 return class; 1455 } 1456 #else 1457 static inline void i801_add_mux(struct i801_priv *priv) { } 1458 static inline void i801_del_mux(struct i801_priv *priv) { } 1459 1460 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv) 1461 { 1462 return I2C_CLASS_HWMON | I2C_CLASS_SPD; 1463 } 1464 #endif 1465 1466 static struct platform_device * 1467 i801_add_tco_spt(struct i801_priv *priv, struct pci_dev *pci_dev, 1468 struct resource *tco_res) 1469 { 1470 static const struct itco_wdt_platform_data pldata = { 1471 .name = "Intel PCH", 1472 .version = 4, 1473 }; 1474 struct resource *res; 1475 int ret; 1476 1477 /* 1478 * We must access the NO_REBOOT bit over the Primary to Sideband 1479 * (P2SB) bridge. 1480 */ 1481 1482 res = &tco_res[1]; 1483 ret = p2sb_bar(pci_dev->bus, 0, res); 1484 if (ret) 1485 return ERR_PTR(ret); 1486 1487 if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS) 1488 res->start += SBREG_SMBCTRL_DNV; 1489 else 1490 res->start += SBREG_SMBCTRL; 1491 1492 res->end = res->start + 3; 1493 1494 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1, 1495 tco_res, 2, &pldata, sizeof(pldata)); 1496 } 1497 1498 static struct platform_device * 1499 i801_add_tco_cnl(struct i801_priv *priv, struct pci_dev *pci_dev, 1500 struct resource *tco_res) 1501 { 1502 static const struct itco_wdt_platform_data pldata = { 1503 .name = "Intel PCH", 1504 .version = 6, 1505 }; 1506 1507 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1, 1508 tco_res, 1, &pldata, sizeof(pldata)); 1509 } 1510 1511 static void i801_add_tco(struct i801_priv *priv) 1512 { 1513 struct pci_dev *pci_dev = priv->pci_dev; 1514 struct resource tco_res[2], *res; 1515 u32 tco_base, tco_ctl; 1516 1517 /* If we have ACPI based watchdog use that instead */ 1518 if (acpi_has_watchdog()) 1519 return; 1520 1521 if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL))) 1522 return; 1523 1524 pci_read_config_dword(pci_dev, TCOBASE, &tco_base); 1525 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl); 1526 if (!(tco_ctl & TCOCTL_EN)) 1527 return; 1528 1529 memset(tco_res, 0, sizeof(tco_res)); 1530 /* 1531 * Always populate the main iTCO IO resource here. The second entry 1532 * for NO_REBOOT MMIO is filled by the SPT specific function. 1533 */ 1534 res = &tco_res[0]; 1535 res->start = tco_base & ~1; 1536 res->end = res->start + 32 - 1; 1537 res->flags = IORESOURCE_IO; 1538 1539 if (priv->features & FEATURE_TCO_CNL) 1540 priv->tco_pdev = i801_add_tco_cnl(priv, pci_dev, tco_res); 1541 else 1542 priv->tco_pdev = i801_add_tco_spt(priv, pci_dev, tco_res); 1543 1544 if (IS_ERR(priv->tco_pdev)) 1545 dev_warn(&pci_dev->dev, "failed to create iTCO device\n"); 1546 } 1547 1548 #ifdef CONFIG_ACPI 1549 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv, 1550 acpi_physical_address address) 1551 { 1552 return address >= priv->smba && 1553 address <= pci_resource_end(priv->pci_dev, SMBBAR); 1554 } 1555 1556 static acpi_status 1557 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits, 1558 u64 *value, void *handler_context, void *region_context) 1559 { 1560 struct i801_priv *priv = handler_context; 1561 struct pci_dev *pdev = priv->pci_dev; 1562 acpi_status status; 1563 1564 /* 1565 * Once BIOS AML code touches the OpRegion we warn and inhibit any 1566 * further access from the driver itself. This device is now owned 1567 * by the system firmware. 1568 */ 1569 mutex_lock(&priv->acpi_lock); 1570 1571 if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) { 1572 priv->acpi_reserved = true; 1573 1574 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n"); 1575 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n"); 1576 1577 /* 1578 * BIOS is accessing the host controller so prevent it from 1579 * suspending automatically from now on. 1580 */ 1581 pm_runtime_get_sync(&pdev->dev); 1582 } 1583 1584 if ((function & ACPI_IO_MASK) == ACPI_READ) 1585 status = acpi_os_read_port(address, (u32 *)value, bits); 1586 else 1587 status = acpi_os_write_port(address, (u32)*value, bits); 1588 1589 mutex_unlock(&priv->acpi_lock); 1590 1591 return status; 1592 } 1593 1594 static int i801_acpi_probe(struct i801_priv *priv) 1595 { 1596 acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev); 1597 acpi_status status; 1598 1599 status = acpi_install_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO, 1600 i801_acpi_io_handler, NULL, priv); 1601 if (ACPI_SUCCESS(status)) 1602 return 0; 1603 1604 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]); 1605 } 1606 1607 static void i801_acpi_remove(struct i801_priv *priv) 1608 { 1609 acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev); 1610 1611 acpi_remove_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler); 1612 } 1613 #else 1614 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; } 1615 static inline void i801_acpi_remove(struct i801_priv *priv) { } 1616 #endif 1617 1618 static void i801_setup_hstcfg(struct i801_priv *priv) 1619 { 1620 unsigned char hstcfg = priv->original_hstcfg; 1621 1622 hstcfg &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ 1623 hstcfg |= SMBHSTCFG_HST_EN; 1624 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hstcfg); 1625 } 1626 1627 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id) 1628 { 1629 int err, i; 1630 struct i801_priv *priv; 1631 1632 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL); 1633 if (!priv) 1634 return -ENOMEM; 1635 1636 i2c_set_adapdata(&priv->adapter, priv); 1637 priv->adapter.owner = THIS_MODULE; 1638 priv->adapter.class = i801_get_adapter_class(priv); 1639 priv->adapter.algo = &smbus_algorithm; 1640 priv->adapter.dev.parent = &dev->dev; 1641 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev)); 1642 priv->adapter.retries = 3; 1643 mutex_init(&priv->acpi_lock); 1644 1645 priv->pci_dev = dev; 1646 priv->features = id->driver_data; 1647 1648 /* Disable features on user request */ 1649 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) { 1650 if (priv->features & disable_features & (1 << i)) 1651 dev_notice(&dev->dev, "%s disabled by user\n", 1652 i801_feature_names[i]); 1653 } 1654 priv->features &= ~disable_features; 1655 1656 /* The block process call uses block buffer mode */ 1657 if (!(priv->features & FEATURE_BLOCK_BUFFER)) 1658 priv->features &= ~FEATURE_BLOCK_PROC; 1659 1660 err = pcim_enable_device(dev); 1661 if (err) { 1662 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", 1663 err); 1664 return err; 1665 } 1666 pcim_pin_device(dev); 1667 1668 /* Determine the address of the SMBus area */ 1669 priv->smba = pci_resource_start(dev, SMBBAR); 1670 if (!priv->smba) { 1671 dev_err(&dev->dev, 1672 "SMBus base address uninitialized, upgrade BIOS\n"); 1673 return -ENODEV; 1674 } 1675 1676 if (i801_acpi_probe(priv)) 1677 return -ENODEV; 1678 1679 err = pcim_iomap_regions(dev, 1 << SMBBAR, DRV_NAME); 1680 if (err) { 1681 dev_err(&dev->dev, 1682 "Failed to request SMBus region 0x%lx-0x%Lx\n", 1683 priv->smba, 1684 (unsigned long long)pci_resource_end(dev, SMBBAR)); 1685 i801_acpi_remove(priv); 1686 return err; 1687 } 1688 1689 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &priv->original_hstcfg); 1690 i801_setup_hstcfg(priv); 1691 if (!(priv->original_hstcfg & SMBHSTCFG_HST_EN)) 1692 dev_info(&dev->dev, "Enabling SMBus device\n"); 1693 1694 if (priv->original_hstcfg & SMBHSTCFG_SMB_SMI_EN) { 1695 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); 1696 /* Disable SMBus interrupt feature if SMBus using SMI# */ 1697 priv->features &= ~FEATURE_IRQ; 1698 } 1699 if (priv->original_hstcfg & SMBHSTCFG_SPD_WD) 1700 dev_info(&dev->dev, "SPD Write Disable is set\n"); 1701 1702 /* Clear special mode bits */ 1703 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) 1704 outb_p(inb_p(SMBAUXCTL(priv)) & 1705 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 1706 1707 /* Default timeout in interrupt mode: 200 ms */ 1708 priv->adapter.timeout = HZ / 5; 1709 1710 if (dev->irq == IRQ_NOTCONNECTED) 1711 priv->features &= ~FEATURE_IRQ; 1712 1713 if (priv->features & FEATURE_IRQ) { 1714 u16 pcists; 1715 1716 /* Complain if an interrupt is already pending */ 1717 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists); 1718 if (pcists & PCI_STATUS_INTERRUPT) 1719 dev_warn(&dev->dev, "An interrupt is pending!\n"); 1720 } 1721 1722 if (priv->features & FEATURE_IRQ) { 1723 init_completion(&priv->done); 1724 1725 err = devm_request_irq(&dev->dev, dev->irq, i801_isr, 1726 IRQF_SHARED, DRV_NAME, priv); 1727 if (err) { 1728 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n", 1729 dev->irq, err); 1730 priv->features &= ~FEATURE_IRQ; 1731 } 1732 } 1733 dev_info(&dev->dev, "SMBus using %s\n", 1734 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling"); 1735 1736 /* Host notification uses an interrupt */ 1737 if (!(priv->features & FEATURE_IRQ)) 1738 priv->features &= ~FEATURE_HOST_NOTIFY; 1739 1740 /* Remember original Interrupt and Host Notify settings */ 1741 priv->original_hstcnt = inb_p(SMBHSTCNT(priv)) & ~SMBHSTCNT_KILL; 1742 if (priv->features & FEATURE_HOST_NOTIFY) 1743 priv->original_slvcmd = inb_p(SMBSLVCMD(priv)); 1744 1745 i801_add_tco(priv); 1746 1747 snprintf(priv->adapter.name, sizeof(priv->adapter.name), 1748 "SMBus I801 adapter at %04lx", priv->smba); 1749 err = i2c_add_adapter(&priv->adapter); 1750 if (err) { 1751 i801_acpi_remove(priv); 1752 return err; 1753 } 1754 1755 i801_enable_host_notify(&priv->adapter); 1756 1757 i801_probe_optional_slaves(priv); 1758 /* We ignore errors - multiplexing is optional */ 1759 i801_add_mux(priv); 1760 1761 pci_set_drvdata(dev, priv); 1762 1763 dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 1764 pm_runtime_set_autosuspend_delay(&dev->dev, 1000); 1765 pm_runtime_use_autosuspend(&dev->dev); 1766 pm_runtime_put_autosuspend(&dev->dev); 1767 pm_runtime_allow(&dev->dev); 1768 1769 return 0; 1770 } 1771 1772 static void i801_remove(struct pci_dev *dev) 1773 { 1774 struct i801_priv *priv = pci_get_drvdata(dev); 1775 1776 outb_p(priv->original_hstcnt, SMBHSTCNT(priv)); 1777 i801_disable_host_notify(priv); 1778 i801_del_mux(priv); 1779 i2c_del_adapter(&priv->adapter); 1780 i801_acpi_remove(priv); 1781 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); 1782 1783 platform_device_unregister(priv->tco_pdev); 1784 1785 /* if acpi_reserved is set then usage_count is incremented already */ 1786 if (!priv->acpi_reserved) 1787 pm_runtime_get_noresume(&dev->dev); 1788 1789 /* 1790 * do not call pci_disable_device(dev) since it can cause hard hangs on 1791 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) 1792 */ 1793 } 1794 1795 static void i801_shutdown(struct pci_dev *dev) 1796 { 1797 struct i801_priv *priv = pci_get_drvdata(dev); 1798 1799 /* Restore config registers to avoid hard hang on some systems */ 1800 outb_p(priv->original_hstcnt, SMBHSTCNT(priv)); 1801 i801_disable_host_notify(priv); 1802 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); 1803 } 1804 1805 #ifdef CONFIG_PM_SLEEP 1806 static int i801_suspend(struct device *dev) 1807 { 1808 struct i801_priv *priv = dev_get_drvdata(dev); 1809 1810 outb_p(priv->original_hstcnt, SMBHSTCNT(priv)); 1811 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, priv->original_hstcfg); 1812 return 0; 1813 } 1814 1815 static int i801_resume(struct device *dev) 1816 { 1817 struct i801_priv *priv = dev_get_drvdata(dev); 1818 1819 i801_setup_hstcfg(priv); 1820 i801_enable_host_notify(&priv->adapter); 1821 1822 return 0; 1823 } 1824 #endif 1825 1826 static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume); 1827 1828 static struct pci_driver i801_driver = { 1829 .name = DRV_NAME, 1830 .id_table = i801_ids, 1831 .probe = i801_probe, 1832 .remove = i801_remove, 1833 .shutdown = i801_shutdown, 1834 .driver = { 1835 .pm = &i801_pm_ops, 1836 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1837 }, 1838 }; 1839 1840 static int __init i2c_i801_init(void) 1841 { 1842 if (dmi_name_in_vendors("FUJITSU")) 1843 input_apanel_init(); 1844 return pci_register_driver(&i801_driver); 1845 } 1846 1847 static void __exit i2c_i801_exit(void) 1848 { 1849 pci_unregister_driver(&i801_driver); 1850 } 1851 1852 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>"); 1853 MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>"); 1854 MODULE_DESCRIPTION("I801 SMBus driver"); 1855 MODULE_LICENSE("GPL"); 1856 1857 module_init(i2c_i801_init); 1858 module_exit(i2c_i801_exit); 1859