1 /* 2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, 3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker 4 <mdsxyz123@yahoo.com> 5 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de> 6 Copyright (C) 2010 Intel Corporation, 7 David Woodhouse <dwmw2@infradead.org> 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 2 of the License, or 12 (at your option) any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 */ 19 20 /* 21 * Supports the following Intel I/O Controller Hubs (ICH): 22 * 23 * I/O Block I2C 24 * region SMBus Block proc. block 25 * Chip name PCI ID size PEC buffer call read 26 * --------------------------------------------------------------------------- 27 * 82801AA (ICH) 0x2413 16 no no no no 28 * 82801AB (ICH0) 0x2423 16 no no no no 29 * 82801BA (ICH2) 0x2443 16 no no no no 30 * 82801CA (ICH3) 0x2483 32 soft no no no 31 * 82801DB (ICH4) 0x24c3 32 hard yes no no 32 * 82801E (ICH5) 0x24d3 32 hard yes yes yes 33 * 6300ESB 0x25a4 32 hard yes yes yes 34 * 82801F (ICH6) 0x266a 32 hard yes yes yes 35 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes 36 * 82801G (ICH7) 0x27da 32 hard yes yes yes 37 * 82801H (ICH8) 0x283e 32 hard yes yes yes 38 * 82801I (ICH9) 0x2930 32 hard yes yes yes 39 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes 40 * ICH10 0x3a30 32 hard yes yes yes 41 * ICH10 0x3a60 32 hard yes yes yes 42 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes 43 * 6 Series (PCH) 0x1c22 32 hard yes yes yes 44 * Patsburg (PCH) 0x1d22 32 hard yes yes yes 45 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes 46 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes 47 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes 48 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes 49 * Panther Point (PCH) 0x1e22 32 hard yes yes yes 50 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes 51 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes 52 * Avoton (SOC) 0x1f3c 32 hard yes yes yes 53 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes 54 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes 55 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes 56 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes 57 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes 58 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes 59 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes 60 * BayTrail (SOC) 0x0f12 32 hard yes yes yes 61 * Braswell (SOC) 0x2292 32 hard yes yes yes 62 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes 63 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes 64 * DNV (SOC) 0x19df 32 hard yes yes yes 65 * Broxton (SOC) 0x5ad4 32 hard yes yes yes 66 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes 67 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes 68 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes 69 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes 70 * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes 71 * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes 72 * Cedar Fork (PCH) 0x18df 32 hard yes yes yes 73 * Ice Lake-LP (PCH) 0x34a3 32 hard yes yes yes 74 * 75 * Features supported by this driver: 76 * Software PEC no 77 * Hardware PEC yes 78 * Block buffer yes 79 * Block process call transaction no 80 * I2C block read transaction yes (doesn't use the block buffer) 81 * Slave mode no 82 * SMBus Host Notify yes 83 * Interrupt processing yes 84 * 85 * See the file Documentation/i2c/busses/i2c-i801 for details. 86 */ 87 88 #include <linux/interrupt.h> 89 #include <linux/module.h> 90 #include <linux/pci.h> 91 #include <linux/kernel.h> 92 #include <linux/stddef.h> 93 #include <linux/delay.h> 94 #include <linux/ioport.h> 95 #include <linux/init.h> 96 #include <linux/i2c.h> 97 #include <linux/i2c-smbus.h> 98 #include <linux/acpi.h> 99 #include <linux/io.h> 100 #include <linux/dmi.h> 101 #include <linux/slab.h> 102 #include <linux/wait.h> 103 #include <linux/err.h> 104 #include <linux/platform_device.h> 105 #include <linux/platform_data/itco_wdt.h> 106 #include <linux/pm_runtime.h> 107 108 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 109 #include <linux/gpio.h> 110 #include <linux/platform_data/i2c-mux-gpio.h> 111 #endif 112 113 /* I801 SMBus address offsets */ 114 #define SMBHSTSTS(p) (0 + (p)->smba) 115 #define SMBHSTCNT(p) (2 + (p)->smba) 116 #define SMBHSTCMD(p) (3 + (p)->smba) 117 #define SMBHSTADD(p) (4 + (p)->smba) 118 #define SMBHSTDAT0(p) (5 + (p)->smba) 119 #define SMBHSTDAT1(p) (6 + (p)->smba) 120 #define SMBBLKDAT(p) (7 + (p)->smba) 121 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */ 122 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */ 123 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */ 124 #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */ 125 #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */ 126 #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */ 127 128 /* PCI Address Constants */ 129 #define SMBBAR 4 130 #define SMBPCICTL 0x004 131 #define SMBPCISTS 0x006 132 #define SMBHSTCFG 0x040 133 #define TCOBASE 0x050 134 #define TCOCTL 0x054 135 136 #define ACPIBASE 0x040 137 #define ACPIBASE_SMI_OFF 0x030 138 #define ACPICTRL 0x044 139 #define ACPICTRL_EN 0x080 140 141 #define SBREG_BAR 0x10 142 #define SBREG_SMBCTRL 0xc6000c 143 144 /* Host status bits for SMBPCISTS */ 145 #define SMBPCISTS_INTS BIT(3) 146 147 /* Control bits for SMBPCICTL */ 148 #define SMBPCICTL_INTDIS BIT(10) 149 150 /* Host configuration bits for SMBHSTCFG */ 151 #define SMBHSTCFG_HST_EN BIT(0) 152 #define SMBHSTCFG_SMB_SMI_EN BIT(1) 153 #define SMBHSTCFG_I2C_EN BIT(2) 154 #define SMBHSTCFG_SPD_WD BIT(4) 155 156 /* TCO configuration bits for TCOCTL */ 157 #define TCOCTL_EN BIT(8) 158 159 /* Auxiliary status register bits, ICH4+ only */ 160 #define SMBAUXSTS_CRCE BIT(0) 161 #define SMBAUXSTS_STCO BIT(1) 162 163 /* Auxiliary control register bits, ICH4+ only */ 164 #define SMBAUXCTL_CRC BIT(0) 165 #define SMBAUXCTL_E32B BIT(1) 166 167 /* Other settings */ 168 #define MAX_RETRIES 400 169 170 /* I801 command constants */ 171 #define I801_QUICK 0x00 172 #define I801_BYTE 0x04 173 #define I801_BYTE_DATA 0x08 174 #define I801_WORD_DATA 0x0C 175 #define I801_PROC_CALL 0x10 /* unimplemented */ 176 #define I801_BLOCK_DATA 0x14 177 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ 178 179 /* I801 Host Control register bits */ 180 #define SMBHSTCNT_INTREN BIT(0) 181 #define SMBHSTCNT_KILL BIT(1) 182 #define SMBHSTCNT_LAST_BYTE BIT(5) 183 #define SMBHSTCNT_START BIT(6) 184 #define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */ 185 186 /* I801 Hosts Status register bits */ 187 #define SMBHSTSTS_BYTE_DONE BIT(7) 188 #define SMBHSTSTS_INUSE_STS BIT(6) 189 #define SMBHSTSTS_SMBALERT_STS BIT(5) 190 #define SMBHSTSTS_FAILED BIT(4) 191 #define SMBHSTSTS_BUS_ERR BIT(3) 192 #define SMBHSTSTS_DEV_ERR BIT(2) 193 #define SMBHSTSTS_INTR BIT(1) 194 #define SMBHSTSTS_HOST_BUSY BIT(0) 195 196 /* Host Notify Status register bits */ 197 #define SMBSLVSTS_HST_NTFY_STS BIT(0) 198 199 /* Host Notify Command register bits */ 200 #define SMBSLVCMD_HST_NTFY_INTREN BIT(0) 201 202 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \ 203 SMBHSTSTS_DEV_ERR) 204 205 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \ 206 STATUS_ERROR_FLAGS) 207 208 /* Older devices have their ID defined in <linux/pci_ids.h> */ 209 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12 210 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df 211 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df 212 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 213 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 214 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */ 215 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70 216 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71 217 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72 218 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 219 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c 220 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292 221 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 222 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0 223 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4 224 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS 0x34a3 225 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 226 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4 227 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 228 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2 229 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22 230 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d 231 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e 232 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f 233 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22 234 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2 235 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23 236 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3 237 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123 238 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3 239 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223 240 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3 241 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323 242 243 struct i801_mux_config { 244 char *gpio_chip; 245 unsigned values[3]; 246 int n_values; 247 unsigned classes[3]; 248 unsigned gpios[2]; /* Relative to gpio_chip->base */ 249 int n_gpios; 250 }; 251 252 struct i801_priv { 253 struct i2c_adapter adapter; 254 unsigned long smba; 255 unsigned char original_hstcfg; 256 unsigned char original_slvcmd; 257 struct pci_dev *pci_dev; 258 unsigned int features; 259 260 /* isr processing */ 261 wait_queue_head_t waitq; 262 u8 status; 263 264 /* Command state used by isr for byte-by-byte block transactions */ 265 u8 cmd; 266 bool is_read; 267 int count; 268 int len; 269 u8 *data; 270 271 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 272 const struct i801_mux_config *mux_drvdata; 273 struct platform_device *mux_pdev; 274 #endif 275 struct platform_device *tco_pdev; 276 277 /* 278 * If set to true the host controller registers are reserved for 279 * ACPI AML use. Protected by acpi_lock. 280 */ 281 bool acpi_reserved; 282 struct mutex acpi_lock; 283 }; 284 285 #define FEATURE_SMBUS_PEC BIT(0) 286 #define FEATURE_BLOCK_BUFFER BIT(1) 287 #define FEATURE_BLOCK_PROC BIT(2) 288 #define FEATURE_I2C_BLOCK_READ BIT(3) 289 #define FEATURE_IRQ BIT(4) 290 #define FEATURE_HOST_NOTIFY BIT(5) 291 /* Not really a feature, but it's convenient to handle it as such */ 292 #define FEATURE_IDF BIT(15) 293 #define FEATURE_TCO BIT(16) 294 295 static const char *i801_feature_names[] = { 296 "SMBus PEC", 297 "Block buffer", 298 "Block process call", 299 "I2C block read", 300 "Interrupt", 301 "SMBus Host Notify", 302 }; 303 304 static unsigned int disable_features; 305 module_param(disable_features, uint, S_IRUGO | S_IWUSR); 306 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n" 307 "\t\t 0x01 disable SMBus PEC\n" 308 "\t\t 0x02 disable the block buffer\n" 309 "\t\t 0x08 disable the I2C block read functionality\n" 310 "\t\t 0x10 don't use interrupts\n" 311 "\t\t 0x20 disable SMBus Host Notify "); 312 313 /* Make sure the SMBus host is ready to start transmitting. 314 Return 0 if it is, -EBUSY if it is not. */ 315 static int i801_check_pre(struct i801_priv *priv) 316 { 317 int status; 318 319 status = inb_p(SMBHSTSTS(priv)); 320 if (status & SMBHSTSTS_HOST_BUSY) { 321 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n"); 322 return -EBUSY; 323 } 324 325 status &= STATUS_FLAGS; 326 if (status) { 327 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n", 328 status); 329 outb_p(status, SMBHSTSTS(priv)); 330 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS; 331 if (status) { 332 dev_err(&priv->pci_dev->dev, 333 "Failed clearing status flags (%02x)\n", 334 status); 335 return -EBUSY; 336 } 337 } 338 339 /* 340 * Clear CRC status if needed. 341 * During normal operation, i801_check_post() takes care 342 * of it after every operation. We do it here only in case 343 * the hardware was already in this state when the driver 344 * started. 345 */ 346 if (priv->features & FEATURE_SMBUS_PEC) { 347 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE; 348 if (status) { 349 dev_dbg(&priv->pci_dev->dev, 350 "Clearing aux status flags (%02x)\n", status); 351 outb_p(status, SMBAUXSTS(priv)); 352 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE; 353 if (status) { 354 dev_err(&priv->pci_dev->dev, 355 "Failed clearing aux status flags (%02x)\n", 356 status); 357 return -EBUSY; 358 } 359 } 360 } 361 362 return 0; 363 } 364 365 /* 366 * Convert the status register to an error code, and clear it. 367 * Note that status only contains the bits we want to clear, not the 368 * actual register value. 369 */ 370 static int i801_check_post(struct i801_priv *priv, int status) 371 { 372 int result = 0; 373 374 /* 375 * If the SMBus is still busy, we give up 376 * Note: This timeout condition only happens when using polling 377 * transactions. For interrupt operation, NAK/timeout is indicated by 378 * DEV_ERR. 379 */ 380 if (unlikely(status < 0)) { 381 dev_err(&priv->pci_dev->dev, "Transaction timeout\n"); 382 /* try to stop the current command */ 383 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n"); 384 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL, 385 SMBHSTCNT(priv)); 386 usleep_range(1000, 2000); 387 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL), 388 SMBHSTCNT(priv)); 389 390 /* Check if it worked */ 391 status = inb_p(SMBHSTSTS(priv)); 392 if ((status & SMBHSTSTS_HOST_BUSY) || 393 !(status & SMBHSTSTS_FAILED)) 394 dev_err(&priv->pci_dev->dev, 395 "Failed terminating the transaction\n"); 396 outb_p(STATUS_FLAGS, SMBHSTSTS(priv)); 397 return -ETIMEDOUT; 398 } 399 400 if (status & SMBHSTSTS_FAILED) { 401 result = -EIO; 402 dev_err(&priv->pci_dev->dev, "Transaction failed\n"); 403 } 404 if (status & SMBHSTSTS_DEV_ERR) { 405 /* 406 * This may be a PEC error, check and clear it. 407 * 408 * AUXSTS is handled differently from HSTSTS. 409 * For HSTSTS, i801_isr() or i801_wait_intr() 410 * has already cleared the error bits in hardware, 411 * and we are passed a copy of the original value 412 * in "status". 413 * For AUXSTS, the hardware register is left 414 * for us to handle here. 415 * This is asymmetric, slightly iffy, but safe, 416 * since all this code is serialized and the CRCE 417 * bit is harmless as long as it's cleared before 418 * the next operation. 419 */ 420 if ((priv->features & FEATURE_SMBUS_PEC) && 421 (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) { 422 outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv)); 423 result = -EBADMSG; 424 dev_dbg(&priv->pci_dev->dev, "PEC error\n"); 425 } else { 426 result = -ENXIO; 427 dev_dbg(&priv->pci_dev->dev, "No response\n"); 428 } 429 } 430 if (status & SMBHSTSTS_BUS_ERR) { 431 result = -EAGAIN; 432 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n"); 433 } 434 435 /* Clear status flags except BYTE_DONE, to be cleared by caller */ 436 outb_p(status, SMBHSTSTS(priv)); 437 438 return result; 439 } 440 441 /* Wait for BUSY being cleared and either INTR or an error flag being set */ 442 static int i801_wait_intr(struct i801_priv *priv) 443 { 444 int timeout = 0; 445 int status; 446 447 /* We will always wait for a fraction of a second! */ 448 do { 449 usleep_range(250, 500); 450 status = inb_p(SMBHSTSTS(priv)); 451 } while (((status & SMBHSTSTS_HOST_BUSY) || 452 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) && 453 (timeout++ < MAX_RETRIES)); 454 455 if (timeout > MAX_RETRIES) { 456 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n"); 457 return -ETIMEDOUT; 458 } 459 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR); 460 } 461 462 /* Wait for either BYTE_DONE or an error flag being set */ 463 static int i801_wait_byte_done(struct i801_priv *priv) 464 { 465 int timeout = 0; 466 int status; 467 468 /* We will always wait for a fraction of a second! */ 469 do { 470 usleep_range(250, 500); 471 status = inb_p(SMBHSTSTS(priv)); 472 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) && 473 (timeout++ < MAX_RETRIES)); 474 475 if (timeout > MAX_RETRIES) { 476 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n"); 477 return -ETIMEDOUT; 478 } 479 return status & STATUS_ERROR_FLAGS; 480 } 481 482 static int i801_transaction(struct i801_priv *priv, int xact) 483 { 484 int status; 485 int result; 486 const struct i2c_adapter *adap = &priv->adapter; 487 488 result = i801_check_pre(priv); 489 if (result < 0) 490 return result; 491 492 if (priv->features & FEATURE_IRQ) { 493 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START, 494 SMBHSTCNT(priv)); 495 result = wait_event_timeout(priv->waitq, 496 (status = priv->status), 497 adap->timeout); 498 if (!result) { 499 status = -ETIMEDOUT; 500 dev_warn(&priv->pci_dev->dev, 501 "Timeout waiting for interrupt!\n"); 502 } 503 priv->status = 0; 504 return i801_check_post(priv, status); 505 } 506 507 /* the current contents of SMBHSTCNT can be overwritten, since PEC, 508 * SMBSCMD are passed in xact */ 509 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv)); 510 511 status = i801_wait_intr(priv); 512 return i801_check_post(priv, status); 513 } 514 515 static int i801_block_transaction_by_block(struct i801_priv *priv, 516 union i2c_smbus_data *data, 517 char read_write, int hwpec) 518 { 519 int i, len; 520 int status; 521 522 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ 523 524 /* Use 32-byte buffer to process this transaction */ 525 if (read_write == I2C_SMBUS_WRITE) { 526 len = data->block[0]; 527 outb_p(len, SMBHSTDAT0(priv)); 528 for (i = 0; i < len; i++) 529 outb_p(data->block[i+1], SMBBLKDAT(priv)); 530 } 531 532 status = i801_transaction(priv, I801_BLOCK_DATA | 533 (hwpec ? SMBHSTCNT_PEC_EN : 0)); 534 if (status) 535 return status; 536 537 if (read_write == I2C_SMBUS_READ) { 538 len = inb_p(SMBHSTDAT0(priv)); 539 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) 540 return -EPROTO; 541 542 data->block[0] = len; 543 for (i = 0; i < len; i++) 544 data->block[i + 1] = inb_p(SMBBLKDAT(priv)); 545 } 546 return 0; 547 } 548 549 static void i801_isr_byte_done(struct i801_priv *priv) 550 { 551 if (priv->is_read) { 552 /* For SMBus block reads, length is received with first byte */ 553 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) && 554 (priv->count == 0)) { 555 priv->len = inb_p(SMBHSTDAT0(priv)); 556 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) { 557 dev_err(&priv->pci_dev->dev, 558 "Illegal SMBus block read size %d\n", 559 priv->len); 560 /* FIXME: Recover */ 561 priv->len = I2C_SMBUS_BLOCK_MAX; 562 } else { 563 dev_dbg(&priv->pci_dev->dev, 564 "SMBus block read size is %d\n", 565 priv->len); 566 } 567 priv->data[-1] = priv->len; 568 } 569 570 /* Read next byte */ 571 if (priv->count < priv->len) 572 priv->data[priv->count++] = inb(SMBBLKDAT(priv)); 573 else 574 dev_dbg(&priv->pci_dev->dev, 575 "Discarding extra byte on block read\n"); 576 577 /* Set LAST_BYTE for last byte of read transaction */ 578 if (priv->count == priv->len - 1) 579 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE, 580 SMBHSTCNT(priv)); 581 } else if (priv->count < priv->len - 1) { 582 /* Write next byte, except for IRQ after last byte */ 583 outb_p(priv->data[++priv->count], SMBBLKDAT(priv)); 584 } 585 586 /* Clear BYTE_DONE to continue with next byte */ 587 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 588 } 589 590 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv) 591 { 592 unsigned short addr; 593 594 addr = inb_p(SMBNTFDADD(priv)) >> 1; 595 596 /* 597 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba) 598 * always returns 0. Our current implementation doesn't provide 599 * data, so we just ignore it. 600 */ 601 i2c_handle_smbus_host_notify(&priv->adapter, addr); 602 603 /* clear Host Notify bit and return */ 604 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 605 return IRQ_HANDLED; 606 } 607 608 /* 609 * There are three kinds of interrupts: 610 * 611 * 1) i801 signals transaction completion with one of these interrupts: 612 * INTR - Success 613 * DEV_ERR - Invalid command, NAK or communication timeout 614 * BUS_ERR - SMI# transaction collision 615 * FAILED - transaction was canceled due to a KILL request 616 * When any of these occur, update ->status and wake up the waitq. 617 * ->status must be cleared before kicking off the next transaction. 618 * 619 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt 620 * occurs for each byte of a byte-by-byte to prepare the next byte. 621 * 622 * 3) Host Notify interrupts 623 */ 624 static irqreturn_t i801_isr(int irq, void *dev_id) 625 { 626 struct i801_priv *priv = dev_id; 627 u16 pcists; 628 u8 status; 629 630 /* Confirm this is our interrupt */ 631 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); 632 if (!(pcists & SMBPCISTS_INTS)) 633 return IRQ_NONE; 634 635 if (priv->features & FEATURE_HOST_NOTIFY) { 636 status = inb_p(SMBSLVSTS(priv)); 637 if (status & SMBSLVSTS_HST_NTFY_STS) 638 return i801_host_notify_isr(priv); 639 } 640 641 status = inb_p(SMBHSTSTS(priv)); 642 if (status & SMBHSTSTS_BYTE_DONE) 643 i801_isr_byte_done(priv); 644 645 /* 646 * Clear irq sources and report transaction result. 647 * ->status must be cleared before the next transaction is started. 648 */ 649 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS; 650 if (status) { 651 outb_p(status, SMBHSTSTS(priv)); 652 priv->status = status; 653 wake_up(&priv->waitq); 654 } 655 656 return IRQ_HANDLED; 657 } 658 659 /* 660 * For "byte-by-byte" block transactions: 661 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1 662 * I2C read uses cmd=I801_I2C_BLOCK_DATA 663 */ 664 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, 665 union i2c_smbus_data *data, 666 char read_write, int command, 667 int hwpec) 668 { 669 int i, len; 670 int smbcmd; 671 int status; 672 int result; 673 const struct i2c_adapter *adap = &priv->adapter; 674 675 result = i801_check_pre(priv); 676 if (result < 0) 677 return result; 678 679 len = data->block[0]; 680 681 if (read_write == I2C_SMBUS_WRITE) { 682 outb_p(len, SMBHSTDAT0(priv)); 683 outb_p(data->block[1], SMBBLKDAT(priv)); 684 } 685 686 if (command == I2C_SMBUS_I2C_BLOCK_DATA && 687 read_write == I2C_SMBUS_READ) 688 smbcmd = I801_I2C_BLOCK_DATA; 689 else 690 smbcmd = I801_BLOCK_DATA; 691 692 if (priv->features & FEATURE_IRQ) { 693 priv->is_read = (read_write == I2C_SMBUS_READ); 694 if (len == 1 && priv->is_read) 695 smbcmd |= SMBHSTCNT_LAST_BYTE; 696 priv->cmd = smbcmd | SMBHSTCNT_INTREN; 697 priv->len = len; 698 priv->count = 0; 699 priv->data = &data->block[1]; 700 701 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv)); 702 result = wait_event_timeout(priv->waitq, 703 (status = priv->status), 704 adap->timeout); 705 if (!result) { 706 status = -ETIMEDOUT; 707 dev_warn(&priv->pci_dev->dev, 708 "Timeout waiting for interrupt!\n"); 709 } 710 priv->status = 0; 711 return i801_check_post(priv, status); 712 } 713 714 for (i = 1; i <= len; i++) { 715 if (i == len && read_write == I2C_SMBUS_READ) 716 smbcmd |= SMBHSTCNT_LAST_BYTE; 717 outb_p(smbcmd, SMBHSTCNT(priv)); 718 719 if (i == 1) 720 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START, 721 SMBHSTCNT(priv)); 722 723 status = i801_wait_byte_done(priv); 724 if (status) 725 goto exit; 726 727 if (i == 1 && read_write == I2C_SMBUS_READ 728 && command != I2C_SMBUS_I2C_BLOCK_DATA) { 729 len = inb_p(SMBHSTDAT0(priv)); 730 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { 731 dev_err(&priv->pci_dev->dev, 732 "Illegal SMBus block read size %d\n", 733 len); 734 /* Recover */ 735 while (inb_p(SMBHSTSTS(priv)) & 736 SMBHSTSTS_HOST_BUSY) 737 outb_p(SMBHSTSTS_BYTE_DONE, 738 SMBHSTSTS(priv)); 739 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); 740 return -EPROTO; 741 } 742 data->block[0] = len; 743 } 744 745 /* Retrieve/store value in SMBBLKDAT */ 746 if (read_write == I2C_SMBUS_READ) 747 data->block[i] = inb_p(SMBBLKDAT(priv)); 748 if (read_write == I2C_SMBUS_WRITE && i+1 <= len) 749 outb_p(data->block[i+1], SMBBLKDAT(priv)); 750 751 /* signals SMBBLKDAT ready */ 752 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 753 } 754 755 status = i801_wait_intr(priv); 756 exit: 757 return i801_check_post(priv, status); 758 } 759 760 static int i801_set_block_buffer_mode(struct i801_priv *priv) 761 { 762 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv)); 763 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0) 764 return -EIO; 765 return 0; 766 } 767 768 /* Block transaction function */ 769 static int i801_block_transaction(struct i801_priv *priv, 770 union i2c_smbus_data *data, char read_write, 771 int command, int hwpec) 772 { 773 int result = 0; 774 unsigned char hostc; 775 776 if (command == I2C_SMBUS_I2C_BLOCK_DATA) { 777 if (read_write == I2C_SMBUS_WRITE) { 778 /* set I2C_EN bit in configuration register */ 779 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc); 780 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, 781 hostc | SMBHSTCFG_I2C_EN); 782 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) { 783 dev_err(&priv->pci_dev->dev, 784 "I2C block read is unsupported!\n"); 785 return -EOPNOTSUPP; 786 } 787 } 788 789 if (read_write == I2C_SMBUS_WRITE 790 || command == I2C_SMBUS_I2C_BLOCK_DATA) { 791 if (data->block[0] < 1) 792 data->block[0] = 1; 793 if (data->block[0] > I2C_SMBUS_BLOCK_MAX) 794 data->block[0] = I2C_SMBUS_BLOCK_MAX; 795 } else { 796 data->block[0] = 32; /* max for SMBus block reads */ 797 } 798 799 /* Experience has shown that the block buffer can only be used for 800 SMBus (not I2C) block transactions, even though the datasheet 801 doesn't mention this limitation. */ 802 if ((priv->features & FEATURE_BLOCK_BUFFER) 803 && command != I2C_SMBUS_I2C_BLOCK_DATA 804 && i801_set_block_buffer_mode(priv) == 0) 805 result = i801_block_transaction_by_block(priv, data, 806 read_write, hwpec); 807 else 808 result = i801_block_transaction_byte_by_byte(priv, data, 809 read_write, 810 command, hwpec); 811 812 if (command == I2C_SMBUS_I2C_BLOCK_DATA 813 && read_write == I2C_SMBUS_WRITE) { 814 /* restore saved configuration register value */ 815 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc); 816 } 817 return result; 818 } 819 820 /* Return negative errno on error. */ 821 static s32 i801_access(struct i2c_adapter *adap, u16 addr, 822 unsigned short flags, char read_write, u8 command, 823 int size, union i2c_smbus_data *data) 824 { 825 int hwpec; 826 int block = 0; 827 int ret = 0, xact = 0; 828 struct i801_priv *priv = i2c_get_adapdata(adap); 829 830 mutex_lock(&priv->acpi_lock); 831 if (priv->acpi_reserved) { 832 mutex_unlock(&priv->acpi_lock); 833 return -EBUSY; 834 } 835 836 pm_runtime_get_sync(&priv->pci_dev->dev); 837 838 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) 839 && size != I2C_SMBUS_QUICK 840 && size != I2C_SMBUS_I2C_BLOCK_DATA; 841 842 switch (size) { 843 case I2C_SMBUS_QUICK: 844 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 845 SMBHSTADD(priv)); 846 xact = I801_QUICK; 847 break; 848 case I2C_SMBUS_BYTE: 849 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 850 SMBHSTADD(priv)); 851 if (read_write == I2C_SMBUS_WRITE) 852 outb_p(command, SMBHSTCMD(priv)); 853 xact = I801_BYTE; 854 break; 855 case I2C_SMBUS_BYTE_DATA: 856 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 857 SMBHSTADD(priv)); 858 outb_p(command, SMBHSTCMD(priv)); 859 if (read_write == I2C_SMBUS_WRITE) 860 outb_p(data->byte, SMBHSTDAT0(priv)); 861 xact = I801_BYTE_DATA; 862 break; 863 case I2C_SMBUS_WORD_DATA: 864 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 865 SMBHSTADD(priv)); 866 outb_p(command, SMBHSTCMD(priv)); 867 if (read_write == I2C_SMBUS_WRITE) { 868 outb_p(data->word & 0xff, SMBHSTDAT0(priv)); 869 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); 870 } 871 xact = I801_WORD_DATA; 872 break; 873 case I2C_SMBUS_BLOCK_DATA: 874 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 875 SMBHSTADD(priv)); 876 outb_p(command, SMBHSTCMD(priv)); 877 block = 1; 878 break; 879 case I2C_SMBUS_I2C_BLOCK_DATA: 880 /* 881 * NB: page 240 of ICH5 datasheet shows that the R/#W 882 * bit should be cleared here, even when reading. 883 * However if SPD Write Disable is set (Lynx Point and later), 884 * the read will fail if we don't set the R/#W bit. 885 */ 886 outb_p(((addr & 0x7f) << 1) | 887 ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ? 888 (read_write & 0x01) : 0), 889 SMBHSTADD(priv)); 890 if (read_write == I2C_SMBUS_READ) { 891 /* NB: page 240 of ICH5 datasheet also shows 892 * that DATA1 is the cmd field when reading */ 893 outb_p(command, SMBHSTDAT1(priv)); 894 } else 895 outb_p(command, SMBHSTCMD(priv)); 896 block = 1; 897 break; 898 default: 899 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n", 900 size); 901 ret = -EOPNOTSUPP; 902 goto out; 903 } 904 905 if (hwpec) /* enable/disable hardware PEC */ 906 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv)); 907 else 908 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC), 909 SMBAUXCTL(priv)); 910 911 if (block) 912 ret = i801_block_transaction(priv, data, read_write, size, 913 hwpec); 914 else 915 ret = i801_transaction(priv, xact); 916 917 /* Some BIOSes don't like it when PEC is enabled at reboot or resume 918 time, so we forcibly disable it after every transaction. Turn off 919 E32B for the same reason. */ 920 if (hwpec || block) 921 outb_p(inb_p(SMBAUXCTL(priv)) & 922 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 923 924 if (block) 925 goto out; 926 if (ret) 927 goto out; 928 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK)) 929 goto out; 930 931 switch (xact & 0x7f) { 932 case I801_BYTE: /* Result put in SMBHSTDAT0 */ 933 case I801_BYTE_DATA: 934 data->byte = inb_p(SMBHSTDAT0(priv)); 935 break; 936 case I801_WORD_DATA: 937 data->word = inb_p(SMBHSTDAT0(priv)) + 938 (inb_p(SMBHSTDAT1(priv)) << 8); 939 break; 940 } 941 942 out: 943 pm_runtime_mark_last_busy(&priv->pci_dev->dev); 944 pm_runtime_put_autosuspend(&priv->pci_dev->dev); 945 mutex_unlock(&priv->acpi_lock); 946 return ret; 947 } 948 949 950 static u32 i801_func(struct i2c_adapter *adapter) 951 { 952 struct i801_priv *priv = i2c_get_adapdata(adapter); 953 954 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 955 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 956 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | 957 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | 958 ((priv->features & FEATURE_I2C_BLOCK_READ) ? 959 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) | 960 ((priv->features & FEATURE_HOST_NOTIFY) ? 961 I2C_FUNC_SMBUS_HOST_NOTIFY : 0); 962 } 963 964 static void i801_enable_host_notify(struct i2c_adapter *adapter) 965 { 966 struct i801_priv *priv = i2c_get_adapdata(adapter); 967 968 if (!(priv->features & FEATURE_HOST_NOTIFY)) 969 return; 970 971 if (!(SMBSLVCMD_HST_NTFY_INTREN & priv->original_slvcmd)) 972 outb_p(SMBSLVCMD_HST_NTFY_INTREN | priv->original_slvcmd, 973 SMBSLVCMD(priv)); 974 975 /* clear Host Notify bit to allow a new notification */ 976 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 977 } 978 979 static void i801_disable_host_notify(struct i801_priv *priv) 980 { 981 if (!(priv->features & FEATURE_HOST_NOTIFY)) 982 return; 983 984 outb_p(priv->original_slvcmd, SMBSLVCMD(priv)); 985 } 986 987 static const struct i2c_algorithm smbus_algorithm = { 988 .smbus_xfer = i801_access, 989 .functionality = i801_func, 990 }; 991 992 static const struct pci_device_id i801_ids[] = { 993 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) }, 994 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) }, 995 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) }, 996 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) }, 997 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) }, 998 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) }, 999 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) }, 1000 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) }, 1001 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) }, 1002 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) }, 1003 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) }, 1004 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) }, 1005 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) }, 1006 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) }, 1007 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) }, 1008 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) }, 1009 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) }, 1010 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) }, 1011 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) }, 1012 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) }, 1013 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) }, 1014 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) }, 1015 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) }, 1016 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) }, 1017 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) }, 1018 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) }, 1019 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) }, 1020 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) }, 1021 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) }, 1022 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) }, 1023 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) }, 1024 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS) }, 1025 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) }, 1026 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) }, 1027 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) }, 1028 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) }, 1029 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) }, 1030 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) }, 1031 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMBUS) }, 1032 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) }, 1033 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) }, 1034 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) }, 1035 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) }, 1036 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) }, 1037 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS) }, 1038 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS) }, 1039 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS) }, 1040 { 0, } 1041 }; 1042 1043 MODULE_DEVICE_TABLE(pci, i801_ids); 1044 1045 #if defined CONFIG_X86 && defined CONFIG_DMI 1046 static unsigned char apanel_addr; 1047 1048 /* Scan the system ROM for the signature "FJKEYINF" */ 1049 static __init const void __iomem *bios_signature(const void __iomem *bios) 1050 { 1051 ssize_t offset; 1052 const unsigned char signature[] = "FJKEYINF"; 1053 1054 for (offset = 0; offset < 0x10000; offset += 0x10) { 1055 if (check_signature(bios + offset, signature, 1056 sizeof(signature)-1)) 1057 return bios + offset; 1058 } 1059 return NULL; 1060 } 1061 1062 static void __init input_apanel_init(void) 1063 { 1064 void __iomem *bios; 1065 const void __iomem *p; 1066 1067 bios = ioremap(0xF0000, 0x10000); /* Can't fail */ 1068 p = bios_signature(bios); 1069 if (p) { 1070 /* just use the first address */ 1071 apanel_addr = readb(p + 8 + 3) >> 1; 1072 } 1073 iounmap(bios); 1074 } 1075 1076 struct dmi_onboard_device_info { 1077 const char *name; 1078 u8 type; 1079 unsigned short i2c_addr; 1080 const char *i2c_type; 1081 }; 1082 1083 static const struct dmi_onboard_device_info dmi_devices[] = { 1084 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" }, 1085 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" }, 1086 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" }, 1087 }; 1088 1089 static void dmi_check_onboard_device(u8 type, const char *name, 1090 struct i2c_adapter *adap) 1091 { 1092 int i; 1093 struct i2c_board_info info; 1094 1095 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) { 1096 /* & ~0x80, ignore enabled/disabled bit */ 1097 if ((type & ~0x80) != dmi_devices[i].type) 1098 continue; 1099 if (strcasecmp(name, dmi_devices[i].name)) 1100 continue; 1101 1102 memset(&info, 0, sizeof(struct i2c_board_info)); 1103 info.addr = dmi_devices[i].i2c_addr; 1104 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); 1105 i2c_new_device(adap, &info); 1106 break; 1107 } 1108 } 1109 1110 /* We use our own function to check for onboard devices instead of 1111 dmi_find_device() as some buggy BIOS's have the devices we are interested 1112 in marked as disabled */ 1113 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap) 1114 { 1115 int i, count; 1116 1117 if (dm->type != 10) 1118 return; 1119 1120 count = (dm->length - sizeof(struct dmi_header)) / 2; 1121 for (i = 0; i < count; i++) { 1122 const u8 *d = (char *)(dm + 1) + (i * 2); 1123 const char *name = ((char *) dm) + dm->length; 1124 u8 type = d[0]; 1125 u8 s = d[1]; 1126 1127 if (!s) 1128 continue; 1129 s--; 1130 while (s > 0 && name[0]) { 1131 name += strlen(name) + 1; 1132 s--; 1133 } 1134 if (name[0] == 0) /* Bogus string reference */ 1135 continue; 1136 1137 dmi_check_onboard_device(type, name, adap); 1138 } 1139 } 1140 1141 /* Register optional slaves */ 1142 static void i801_probe_optional_slaves(struct i801_priv *priv) 1143 { 1144 /* Only register slaves on main SMBus channel */ 1145 if (priv->features & FEATURE_IDF) 1146 return; 1147 1148 if (apanel_addr) { 1149 struct i2c_board_info info; 1150 1151 memset(&info, 0, sizeof(struct i2c_board_info)); 1152 info.addr = apanel_addr; 1153 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE); 1154 i2c_new_device(&priv->adapter, &info); 1155 } 1156 1157 if (dmi_name_in_vendors("FUJITSU")) 1158 dmi_walk(dmi_check_onboard_devices, &priv->adapter); 1159 } 1160 #else 1161 static void __init input_apanel_init(void) {} 1162 static void i801_probe_optional_slaves(struct i801_priv *priv) {} 1163 #endif /* CONFIG_X86 && CONFIG_DMI */ 1164 1165 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 1166 static struct i801_mux_config i801_mux_config_asus_z8_d12 = { 1167 .gpio_chip = "gpio_ich", 1168 .values = { 0x02, 0x03 }, 1169 .n_values = 2, 1170 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD }, 1171 .gpios = { 52, 53 }, 1172 .n_gpios = 2, 1173 }; 1174 1175 static struct i801_mux_config i801_mux_config_asus_z8_d18 = { 1176 .gpio_chip = "gpio_ich", 1177 .values = { 0x02, 0x03, 0x01 }, 1178 .n_values = 3, 1179 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD }, 1180 .gpios = { 52, 53 }, 1181 .n_gpios = 2, 1182 }; 1183 1184 static const struct dmi_system_id mux_dmi_table[] = { 1185 { 1186 .matches = { 1187 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1188 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"), 1189 }, 1190 .driver_data = &i801_mux_config_asus_z8_d12, 1191 }, 1192 { 1193 .matches = { 1194 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1195 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"), 1196 }, 1197 .driver_data = &i801_mux_config_asus_z8_d12, 1198 }, 1199 { 1200 .matches = { 1201 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1202 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"), 1203 }, 1204 .driver_data = &i801_mux_config_asus_z8_d12, 1205 }, 1206 { 1207 .matches = { 1208 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1209 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"), 1210 }, 1211 .driver_data = &i801_mux_config_asus_z8_d12, 1212 }, 1213 { 1214 .matches = { 1215 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1216 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"), 1217 }, 1218 .driver_data = &i801_mux_config_asus_z8_d12, 1219 }, 1220 { 1221 .matches = { 1222 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1223 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"), 1224 }, 1225 .driver_data = &i801_mux_config_asus_z8_d12, 1226 }, 1227 { 1228 .matches = { 1229 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1230 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"), 1231 }, 1232 .driver_data = &i801_mux_config_asus_z8_d18, 1233 }, 1234 { 1235 .matches = { 1236 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1237 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"), 1238 }, 1239 .driver_data = &i801_mux_config_asus_z8_d18, 1240 }, 1241 { 1242 .matches = { 1243 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1244 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"), 1245 }, 1246 .driver_data = &i801_mux_config_asus_z8_d12, 1247 }, 1248 { } 1249 }; 1250 1251 /* Setup multiplexing if needed */ 1252 static int i801_add_mux(struct i801_priv *priv) 1253 { 1254 struct device *dev = &priv->adapter.dev; 1255 const struct i801_mux_config *mux_config; 1256 struct i2c_mux_gpio_platform_data gpio_data; 1257 int err; 1258 1259 if (!priv->mux_drvdata) 1260 return 0; 1261 mux_config = priv->mux_drvdata; 1262 1263 /* Prepare the platform data */ 1264 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data)); 1265 gpio_data.parent = priv->adapter.nr; 1266 gpio_data.values = mux_config->values; 1267 gpio_data.n_values = mux_config->n_values; 1268 gpio_data.classes = mux_config->classes; 1269 gpio_data.gpio_chip = mux_config->gpio_chip; 1270 gpio_data.gpios = mux_config->gpios; 1271 gpio_data.n_gpios = mux_config->n_gpios; 1272 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE; 1273 1274 /* Register the mux device */ 1275 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio", 1276 PLATFORM_DEVID_AUTO, &gpio_data, 1277 sizeof(struct i2c_mux_gpio_platform_data)); 1278 if (IS_ERR(priv->mux_pdev)) { 1279 err = PTR_ERR(priv->mux_pdev); 1280 priv->mux_pdev = NULL; 1281 dev_err(dev, "Failed to register i2c-mux-gpio device\n"); 1282 return err; 1283 } 1284 1285 return 0; 1286 } 1287 1288 static void i801_del_mux(struct i801_priv *priv) 1289 { 1290 if (priv->mux_pdev) 1291 platform_device_unregister(priv->mux_pdev); 1292 } 1293 1294 static unsigned int i801_get_adapter_class(struct i801_priv *priv) 1295 { 1296 const struct dmi_system_id *id; 1297 const struct i801_mux_config *mux_config; 1298 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 1299 int i; 1300 1301 id = dmi_first_match(mux_dmi_table); 1302 if (id) { 1303 /* Remove branch classes from trunk */ 1304 mux_config = id->driver_data; 1305 for (i = 0; i < mux_config->n_values; i++) 1306 class &= ~mux_config->classes[i]; 1307 1308 /* Remember for later */ 1309 priv->mux_drvdata = mux_config; 1310 } 1311 1312 return class; 1313 } 1314 #else 1315 static inline int i801_add_mux(struct i801_priv *priv) { return 0; } 1316 static inline void i801_del_mux(struct i801_priv *priv) { } 1317 1318 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv) 1319 { 1320 return I2C_CLASS_HWMON | I2C_CLASS_SPD; 1321 } 1322 #endif 1323 1324 static const struct itco_wdt_platform_data tco_platform_data = { 1325 .name = "Intel PCH", 1326 .version = 4, 1327 }; 1328 1329 static DEFINE_SPINLOCK(p2sb_spinlock); 1330 1331 static void i801_add_tco(struct i801_priv *priv) 1332 { 1333 struct pci_dev *pci_dev = priv->pci_dev; 1334 struct resource tco_res[3], *res; 1335 struct platform_device *pdev; 1336 unsigned int devfn; 1337 u32 tco_base, tco_ctl; 1338 u32 base_addr, ctrl_val; 1339 u64 base64_addr; 1340 u8 hidden; 1341 1342 if (!(priv->features & FEATURE_TCO)) 1343 return; 1344 1345 pci_read_config_dword(pci_dev, TCOBASE, &tco_base); 1346 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl); 1347 if (!(tco_ctl & TCOCTL_EN)) 1348 return; 1349 1350 memset(tco_res, 0, sizeof(tco_res)); 1351 1352 res = &tco_res[ICH_RES_IO_TCO]; 1353 res->start = tco_base & ~1; 1354 res->end = res->start + 32 - 1; 1355 res->flags = IORESOURCE_IO; 1356 1357 /* 1358 * Power Management registers. 1359 */ 1360 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 2); 1361 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPIBASE, &base_addr); 1362 1363 res = &tco_res[ICH_RES_IO_SMI]; 1364 res->start = (base_addr & ~1) + ACPIBASE_SMI_OFF; 1365 res->end = res->start + 3; 1366 res->flags = IORESOURCE_IO; 1367 1368 /* 1369 * Enable the ACPI I/O space. 1370 */ 1371 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPICTRL, &ctrl_val); 1372 ctrl_val |= ACPICTRL_EN; 1373 pci_bus_write_config_dword(pci_dev->bus, devfn, ACPICTRL, ctrl_val); 1374 1375 /* 1376 * We must access the NO_REBOOT bit over the Primary to Sideband 1377 * bridge (P2SB). The BIOS prevents the P2SB device from being 1378 * enumerated by the PCI subsystem, so we need to unhide/hide it 1379 * to lookup the P2SB BAR. 1380 */ 1381 spin_lock(&p2sb_spinlock); 1382 1383 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1); 1384 1385 /* Unhide the P2SB device, if it is hidden */ 1386 pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden); 1387 if (hidden) 1388 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0); 1389 1390 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr); 1391 base64_addr = base_addr & 0xfffffff0; 1392 1393 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr); 1394 base64_addr |= (u64)base_addr << 32; 1395 1396 /* Hide the P2SB device, if it was hidden before */ 1397 if (hidden) 1398 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden); 1399 spin_unlock(&p2sb_spinlock); 1400 1401 res = &tco_res[ICH_RES_MEM_OFF]; 1402 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL; 1403 res->end = res->start + 3; 1404 res->flags = IORESOURCE_MEM; 1405 1406 pdev = platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1, 1407 tco_res, 3, &tco_platform_data, 1408 sizeof(tco_platform_data)); 1409 if (IS_ERR(pdev)) { 1410 dev_warn(&pci_dev->dev, "failed to create iTCO device\n"); 1411 return; 1412 } 1413 1414 priv->tco_pdev = pdev; 1415 } 1416 1417 #ifdef CONFIG_ACPI 1418 static acpi_status 1419 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits, 1420 u64 *value, void *handler_context, void *region_context) 1421 { 1422 struct i801_priv *priv = handler_context; 1423 struct pci_dev *pdev = priv->pci_dev; 1424 acpi_status status; 1425 1426 /* 1427 * Once BIOS AML code touches the OpRegion we warn and inhibit any 1428 * further access from the driver itself. This device is now owned 1429 * by the system firmware. 1430 */ 1431 mutex_lock(&priv->acpi_lock); 1432 1433 if (!priv->acpi_reserved) { 1434 priv->acpi_reserved = true; 1435 1436 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n"); 1437 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n"); 1438 1439 /* 1440 * BIOS is accessing the host controller so prevent it from 1441 * suspending automatically from now on. 1442 */ 1443 pm_runtime_get_sync(&pdev->dev); 1444 } 1445 1446 if ((function & ACPI_IO_MASK) == ACPI_READ) 1447 status = acpi_os_read_port(address, (u32 *)value, bits); 1448 else 1449 status = acpi_os_write_port(address, (u32)*value, bits); 1450 1451 mutex_unlock(&priv->acpi_lock); 1452 1453 return status; 1454 } 1455 1456 static int i801_acpi_probe(struct i801_priv *priv) 1457 { 1458 struct acpi_device *adev; 1459 acpi_status status; 1460 1461 adev = ACPI_COMPANION(&priv->pci_dev->dev); 1462 if (adev) { 1463 status = acpi_install_address_space_handler(adev->handle, 1464 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler, 1465 NULL, priv); 1466 if (ACPI_SUCCESS(status)) 1467 return 0; 1468 } 1469 1470 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]); 1471 } 1472 1473 static void i801_acpi_remove(struct i801_priv *priv) 1474 { 1475 struct acpi_device *adev; 1476 1477 adev = ACPI_COMPANION(&priv->pci_dev->dev); 1478 if (!adev) 1479 return; 1480 1481 acpi_remove_address_space_handler(adev->handle, 1482 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler); 1483 1484 mutex_lock(&priv->acpi_lock); 1485 if (priv->acpi_reserved) 1486 pm_runtime_put(&priv->pci_dev->dev); 1487 mutex_unlock(&priv->acpi_lock); 1488 } 1489 #else 1490 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; } 1491 static inline void i801_acpi_remove(struct i801_priv *priv) { } 1492 #endif 1493 1494 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id) 1495 { 1496 unsigned char temp; 1497 int err, i; 1498 struct i801_priv *priv; 1499 1500 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL); 1501 if (!priv) 1502 return -ENOMEM; 1503 1504 i2c_set_adapdata(&priv->adapter, priv); 1505 priv->adapter.owner = THIS_MODULE; 1506 priv->adapter.class = i801_get_adapter_class(priv); 1507 priv->adapter.algo = &smbus_algorithm; 1508 priv->adapter.dev.parent = &dev->dev; 1509 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev)); 1510 priv->adapter.retries = 3; 1511 mutex_init(&priv->acpi_lock); 1512 1513 priv->pci_dev = dev; 1514 switch (dev->device) { 1515 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS: 1516 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS: 1517 case PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS: 1518 case PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS: 1519 case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS: 1520 case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS: 1521 case PCI_DEVICE_ID_INTEL_CDF_SMBUS: 1522 case PCI_DEVICE_ID_INTEL_DNV_SMBUS: 1523 case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS: 1524 case PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS: 1525 priv->features |= FEATURE_I2C_BLOCK_READ; 1526 priv->features |= FEATURE_IRQ; 1527 priv->features |= FEATURE_SMBUS_PEC; 1528 priv->features |= FEATURE_BLOCK_BUFFER; 1529 /* If we have ACPI based watchdog use that instead */ 1530 if (!acpi_has_watchdog()) 1531 priv->features |= FEATURE_TCO; 1532 priv->features |= FEATURE_HOST_NOTIFY; 1533 break; 1534 1535 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0: 1536 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1: 1537 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2: 1538 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0: 1539 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1: 1540 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2: 1541 priv->features |= FEATURE_IDF; 1542 /* fall through */ 1543 default: 1544 priv->features |= FEATURE_I2C_BLOCK_READ; 1545 priv->features |= FEATURE_IRQ; 1546 /* fall through */ 1547 case PCI_DEVICE_ID_INTEL_82801DB_3: 1548 priv->features |= FEATURE_SMBUS_PEC; 1549 priv->features |= FEATURE_BLOCK_BUFFER; 1550 /* fall through */ 1551 case PCI_DEVICE_ID_INTEL_82801CA_3: 1552 priv->features |= FEATURE_HOST_NOTIFY; 1553 /* fall through */ 1554 case PCI_DEVICE_ID_INTEL_82801BA_2: 1555 case PCI_DEVICE_ID_INTEL_82801AB_3: 1556 case PCI_DEVICE_ID_INTEL_82801AA_3: 1557 break; 1558 } 1559 1560 /* Disable features on user request */ 1561 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) { 1562 if (priv->features & disable_features & (1 << i)) 1563 dev_notice(&dev->dev, "%s disabled by user\n", 1564 i801_feature_names[i]); 1565 } 1566 priv->features &= ~disable_features; 1567 1568 err = pcim_enable_device(dev); 1569 if (err) { 1570 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", 1571 err); 1572 return err; 1573 } 1574 pcim_pin_device(dev); 1575 1576 /* Determine the address of the SMBus area */ 1577 priv->smba = pci_resource_start(dev, SMBBAR); 1578 if (!priv->smba) { 1579 dev_err(&dev->dev, 1580 "SMBus base address uninitialized, upgrade BIOS\n"); 1581 return -ENODEV; 1582 } 1583 1584 if (i801_acpi_probe(priv)) 1585 return -ENODEV; 1586 1587 err = pcim_iomap_regions(dev, 1 << SMBBAR, 1588 dev_driver_string(&dev->dev)); 1589 if (err) { 1590 dev_err(&dev->dev, 1591 "Failed to request SMBus region 0x%lx-0x%Lx\n", 1592 priv->smba, 1593 (unsigned long long)pci_resource_end(dev, SMBBAR)); 1594 i801_acpi_remove(priv); 1595 return err; 1596 } 1597 1598 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp); 1599 priv->original_hstcfg = temp; 1600 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ 1601 if (!(temp & SMBHSTCFG_HST_EN)) { 1602 dev_info(&dev->dev, "Enabling SMBus device\n"); 1603 temp |= SMBHSTCFG_HST_EN; 1604 } 1605 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp); 1606 1607 if (temp & SMBHSTCFG_SMB_SMI_EN) { 1608 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); 1609 /* Disable SMBus interrupt feature if SMBus using SMI# */ 1610 priv->features &= ~FEATURE_IRQ; 1611 } 1612 if (temp & SMBHSTCFG_SPD_WD) 1613 dev_info(&dev->dev, "SPD Write Disable is set\n"); 1614 1615 /* Clear special mode bits */ 1616 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) 1617 outb_p(inb_p(SMBAUXCTL(priv)) & 1618 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 1619 1620 /* Remember original Host Notify setting */ 1621 if (priv->features & FEATURE_HOST_NOTIFY) 1622 priv->original_slvcmd = inb_p(SMBSLVCMD(priv)); 1623 1624 /* Default timeout in interrupt mode: 200 ms */ 1625 priv->adapter.timeout = HZ / 5; 1626 1627 if (dev->irq == IRQ_NOTCONNECTED) 1628 priv->features &= ~FEATURE_IRQ; 1629 1630 if (priv->features & FEATURE_IRQ) { 1631 u16 pcictl, pcists; 1632 1633 /* Complain if an interrupt is already pending */ 1634 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); 1635 if (pcists & SMBPCISTS_INTS) 1636 dev_warn(&dev->dev, "An interrupt is pending!\n"); 1637 1638 /* Check if interrupts have been disabled */ 1639 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl); 1640 if (pcictl & SMBPCICTL_INTDIS) { 1641 dev_info(&dev->dev, "Interrupts are disabled\n"); 1642 priv->features &= ~FEATURE_IRQ; 1643 } 1644 } 1645 1646 if (priv->features & FEATURE_IRQ) { 1647 init_waitqueue_head(&priv->waitq); 1648 1649 err = devm_request_irq(&dev->dev, dev->irq, i801_isr, 1650 IRQF_SHARED, 1651 dev_driver_string(&dev->dev), priv); 1652 if (err) { 1653 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n", 1654 dev->irq, err); 1655 priv->features &= ~FEATURE_IRQ; 1656 } 1657 } 1658 dev_info(&dev->dev, "SMBus using %s\n", 1659 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling"); 1660 1661 i801_add_tco(priv); 1662 1663 snprintf(priv->adapter.name, sizeof(priv->adapter.name), 1664 "SMBus I801 adapter at %04lx", priv->smba); 1665 err = i2c_add_adapter(&priv->adapter); 1666 if (err) { 1667 i801_acpi_remove(priv); 1668 return err; 1669 } 1670 1671 i801_enable_host_notify(&priv->adapter); 1672 1673 i801_probe_optional_slaves(priv); 1674 /* We ignore errors - multiplexing is optional */ 1675 i801_add_mux(priv); 1676 1677 pci_set_drvdata(dev, priv); 1678 1679 pm_runtime_set_autosuspend_delay(&dev->dev, 1000); 1680 pm_runtime_use_autosuspend(&dev->dev); 1681 pm_runtime_put_autosuspend(&dev->dev); 1682 pm_runtime_allow(&dev->dev); 1683 1684 return 0; 1685 } 1686 1687 static void i801_remove(struct pci_dev *dev) 1688 { 1689 struct i801_priv *priv = pci_get_drvdata(dev); 1690 1691 pm_runtime_forbid(&dev->dev); 1692 pm_runtime_get_noresume(&dev->dev); 1693 1694 i801_disable_host_notify(priv); 1695 i801_del_mux(priv); 1696 i2c_del_adapter(&priv->adapter); 1697 i801_acpi_remove(priv); 1698 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); 1699 1700 platform_device_unregister(priv->tco_pdev); 1701 1702 /* 1703 * do not call pci_disable_device(dev) since it can cause hard hangs on 1704 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) 1705 */ 1706 } 1707 1708 static void i801_shutdown(struct pci_dev *dev) 1709 { 1710 struct i801_priv *priv = pci_get_drvdata(dev); 1711 1712 /* Restore config registers to avoid hard hang on some systems */ 1713 i801_disable_host_notify(priv); 1714 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); 1715 } 1716 1717 #ifdef CONFIG_PM_SLEEP 1718 static int i801_suspend(struct device *dev) 1719 { 1720 struct pci_dev *pci_dev = to_pci_dev(dev); 1721 struct i801_priv *priv = pci_get_drvdata(pci_dev); 1722 1723 pci_write_config_byte(pci_dev, SMBHSTCFG, priv->original_hstcfg); 1724 return 0; 1725 } 1726 1727 static int i801_resume(struct device *dev) 1728 { 1729 struct pci_dev *pci_dev = to_pci_dev(dev); 1730 struct i801_priv *priv = pci_get_drvdata(pci_dev); 1731 1732 i801_enable_host_notify(&priv->adapter); 1733 1734 return 0; 1735 } 1736 #endif 1737 1738 static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume); 1739 1740 static struct pci_driver i801_driver = { 1741 .name = "i801_smbus", 1742 .id_table = i801_ids, 1743 .probe = i801_probe, 1744 .remove = i801_remove, 1745 .shutdown = i801_shutdown, 1746 .driver = { 1747 .pm = &i801_pm_ops, 1748 }, 1749 }; 1750 1751 static int __init i2c_i801_init(void) 1752 { 1753 if (dmi_name_in_vendors("FUJITSU")) 1754 input_apanel_init(); 1755 return pci_register_driver(&i801_driver); 1756 } 1757 1758 static void __exit i2c_i801_exit(void) 1759 { 1760 pci_unregister_driver(&i801_driver); 1761 } 1762 1763 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>"); 1764 MODULE_DESCRIPTION("I801 SMBus driver"); 1765 MODULE_LICENSE("GPL"); 1766 1767 module_init(i2c_i801_init); 1768 module_exit(i2c_i801_exit); 1769