1 /* 2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, 3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker 4 <mdsxyz123@yahoo.com> 5 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de> 6 Copyright (C) 2010 Intel Corporation, 7 David Woodhouse <dwmw2@infradead.org> 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 2 of the License, or 12 (at your option) any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 */ 19 20 /* 21 * Supports the following Intel I/O Controller Hubs (ICH): 22 * 23 * I/O Block I2C 24 * region SMBus Block proc. block 25 * Chip name PCI ID size PEC buffer call read 26 * --------------------------------------------------------------------------- 27 * 82801AA (ICH) 0x2413 16 no no no no 28 * 82801AB (ICH0) 0x2423 16 no no no no 29 * 82801BA (ICH2) 0x2443 16 no no no no 30 * 82801CA (ICH3) 0x2483 32 soft no no no 31 * 82801DB (ICH4) 0x24c3 32 hard yes no no 32 * 82801E (ICH5) 0x24d3 32 hard yes yes yes 33 * 6300ESB 0x25a4 32 hard yes yes yes 34 * 82801F (ICH6) 0x266a 32 hard yes yes yes 35 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes 36 * 82801G (ICH7) 0x27da 32 hard yes yes yes 37 * 82801H (ICH8) 0x283e 32 hard yes yes yes 38 * 82801I (ICH9) 0x2930 32 hard yes yes yes 39 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes 40 * ICH10 0x3a30 32 hard yes yes yes 41 * ICH10 0x3a60 32 hard yes yes yes 42 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes 43 * 6 Series (PCH) 0x1c22 32 hard yes yes yes 44 * Patsburg (PCH) 0x1d22 32 hard yes yes yes 45 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes 46 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes 47 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes 48 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes 49 * Panther Point (PCH) 0x1e22 32 hard yes yes yes 50 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes 51 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes 52 * Avoton (SOC) 0x1f3c 32 hard yes yes yes 53 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes 54 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes 55 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes 56 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes 57 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes 58 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes 59 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes 60 * BayTrail (SOC) 0x0f12 32 hard yes yes yes 61 * Braswell (SOC) 0x2292 32 hard yes yes yes 62 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes 63 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes 64 * DNV (SOC) 0x19df 32 hard yes yes yes 65 * Broxton (SOC) 0x5ad4 32 hard yes yes yes 66 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes 67 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes 68 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes 69 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes 70 * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes 71 * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes 72 * Cedar Fork (PCH) 0x18df 32 hard yes yes yes 73 * 74 * Features supported by this driver: 75 * Software PEC no 76 * Hardware PEC yes 77 * Block buffer yes 78 * Block process call transaction no 79 * I2C block read transaction yes (doesn't use the block buffer) 80 * Slave mode no 81 * SMBus Host Notify yes 82 * Interrupt processing yes 83 * 84 * See the file Documentation/i2c/busses/i2c-i801 for details. 85 */ 86 87 #include <linux/interrupt.h> 88 #include <linux/module.h> 89 #include <linux/pci.h> 90 #include <linux/kernel.h> 91 #include <linux/stddef.h> 92 #include <linux/delay.h> 93 #include <linux/ioport.h> 94 #include <linux/init.h> 95 #include <linux/i2c.h> 96 #include <linux/i2c-smbus.h> 97 #include <linux/acpi.h> 98 #include <linux/io.h> 99 #include <linux/dmi.h> 100 #include <linux/slab.h> 101 #include <linux/wait.h> 102 #include <linux/err.h> 103 #include <linux/platform_device.h> 104 #include <linux/platform_data/itco_wdt.h> 105 #include <linux/pm_runtime.h> 106 107 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 108 #include <linux/gpio.h> 109 #include <linux/platform_data/i2c-mux-gpio.h> 110 #endif 111 112 /* I801 SMBus address offsets */ 113 #define SMBHSTSTS(p) (0 + (p)->smba) 114 #define SMBHSTCNT(p) (2 + (p)->smba) 115 #define SMBHSTCMD(p) (3 + (p)->smba) 116 #define SMBHSTADD(p) (4 + (p)->smba) 117 #define SMBHSTDAT0(p) (5 + (p)->smba) 118 #define SMBHSTDAT1(p) (6 + (p)->smba) 119 #define SMBBLKDAT(p) (7 + (p)->smba) 120 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */ 121 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */ 122 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */ 123 #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */ 124 #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */ 125 #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */ 126 127 /* PCI Address Constants */ 128 #define SMBBAR 4 129 #define SMBPCICTL 0x004 130 #define SMBPCISTS 0x006 131 #define SMBHSTCFG 0x040 132 #define TCOBASE 0x050 133 #define TCOCTL 0x054 134 135 #define ACPIBASE 0x040 136 #define ACPIBASE_SMI_OFF 0x030 137 #define ACPICTRL 0x044 138 #define ACPICTRL_EN 0x080 139 140 #define SBREG_BAR 0x10 141 #define SBREG_SMBCTRL 0xc6000c 142 143 /* Host status bits for SMBPCISTS */ 144 #define SMBPCISTS_INTS BIT(3) 145 146 /* Control bits for SMBPCICTL */ 147 #define SMBPCICTL_INTDIS BIT(10) 148 149 /* Host configuration bits for SMBHSTCFG */ 150 #define SMBHSTCFG_HST_EN BIT(0) 151 #define SMBHSTCFG_SMB_SMI_EN BIT(1) 152 #define SMBHSTCFG_I2C_EN BIT(2) 153 #define SMBHSTCFG_SPD_WD BIT(4) 154 155 /* TCO configuration bits for TCOCTL */ 156 #define TCOCTL_EN BIT(8) 157 158 /* Auxiliary status register bits, ICH4+ only */ 159 #define SMBAUXSTS_CRCE BIT(0) 160 #define SMBAUXSTS_STCO BIT(1) 161 162 /* Auxiliary control register bits, ICH4+ only */ 163 #define SMBAUXCTL_CRC BIT(0) 164 #define SMBAUXCTL_E32B BIT(1) 165 166 /* Other settings */ 167 #define MAX_RETRIES 400 168 169 /* I801 command constants */ 170 #define I801_QUICK 0x00 171 #define I801_BYTE 0x04 172 #define I801_BYTE_DATA 0x08 173 #define I801_WORD_DATA 0x0C 174 #define I801_PROC_CALL 0x10 /* unimplemented */ 175 #define I801_BLOCK_DATA 0x14 176 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ 177 178 /* I801 Host Control register bits */ 179 #define SMBHSTCNT_INTREN BIT(0) 180 #define SMBHSTCNT_KILL BIT(1) 181 #define SMBHSTCNT_LAST_BYTE BIT(5) 182 #define SMBHSTCNT_START BIT(6) 183 #define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */ 184 185 /* I801 Hosts Status register bits */ 186 #define SMBHSTSTS_BYTE_DONE BIT(7) 187 #define SMBHSTSTS_INUSE_STS BIT(6) 188 #define SMBHSTSTS_SMBALERT_STS BIT(5) 189 #define SMBHSTSTS_FAILED BIT(4) 190 #define SMBHSTSTS_BUS_ERR BIT(3) 191 #define SMBHSTSTS_DEV_ERR BIT(2) 192 #define SMBHSTSTS_INTR BIT(1) 193 #define SMBHSTSTS_HOST_BUSY BIT(0) 194 195 /* Host Notify Status register bits */ 196 #define SMBSLVSTS_HST_NTFY_STS BIT(0) 197 198 /* Host Notify Command register bits */ 199 #define SMBSLVCMD_HST_NTFY_INTREN BIT(0) 200 201 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \ 202 SMBHSTSTS_DEV_ERR) 203 204 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \ 205 STATUS_ERROR_FLAGS) 206 207 /* Older devices have their ID defined in <linux/pci_ids.h> */ 208 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12 209 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df 210 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df 211 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 212 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 213 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */ 214 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70 215 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71 216 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72 217 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 218 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c 219 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292 220 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 221 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0 222 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4 223 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 224 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4 225 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 226 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2 227 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22 228 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d 229 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e 230 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f 231 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22 232 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2 233 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23 234 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3 235 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123 236 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3 237 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223 238 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3 239 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323 240 241 struct i801_mux_config { 242 char *gpio_chip; 243 unsigned values[3]; 244 int n_values; 245 unsigned classes[3]; 246 unsigned gpios[2]; /* Relative to gpio_chip->base */ 247 int n_gpios; 248 }; 249 250 struct i801_priv { 251 struct i2c_adapter adapter; 252 unsigned long smba; 253 unsigned char original_hstcfg; 254 unsigned char original_slvcmd; 255 struct pci_dev *pci_dev; 256 unsigned int features; 257 258 /* isr processing */ 259 wait_queue_head_t waitq; 260 u8 status; 261 262 /* Command state used by isr for byte-by-byte block transactions */ 263 u8 cmd; 264 bool is_read; 265 int count; 266 int len; 267 u8 *data; 268 269 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 270 const struct i801_mux_config *mux_drvdata; 271 struct platform_device *mux_pdev; 272 #endif 273 struct platform_device *tco_pdev; 274 275 /* 276 * If set to true the host controller registers are reserved for 277 * ACPI AML use. Protected by acpi_lock. 278 */ 279 bool acpi_reserved; 280 struct mutex acpi_lock; 281 }; 282 283 #define FEATURE_SMBUS_PEC BIT(0) 284 #define FEATURE_BLOCK_BUFFER BIT(1) 285 #define FEATURE_BLOCK_PROC BIT(2) 286 #define FEATURE_I2C_BLOCK_READ BIT(3) 287 #define FEATURE_IRQ BIT(4) 288 #define FEATURE_HOST_NOTIFY BIT(5) 289 /* Not really a feature, but it's convenient to handle it as such */ 290 #define FEATURE_IDF BIT(15) 291 #define FEATURE_TCO BIT(16) 292 293 static const char *i801_feature_names[] = { 294 "SMBus PEC", 295 "Block buffer", 296 "Block process call", 297 "I2C block read", 298 "Interrupt", 299 "SMBus Host Notify", 300 }; 301 302 static unsigned int disable_features; 303 module_param(disable_features, uint, S_IRUGO | S_IWUSR); 304 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n" 305 "\t\t 0x01 disable SMBus PEC\n" 306 "\t\t 0x02 disable the block buffer\n" 307 "\t\t 0x08 disable the I2C block read functionality\n" 308 "\t\t 0x10 don't use interrupts\n" 309 "\t\t 0x20 disable SMBus Host Notify "); 310 311 /* Make sure the SMBus host is ready to start transmitting. 312 Return 0 if it is, -EBUSY if it is not. */ 313 static int i801_check_pre(struct i801_priv *priv) 314 { 315 int status; 316 317 status = inb_p(SMBHSTSTS(priv)); 318 if (status & SMBHSTSTS_HOST_BUSY) { 319 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n"); 320 return -EBUSY; 321 } 322 323 status &= STATUS_FLAGS; 324 if (status) { 325 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n", 326 status); 327 outb_p(status, SMBHSTSTS(priv)); 328 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS; 329 if (status) { 330 dev_err(&priv->pci_dev->dev, 331 "Failed clearing status flags (%02x)\n", 332 status); 333 return -EBUSY; 334 } 335 } 336 337 /* 338 * Clear CRC status if needed. 339 * During normal operation, i801_check_post() takes care 340 * of it after every operation. We do it here only in case 341 * the hardware was already in this state when the driver 342 * started. 343 */ 344 if (priv->features & FEATURE_SMBUS_PEC) { 345 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE; 346 if (status) { 347 dev_dbg(&priv->pci_dev->dev, 348 "Clearing aux status flags (%02x)\n", status); 349 outb_p(status, SMBAUXSTS(priv)); 350 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE; 351 if (status) { 352 dev_err(&priv->pci_dev->dev, 353 "Failed clearing aux status flags (%02x)\n", 354 status); 355 return -EBUSY; 356 } 357 } 358 } 359 360 return 0; 361 } 362 363 /* 364 * Convert the status register to an error code, and clear it. 365 * Note that status only contains the bits we want to clear, not the 366 * actual register value. 367 */ 368 static int i801_check_post(struct i801_priv *priv, int status) 369 { 370 int result = 0; 371 372 /* 373 * If the SMBus is still busy, we give up 374 * Note: This timeout condition only happens when using polling 375 * transactions. For interrupt operation, NAK/timeout is indicated by 376 * DEV_ERR. 377 */ 378 if (unlikely(status < 0)) { 379 dev_err(&priv->pci_dev->dev, "Transaction timeout\n"); 380 /* try to stop the current command */ 381 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n"); 382 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL, 383 SMBHSTCNT(priv)); 384 usleep_range(1000, 2000); 385 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL), 386 SMBHSTCNT(priv)); 387 388 /* Check if it worked */ 389 status = inb_p(SMBHSTSTS(priv)); 390 if ((status & SMBHSTSTS_HOST_BUSY) || 391 !(status & SMBHSTSTS_FAILED)) 392 dev_err(&priv->pci_dev->dev, 393 "Failed terminating the transaction\n"); 394 outb_p(STATUS_FLAGS, SMBHSTSTS(priv)); 395 return -ETIMEDOUT; 396 } 397 398 if (status & SMBHSTSTS_FAILED) { 399 result = -EIO; 400 dev_err(&priv->pci_dev->dev, "Transaction failed\n"); 401 } 402 if (status & SMBHSTSTS_DEV_ERR) { 403 /* 404 * This may be a PEC error, check and clear it. 405 * 406 * AUXSTS is handled differently from HSTSTS. 407 * For HSTSTS, i801_isr() or i801_wait_intr() 408 * has already cleared the error bits in hardware, 409 * and we are passed a copy of the original value 410 * in "status". 411 * For AUXSTS, the hardware register is left 412 * for us to handle here. 413 * This is asymmetric, slightly iffy, but safe, 414 * since all this code is serialized and the CRCE 415 * bit is harmless as long as it's cleared before 416 * the next operation. 417 */ 418 if ((priv->features & FEATURE_SMBUS_PEC) && 419 (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) { 420 outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv)); 421 result = -EBADMSG; 422 dev_dbg(&priv->pci_dev->dev, "PEC error\n"); 423 } else { 424 result = -ENXIO; 425 dev_dbg(&priv->pci_dev->dev, "No response\n"); 426 } 427 } 428 if (status & SMBHSTSTS_BUS_ERR) { 429 result = -EAGAIN; 430 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n"); 431 } 432 433 /* Clear status flags except BYTE_DONE, to be cleared by caller */ 434 outb_p(status, SMBHSTSTS(priv)); 435 436 return result; 437 } 438 439 /* Wait for BUSY being cleared and either INTR or an error flag being set */ 440 static int i801_wait_intr(struct i801_priv *priv) 441 { 442 int timeout = 0; 443 int status; 444 445 /* We will always wait for a fraction of a second! */ 446 do { 447 usleep_range(250, 500); 448 status = inb_p(SMBHSTSTS(priv)); 449 } while (((status & SMBHSTSTS_HOST_BUSY) || 450 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) && 451 (timeout++ < MAX_RETRIES)); 452 453 if (timeout > MAX_RETRIES) { 454 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n"); 455 return -ETIMEDOUT; 456 } 457 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR); 458 } 459 460 /* Wait for either BYTE_DONE or an error flag being set */ 461 static int i801_wait_byte_done(struct i801_priv *priv) 462 { 463 int timeout = 0; 464 int status; 465 466 /* We will always wait for a fraction of a second! */ 467 do { 468 usleep_range(250, 500); 469 status = inb_p(SMBHSTSTS(priv)); 470 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) && 471 (timeout++ < MAX_RETRIES)); 472 473 if (timeout > MAX_RETRIES) { 474 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n"); 475 return -ETIMEDOUT; 476 } 477 return status & STATUS_ERROR_FLAGS; 478 } 479 480 static int i801_transaction(struct i801_priv *priv, int xact) 481 { 482 int status; 483 int result; 484 const struct i2c_adapter *adap = &priv->adapter; 485 486 result = i801_check_pre(priv); 487 if (result < 0) 488 return result; 489 490 if (priv->features & FEATURE_IRQ) { 491 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START, 492 SMBHSTCNT(priv)); 493 result = wait_event_timeout(priv->waitq, 494 (status = priv->status), 495 adap->timeout); 496 if (!result) { 497 status = -ETIMEDOUT; 498 dev_warn(&priv->pci_dev->dev, 499 "Timeout waiting for interrupt!\n"); 500 } 501 priv->status = 0; 502 return i801_check_post(priv, status); 503 } 504 505 /* the current contents of SMBHSTCNT can be overwritten, since PEC, 506 * SMBSCMD are passed in xact */ 507 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv)); 508 509 status = i801_wait_intr(priv); 510 return i801_check_post(priv, status); 511 } 512 513 static int i801_block_transaction_by_block(struct i801_priv *priv, 514 union i2c_smbus_data *data, 515 char read_write, int hwpec) 516 { 517 int i, len; 518 int status; 519 520 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ 521 522 /* Use 32-byte buffer to process this transaction */ 523 if (read_write == I2C_SMBUS_WRITE) { 524 len = data->block[0]; 525 outb_p(len, SMBHSTDAT0(priv)); 526 for (i = 0; i < len; i++) 527 outb_p(data->block[i+1], SMBBLKDAT(priv)); 528 } 529 530 status = i801_transaction(priv, I801_BLOCK_DATA | 531 (hwpec ? SMBHSTCNT_PEC_EN : 0)); 532 if (status) 533 return status; 534 535 if (read_write == I2C_SMBUS_READ) { 536 len = inb_p(SMBHSTDAT0(priv)); 537 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) 538 return -EPROTO; 539 540 data->block[0] = len; 541 for (i = 0; i < len; i++) 542 data->block[i + 1] = inb_p(SMBBLKDAT(priv)); 543 } 544 return 0; 545 } 546 547 static void i801_isr_byte_done(struct i801_priv *priv) 548 { 549 if (priv->is_read) { 550 /* For SMBus block reads, length is received with first byte */ 551 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) && 552 (priv->count == 0)) { 553 priv->len = inb_p(SMBHSTDAT0(priv)); 554 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) { 555 dev_err(&priv->pci_dev->dev, 556 "Illegal SMBus block read size %d\n", 557 priv->len); 558 /* FIXME: Recover */ 559 priv->len = I2C_SMBUS_BLOCK_MAX; 560 } else { 561 dev_dbg(&priv->pci_dev->dev, 562 "SMBus block read size is %d\n", 563 priv->len); 564 } 565 priv->data[-1] = priv->len; 566 } 567 568 /* Read next byte */ 569 if (priv->count < priv->len) 570 priv->data[priv->count++] = inb(SMBBLKDAT(priv)); 571 else 572 dev_dbg(&priv->pci_dev->dev, 573 "Discarding extra byte on block read\n"); 574 575 /* Set LAST_BYTE for last byte of read transaction */ 576 if (priv->count == priv->len - 1) 577 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE, 578 SMBHSTCNT(priv)); 579 } else if (priv->count < priv->len - 1) { 580 /* Write next byte, except for IRQ after last byte */ 581 outb_p(priv->data[++priv->count], SMBBLKDAT(priv)); 582 } 583 584 /* Clear BYTE_DONE to continue with next byte */ 585 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 586 } 587 588 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv) 589 { 590 unsigned short addr; 591 592 addr = inb_p(SMBNTFDADD(priv)) >> 1; 593 594 /* 595 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba) 596 * always returns 0. Our current implementation doesn't provide 597 * data, so we just ignore it. 598 */ 599 i2c_handle_smbus_host_notify(&priv->adapter, addr); 600 601 /* clear Host Notify bit and return */ 602 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 603 return IRQ_HANDLED; 604 } 605 606 /* 607 * There are three kinds of interrupts: 608 * 609 * 1) i801 signals transaction completion with one of these interrupts: 610 * INTR - Success 611 * DEV_ERR - Invalid command, NAK or communication timeout 612 * BUS_ERR - SMI# transaction collision 613 * FAILED - transaction was canceled due to a KILL request 614 * When any of these occur, update ->status and wake up the waitq. 615 * ->status must be cleared before kicking off the next transaction. 616 * 617 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt 618 * occurs for each byte of a byte-by-byte to prepare the next byte. 619 * 620 * 3) Host Notify interrupts 621 */ 622 static irqreturn_t i801_isr(int irq, void *dev_id) 623 { 624 struct i801_priv *priv = dev_id; 625 u16 pcists; 626 u8 status; 627 628 /* Confirm this is our interrupt */ 629 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); 630 if (!(pcists & SMBPCISTS_INTS)) 631 return IRQ_NONE; 632 633 if (priv->features & FEATURE_HOST_NOTIFY) { 634 status = inb_p(SMBSLVSTS(priv)); 635 if (status & SMBSLVSTS_HST_NTFY_STS) 636 return i801_host_notify_isr(priv); 637 } 638 639 status = inb_p(SMBHSTSTS(priv)); 640 if (status & SMBHSTSTS_BYTE_DONE) 641 i801_isr_byte_done(priv); 642 643 /* 644 * Clear irq sources and report transaction result. 645 * ->status must be cleared before the next transaction is started. 646 */ 647 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS; 648 if (status) { 649 outb_p(status, SMBHSTSTS(priv)); 650 priv->status = status; 651 wake_up(&priv->waitq); 652 } 653 654 return IRQ_HANDLED; 655 } 656 657 /* 658 * For "byte-by-byte" block transactions: 659 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1 660 * I2C read uses cmd=I801_I2C_BLOCK_DATA 661 */ 662 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, 663 union i2c_smbus_data *data, 664 char read_write, int command, 665 int hwpec) 666 { 667 int i, len; 668 int smbcmd; 669 int status; 670 int result; 671 const struct i2c_adapter *adap = &priv->adapter; 672 673 result = i801_check_pre(priv); 674 if (result < 0) 675 return result; 676 677 len = data->block[0]; 678 679 if (read_write == I2C_SMBUS_WRITE) { 680 outb_p(len, SMBHSTDAT0(priv)); 681 outb_p(data->block[1], SMBBLKDAT(priv)); 682 } 683 684 if (command == I2C_SMBUS_I2C_BLOCK_DATA && 685 read_write == I2C_SMBUS_READ) 686 smbcmd = I801_I2C_BLOCK_DATA; 687 else 688 smbcmd = I801_BLOCK_DATA; 689 690 if (priv->features & FEATURE_IRQ) { 691 priv->is_read = (read_write == I2C_SMBUS_READ); 692 if (len == 1 && priv->is_read) 693 smbcmd |= SMBHSTCNT_LAST_BYTE; 694 priv->cmd = smbcmd | SMBHSTCNT_INTREN; 695 priv->len = len; 696 priv->count = 0; 697 priv->data = &data->block[1]; 698 699 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv)); 700 result = wait_event_timeout(priv->waitq, 701 (status = priv->status), 702 adap->timeout); 703 if (!result) { 704 status = -ETIMEDOUT; 705 dev_warn(&priv->pci_dev->dev, 706 "Timeout waiting for interrupt!\n"); 707 } 708 priv->status = 0; 709 return i801_check_post(priv, status); 710 } 711 712 for (i = 1; i <= len; i++) { 713 if (i == len && read_write == I2C_SMBUS_READ) 714 smbcmd |= SMBHSTCNT_LAST_BYTE; 715 outb_p(smbcmd, SMBHSTCNT(priv)); 716 717 if (i == 1) 718 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START, 719 SMBHSTCNT(priv)); 720 721 status = i801_wait_byte_done(priv); 722 if (status) 723 goto exit; 724 725 if (i == 1 && read_write == I2C_SMBUS_READ 726 && command != I2C_SMBUS_I2C_BLOCK_DATA) { 727 len = inb_p(SMBHSTDAT0(priv)); 728 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { 729 dev_err(&priv->pci_dev->dev, 730 "Illegal SMBus block read size %d\n", 731 len); 732 /* Recover */ 733 while (inb_p(SMBHSTSTS(priv)) & 734 SMBHSTSTS_HOST_BUSY) 735 outb_p(SMBHSTSTS_BYTE_DONE, 736 SMBHSTSTS(priv)); 737 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); 738 return -EPROTO; 739 } 740 data->block[0] = len; 741 } 742 743 /* Retrieve/store value in SMBBLKDAT */ 744 if (read_write == I2C_SMBUS_READ) 745 data->block[i] = inb_p(SMBBLKDAT(priv)); 746 if (read_write == I2C_SMBUS_WRITE && i+1 <= len) 747 outb_p(data->block[i+1], SMBBLKDAT(priv)); 748 749 /* signals SMBBLKDAT ready */ 750 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 751 } 752 753 status = i801_wait_intr(priv); 754 exit: 755 return i801_check_post(priv, status); 756 } 757 758 static int i801_set_block_buffer_mode(struct i801_priv *priv) 759 { 760 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv)); 761 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0) 762 return -EIO; 763 return 0; 764 } 765 766 /* Block transaction function */ 767 static int i801_block_transaction(struct i801_priv *priv, 768 union i2c_smbus_data *data, char read_write, 769 int command, int hwpec) 770 { 771 int result = 0; 772 unsigned char hostc; 773 774 if (command == I2C_SMBUS_I2C_BLOCK_DATA) { 775 if (read_write == I2C_SMBUS_WRITE) { 776 /* set I2C_EN bit in configuration register */ 777 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc); 778 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, 779 hostc | SMBHSTCFG_I2C_EN); 780 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) { 781 dev_err(&priv->pci_dev->dev, 782 "I2C block read is unsupported!\n"); 783 return -EOPNOTSUPP; 784 } 785 } 786 787 if (read_write == I2C_SMBUS_WRITE 788 || command == I2C_SMBUS_I2C_BLOCK_DATA) { 789 if (data->block[0] < 1) 790 data->block[0] = 1; 791 if (data->block[0] > I2C_SMBUS_BLOCK_MAX) 792 data->block[0] = I2C_SMBUS_BLOCK_MAX; 793 } else { 794 data->block[0] = 32; /* max for SMBus block reads */ 795 } 796 797 /* Experience has shown that the block buffer can only be used for 798 SMBus (not I2C) block transactions, even though the datasheet 799 doesn't mention this limitation. */ 800 if ((priv->features & FEATURE_BLOCK_BUFFER) 801 && command != I2C_SMBUS_I2C_BLOCK_DATA 802 && i801_set_block_buffer_mode(priv) == 0) 803 result = i801_block_transaction_by_block(priv, data, 804 read_write, hwpec); 805 else 806 result = i801_block_transaction_byte_by_byte(priv, data, 807 read_write, 808 command, hwpec); 809 810 if (command == I2C_SMBUS_I2C_BLOCK_DATA 811 && read_write == I2C_SMBUS_WRITE) { 812 /* restore saved configuration register value */ 813 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc); 814 } 815 return result; 816 } 817 818 /* Return negative errno on error. */ 819 static s32 i801_access(struct i2c_adapter *adap, u16 addr, 820 unsigned short flags, char read_write, u8 command, 821 int size, union i2c_smbus_data *data) 822 { 823 int hwpec; 824 int block = 0; 825 int ret = 0, xact = 0; 826 struct i801_priv *priv = i2c_get_adapdata(adap); 827 828 mutex_lock(&priv->acpi_lock); 829 if (priv->acpi_reserved) { 830 mutex_unlock(&priv->acpi_lock); 831 return -EBUSY; 832 } 833 834 pm_runtime_get_sync(&priv->pci_dev->dev); 835 836 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) 837 && size != I2C_SMBUS_QUICK 838 && size != I2C_SMBUS_I2C_BLOCK_DATA; 839 840 switch (size) { 841 case I2C_SMBUS_QUICK: 842 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 843 SMBHSTADD(priv)); 844 xact = I801_QUICK; 845 break; 846 case I2C_SMBUS_BYTE: 847 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 848 SMBHSTADD(priv)); 849 if (read_write == I2C_SMBUS_WRITE) 850 outb_p(command, SMBHSTCMD(priv)); 851 xact = I801_BYTE; 852 break; 853 case I2C_SMBUS_BYTE_DATA: 854 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 855 SMBHSTADD(priv)); 856 outb_p(command, SMBHSTCMD(priv)); 857 if (read_write == I2C_SMBUS_WRITE) 858 outb_p(data->byte, SMBHSTDAT0(priv)); 859 xact = I801_BYTE_DATA; 860 break; 861 case I2C_SMBUS_WORD_DATA: 862 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 863 SMBHSTADD(priv)); 864 outb_p(command, SMBHSTCMD(priv)); 865 if (read_write == I2C_SMBUS_WRITE) { 866 outb_p(data->word & 0xff, SMBHSTDAT0(priv)); 867 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); 868 } 869 xact = I801_WORD_DATA; 870 break; 871 case I2C_SMBUS_BLOCK_DATA: 872 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 873 SMBHSTADD(priv)); 874 outb_p(command, SMBHSTCMD(priv)); 875 block = 1; 876 break; 877 case I2C_SMBUS_I2C_BLOCK_DATA: 878 /* 879 * NB: page 240 of ICH5 datasheet shows that the R/#W 880 * bit should be cleared here, even when reading. 881 * However if SPD Write Disable is set (Lynx Point and later), 882 * the read will fail if we don't set the R/#W bit. 883 */ 884 outb_p(((addr & 0x7f) << 1) | 885 ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ? 886 (read_write & 0x01) : 0), 887 SMBHSTADD(priv)); 888 if (read_write == I2C_SMBUS_READ) { 889 /* NB: page 240 of ICH5 datasheet also shows 890 * that DATA1 is the cmd field when reading */ 891 outb_p(command, SMBHSTDAT1(priv)); 892 } else 893 outb_p(command, SMBHSTCMD(priv)); 894 block = 1; 895 break; 896 default: 897 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n", 898 size); 899 ret = -EOPNOTSUPP; 900 goto out; 901 } 902 903 if (hwpec) /* enable/disable hardware PEC */ 904 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv)); 905 else 906 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC), 907 SMBAUXCTL(priv)); 908 909 if (block) 910 ret = i801_block_transaction(priv, data, read_write, size, 911 hwpec); 912 else 913 ret = i801_transaction(priv, xact); 914 915 /* Some BIOSes don't like it when PEC is enabled at reboot or resume 916 time, so we forcibly disable it after every transaction. Turn off 917 E32B for the same reason. */ 918 if (hwpec || block) 919 outb_p(inb_p(SMBAUXCTL(priv)) & 920 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 921 922 if (block) 923 goto out; 924 if (ret) 925 goto out; 926 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK)) 927 goto out; 928 929 switch (xact & 0x7f) { 930 case I801_BYTE: /* Result put in SMBHSTDAT0 */ 931 case I801_BYTE_DATA: 932 data->byte = inb_p(SMBHSTDAT0(priv)); 933 break; 934 case I801_WORD_DATA: 935 data->word = inb_p(SMBHSTDAT0(priv)) + 936 (inb_p(SMBHSTDAT1(priv)) << 8); 937 break; 938 } 939 940 out: 941 pm_runtime_mark_last_busy(&priv->pci_dev->dev); 942 pm_runtime_put_autosuspend(&priv->pci_dev->dev); 943 mutex_unlock(&priv->acpi_lock); 944 return ret; 945 } 946 947 948 static u32 i801_func(struct i2c_adapter *adapter) 949 { 950 struct i801_priv *priv = i2c_get_adapdata(adapter); 951 952 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 953 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 954 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | 955 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | 956 ((priv->features & FEATURE_I2C_BLOCK_READ) ? 957 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) | 958 ((priv->features & FEATURE_HOST_NOTIFY) ? 959 I2C_FUNC_SMBUS_HOST_NOTIFY : 0); 960 } 961 962 static void i801_enable_host_notify(struct i2c_adapter *adapter) 963 { 964 struct i801_priv *priv = i2c_get_adapdata(adapter); 965 966 if (!(priv->features & FEATURE_HOST_NOTIFY)) 967 return; 968 969 if (!(SMBSLVCMD_HST_NTFY_INTREN & priv->original_slvcmd)) 970 outb_p(SMBSLVCMD_HST_NTFY_INTREN | priv->original_slvcmd, 971 SMBSLVCMD(priv)); 972 973 /* clear Host Notify bit to allow a new notification */ 974 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 975 } 976 977 static void i801_disable_host_notify(struct i801_priv *priv) 978 { 979 if (!(priv->features & FEATURE_HOST_NOTIFY)) 980 return; 981 982 outb_p(priv->original_slvcmd, SMBSLVCMD(priv)); 983 } 984 985 static const struct i2c_algorithm smbus_algorithm = { 986 .smbus_xfer = i801_access, 987 .functionality = i801_func, 988 }; 989 990 static const struct pci_device_id i801_ids[] = { 991 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) }, 992 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) }, 993 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) }, 994 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) }, 995 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) }, 996 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) }, 997 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) }, 998 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) }, 999 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) }, 1000 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) }, 1001 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) }, 1002 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) }, 1003 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) }, 1004 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) }, 1005 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) }, 1006 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) }, 1007 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) }, 1008 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) }, 1009 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) }, 1010 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) }, 1011 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) }, 1012 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) }, 1013 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) }, 1014 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) }, 1015 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) }, 1016 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) }, 1017 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) }, 1018 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) }, 1019 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) }, 1020 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) }, 1021 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) }, 1022 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS) }, 1023 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) }, 1024 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) }, 1025 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) }, 1026 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) }, 1027 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) }, 1028 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) }, 1029 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMBUS) }, 1030 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) }, 1031 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) }, 1032 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) }, 1033 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) }, 1034 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) }, 1035 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS) }, 1036 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS) }, 1037 { 0, } 1038 }; 1039 1040 MODULE_DEVICE_TABLE(pci, i801_ids); 1041 1042 #if defined CONFIG_X86 && defined CONFIG_DMI 1043 static unsigned char apanel_addr; 1044 1045 /* Scan the system ROM for the signature "FJKEYINF" */ 1046 static __init const void __iomem *bios_signature(const void __iomem *bios) 1047 { 1048 ssize_t offset; 1049 const unsigned char signature[] = "FJKEYINF"; 1050 1051 for (offset = 0; offset < 0x10000; offset += 0x10) { 1052 if (check_signature(bios + offset, signature, 1053 sizeof(signature)-1)) 1054 return bios + offset; 1055 } 1056 return NULL; 1057 } 1058 1059 static void __init input_apanel_init(void) 1060 { 1061 void __iomem *bios; 1062 const void __iomem *p; 1063 1064 bios = ioremap(0xF0000, 0x10000); /* Can't fail */ 1065 p = bios_signature(bios); 1066 if (p) { 1067 /* just use the first address */ 1068 apanel_addr = readb(p + 8 + 3) >> 1; 1069 } 1070 iounmap(bios); 1071 } 1072 1073 struct dmi_onboard_device_info { 1074 const char *name; 1075 u8 type; 1076 unsigned short i2c_addr; 1077 const char *i2c_type; 1078 }; 1079 1080 static const struct dmi_onboard_device_info dmi_devices[] = { 1081 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" }, 1082 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" }, 1083 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" }, 1084 }; 1085 1086 static void dmi_check_onboard_device(u8 type, const char *name, 1087 struct i2c_adapter *adap) 1088 { 1089 int i; 1090 struct i2c_board_info info; 1091 1092 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) { 1093 /* & ~0x80, ignore enabled/disabled bit */ 1094 if ((type & ~0x80) != dmi_devices[i].type) 1095 continue; 1096 if (strcasecmp(name, dmi_devices[i].name)) 1097 continue; 1098 1099 memset(&info, 0, sizeof(struct i2c_board_info)); 1100 info.addr = dmi_devices[i].i2c_addr; 1101 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); 1102 i2c_new_device(adap, &info); 1103 break; 1104 } 1105 } 1106 1107 /* We use our own function to check for onboard devices instead of 1108 dmi_find_device() as some buggy BIOS's have the devices we are interested 1109 in marked as disabled */ 1110 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap) 1111 { 1112 int i, count; 1113 1114 if (dm->type != 10) 1115 return; 1116 1117 count = (dm->length - sizeof(struct dmi_header)) / 2; 1118 for (i = 0; i < count; i++) { 1119 const u8 *d = (char *)(dm + 1) + (i * 2); 1120 const char *name = ((char *) dm) + dm->length; 1121 u8 type = d[0]; 1122 u8 s = d[1]; 1123 1124 if (!s) 1125 continue; 1126 s--; 1127 while (s > 0 && name[0]) { 1128 name += strlen(name) + 1; 1129 s--; 1130 } 1131 if (name[0] == 0) /* Bogus string reference */ 1132 continue; 1133 1134 dmi_check_onboard_device(type, name, adap); 1135 } 1136 } 1137 1138 /* Register optional slaves */ 1139 static void i801_probe_optional_slaves(struct i801_priv *priv) 1140 { 1141 /* Only register slaves on main SMBus channel */ 1142 if (priv->features & FEATURE_IDF) 1143 return; 1144 1145 if (apanel_addr) { 1146 struct i2c_board_info info; 1147 1148 memset(&info, 0, sizeof(struct i2c_board_info)); 1149 info.addr = apanel_addr; 1150 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE); 1151 i2c_new_device(&priv->adapter, &info); 1152 } 1153 1154 if (dmi_name_in_vendors("FUJITSU")) 1155 dmi_walk(dmi_check_onboard_devices, &priv->adapter); 1156 } 1157 #else 1158 static void __init input_apanel_init(void) {} 1159 static void i801_probe_optional_slaves(struct i801_priv *priv) {} 1160 #endif /* CONFIG_X86 && CONFIG_DMI */ 1161 1162 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 1163 static struct i801_mux_config i801_mux_config_asus_z8_d12 = { 1164 .gpio_chip = "gpio_ich", 1165 .values = { 0x02, 0x03 }, 1166 .n_values = 2, 1167 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD }, 1168 .gpios = { 52, 53 }, 1169 .n_gpios = 2, 1170 }; 1171 1172 static struct i801_mux_config i801_mux_config_asus_z8_d18 = { 1173 .gpio_chip = "gpio_ich", 1174 .values = { 0x02, 0x03, 0x01 }, 1175 .n_values = 3, 1176 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD }, 1177 .gpios = { 52, 53 }, 1178 .n_gpios = 2, 1179 }; 1180 1181 static const struct dmi_system_id mux_dmi_table[] = { 1182 { 1183 .matches = { 1184 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1185 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"), 1186 }, 1187 .driver_data = &i801_mux_config_asus_z8_d12, 1188 }, 1189 { 1190 .matches = { 1191 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1192 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"), 1193 }, 1194 .driver_data = &i801_mux_config_asus_z8_d12, 1195 }, 1196 { 1197 .matches = { 1198 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1199 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"), 1200 }, 1201 .driver_data = &i801_mux_config_asus_z8_d12, 1202 }, 1203 { 1204 .matches = { 1205 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1206 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"), 1207 }, 1208 .driver_data = &i801_mux_config_asus_z8_d12, 1209 }, 1210 { 1211 .matches = { 1212 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1213 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"), 1214 }, 1215 .driver_data = &i801_mux_config_asus_z8_d12, 1216 }, 1217 { 1218 .matches = { 1219 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1220 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"), 1221 }, 1222 .driver_data = &i801_mux_config_asus_z8_d12, 1223 }, 1224 { 1225 .matches = { 1226 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1227 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"), 1228 }, 1229 .driver_data = &i801_mux_config_asus_z8_d18, 1230 }, 1231 { 1232 .matches = { 1233 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1234 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"), 1235 }, 1236 .driver_data = &i801_mux_config_asus_z8_d18, 1237 }, 1238 { 1239 .matches = { 1240 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1241 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"), 1242 }, 1243 .driver_data = &i801_mux_config_asus_z8_d12, 1244 }, 1245 { } 1246 }; 1247 1248 /* Setup multiplexing if needed */ 1249 static int i801_add_mux(struct i801_priv *priv) 1250 { 1251 struct device *dev = &priv->adapter.dev; 1252 const struct i801_mux_config *mux_config; 1253 struct i2c_mux_gpio_platform_data gpio_data; 1254 int err; 1255 1256 if (!priv->mux_drvdata) 1257 return 0; 1258 mux_config = priv->mux_drvdata; 1259 1260 /* Prepare the platform data */ 1261 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data)); 1262 gpio_data.parent = priv->adapter.nr; 1263 gpio_data.values = mux_config->values; 1264 gpio_data.n_values = mux_config->n_values; 1265 gpio_data.classes = mux_config->classes; 1266 gpio_data.gpio_chip = mux_config->gpio_chip; 1267 gpio_data.gpios = mux_config->gpios; 1268 gpio_data.n_gpios = mux_config->n_gpios; 1269 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE; 1270 1271 /* Register the mux device */ 1272 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio", 1273 PLATFORM_DEVID_AUTO, &gpio_data, 1274 sizeof(struct i2c_mux_gpio_platform_data)); 1275 if (IS_ERR(priv->mux_pdev)) { 1276 err = PTR_ERR(priv->mux_pdev); 1277 priv->mux_pdev = NULL; 1278 dev_err(dev, "Failed to register i2c-mux-gpio device\n"); 1279 return err; 1280 } 1281 1282 return 0; 1283 } 1284 1285 static void i801_del_mux(struct i801_priv *priv) 1286 { 1287 if (priv->mux_pdev) 1288 platform_device_unregister(priv->mux_pdev); 1289 } 1290 1291 static unsigned int i801_get_adapter_class(struct i801_priv *priv) 1292 { 1293 const struct dmi_system_id *id; 1294 const struct i801_mux_config *mux_config; 1295 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 1296 int i; 1297 1298 id = dmi_first_match(mux_dmi_table); 1299 if (id) { 1300 /* Remove branch classes from trunk */ 1301 mux_config = id->driver_data; 1302 for (i = 0; i < mux_config->n_values; i++) 1303 class &= ~mux_config->classes[i]; 1304 1305 /* Remember for later */ 1306 priv->mux_drvdata = mux_config; 1307 } 1308 1309 return class; 1310 } 1311 #else 1312 static inline int i801_add_mux(struct i801_priv *priv) { return 0; } 1313 static inline void i801_del_mux(struct i801_priv *priv) { } 1314 1315 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv) 1316 { 1317 return I2C_CLASS_HWMON | I2C_CLASS_SPD; 1318 } 1319 #endif 1320 1321 static const struct itco_wdt_platform_data tco_platform_data = { 1322 .name = "Intel PCH", 1323 .version = 4, 1324 }; 1325 1326 static DEFINE_SPINLOCK(p2sb_spinlock); 1327 1328 static void i801_add_tco(struct i801_priv *priv) 1329 { 1330 struct pci_dev *pci_dev = priv->pci_dev; 1331 struct resource tco_res[3], *res; 1332 struct platform_device *pdev; 1333 unsigned int devfn; 1334 u32 tco_base, tco_ctl; 1335 u32 base_addr, ctrl_val; 1336 u64 base64_addr; 1337 u8 hidden; 1338 1339 if (!(priv->features & FEATURE_TCO)) 1340 return; 1341 1342 pci_read_config_dword(pci_dev, TCOBASE, &tco_base); 1343 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl); 1344 if (!(tco_ctl & TCOCTL_EN)) 1345 return; 1346 1347 memset(tco_res, 0, sizeof(tco_res)); 1348 1349 res = &tco_res[ICH_RES_IO_TCO]; 1350 res->start = tco_base & ~1; 1351 res->end = res->start + 32 - 1; 1352 res->flags = IORESOURCE_IO; 1353 1354 /* 1355 * Power Management registers. 1356 */ 1357 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 2); 1358 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPIBASE, &base_addr); 1359 1360 res = &tco_res[ICH_RES_IO_SMI]; 1361 res->start = (base_addr & ~1) + ACPIBASE_SMI_OFF; 1362 res->end = res->start + 3; 1363 res->flags = IORESOURCE_IO; 1364 1365 /* 1366 * Enable the ACPI I/O space. 1367 */ 1368 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPICTRL, &ctrl_val); 1369 ctrl_val |= ACPICTRL_EN; 1370 pci_bus_write_config_dword(pci_dev->bus, devfn, ACPICTRL, ctrl_val); 1371 1372 /* 1373 * We must access the NO_REBOOT bit over the Primary to Sideband 1374 * bridge (P2SB). The BIOS prevents the P2SB device from being 1375 * enumerated by the PCI subsystem, so we need to unhide/hide it 1376 * to lookup the P2SB BAR. 1377 */ 1378 spin_lock(&p2sb_spinlock); 1379 1380 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1); 1381 1382 /* Unhide the P2SB device, if it is hidden */ 1383 pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden); 1384 if (hidden) 1385 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0); 1386 1387 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr); 1388 base64_addr = base_addr & 0xfffffff0; 1389 1390 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr); 1391 base64_addr |= (u64)base_addr << 32; 1392 1393 /* Hide the P2SB device, if it was hidden before */ 1394 if (hidden) 1395 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden); 1396 spin_unlock(&p2sb_spinlock); 1397 1398 res = &tco_res[ICH_RES_MEM_OFF]; 1399 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL; 1400 res->end = res->start + 3; 1401 res->flags = IORESOURCE_MEM; 1402 1403 pdev = platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1, 1404 tco_res, 3, &tco_platform_data, 1405 sizeof(tco_platform_data)); 1406 if (IS_ERR(pdev)) { 1407 dev_warn(&pci_dev->dev, "failed to create iTCO device\n"); 1408 return; 1409 } 1410 1411 priv->tco_pdev = pdev; 1412 } 1413 1414 #ifdef CONFIG_ACPI 1415 static acpi_status 1416 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits, 1417 u64 *value, void *handler_context, void *region_context) 1418 { 1419 struct i801_priv *priv = handler_context; 1420 struct pci_dev *pdev = priv->pci_dev; 1421 acpi_status status; 1422 1423 /* 1424 * Once BIOS AML code touches the OpRegion we warn and inhibit any 1425 * further access from the driver itself. This device is now owned 1426 * by the system firmware. 1427 */ 1428 mutex_lock(&priv->acpi_lock); 1429 1430 if (!priv->acpi_reserved) { 1431 priv->acpi_reserved = true; 1432 1433 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n"); 1434 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n"); 1435 1436 /* 1437 * BIOS is accessing the host controller so prevent it from 1438 * suspending automatically from now on. 1439 */ 1440 pm_runtime_get_sync(&pdev->dev); 1441 } 1442 1443 if ((function & ACPI_IO_MASK) == ACPI_READ) 1444 status = acpi_os_read_port(address, (u32 *)value, bits); 1445 else 1446 status = acpi_os_write_port(address, (u32)*value, bits); 1447 1448 mutex_unlock(&priv->acpi_lock); 1449 1450 return status; 1451 } 1452 1453 static int i801_acpi_probe(struct i801_priv *priv) 1454 { 1455 struct acpi_device *adev; 1456 acpi_status status; 1457 1458 adev = ACPI_COMPANION(&priv->pci_dev->dev); 1459 if (adev) { 1460 status = acpi_install_address_space_handler(adev->handle, 1461 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler, 1462 NULL, priv); 1463 if (ACPI_SUCCESS(status)) 1464 return 0; 1465 } 1466 1467 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]); 1468 } 1469 1470 static void i801_acpi_remove(struct i801_priv *priv) 1471 { 1472 struct acpi_device *adev; 1473 1474 adev = ACPI_COMPANION(&priv->pci_dev->dev); 1475 if (!adev) 1476 return; 1477 1478 acpi_remove_address_space_handler(adev->handle, 1479 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler); 1480 1481 mutex_lock(&priv->acpi_lock); 1482 if (priv->acpi_reserved) 1483 pm_runtime_put(&priv->pci_dev->dev); 1484 mutex_unlock(&priv->acpi_lock); 1485 } 1486 #else 1487 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; } 1488 static inline void i801_acpi_remove(struct i801_priv *priv) { } 1489 #endif 1490 1491 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id) 1492 { 1493 unsigned char temp; 1494 int err, i; 1495 struct i801_priv *priv; 1496 1497 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL); 1498 if (!priv) 1499 return -ENOMEM; 1500 1501 i2c_set_adapdata(&priv->adapter, priv); 1502 priv->adapter.owner = THIS_MODULE; 1503 priv->adapter.class = i801_get_adapter_class(priv); 1504 priv->adapter.algo = &smbus_algorithm; 1505 priv->adapter.dev.parent = &dev->dev; 1506 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev)); 1507 priv->adapter.retries = 3; 1508 mutex_init(&priv->acpi_lock); 1509 1510 priv->pci_dev = dev; 1511 switch (dev->device) { 1512 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS: 1513 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS: 1514 case PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS: 1515 case PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS: 1516 case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS: 1517 case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS: 1518 case PCI_DEVICE_ID_INTEL_CDF_SMBUS: 1519 case PCI_DEVICE_ID_INTEL_DNV_SMBUS: 1520 case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS: 1521 priv->features |= FEATURE_I2C_BLOCK_READ; 1522 priv->features |= FEATURE_IRQ; 1523 priv->features |= FEATURE_SMBUS_PEC; 1524 priv->features |= FEATURE_BLOCK_BUFFER; 1525 /* If we have ACPI based watchdog use that instead */ 1526 if (!acpi_has_watchdog()) 1527 priv->features |= FEATURE_TCO; 1528 priv->features |= FEATURE_HOST_NOTIFY; 1529 break; 1530 1531 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0: 1532 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1: 1533 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2: 1534 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0: 1535 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1: 1536 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2: 1537 priv->features |= FEATURE_IDF; 1538 /* fall through */ 1539 default: 1540 priv->features |= FEATURE_I2C_BLOCK_READ; 1541 priv->features |= FEATURE_IRQ; 1542 /* fall through */ 1543 case PCI_DEVICE_ID_INTEL_82801DB_3: 1544 priv->features |= FEATURE_SMBUS_PEC; 1545 priv->features |= FEATURE_BLOCK_BUFFER; 1546 /* fall through */ 1547 case PCI_DEVICE_ID_INTEL_82801CA_3: 1548 priv->features |= FEATURE_HOST_NOTIFY; 1549 /* fall through */ 1550 case PCI_DEVICE_ID_INTEL_82801BA_2: 1551 case PCI_DEVICE_ID_INTEL_82801AB_3: 1552 case PCI_DEVICE_ID_INTEL_82801AA_3: 1553 break; 1554 } 1555 1556 /* Disable features on user request */ 1557 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) { 1558 if (priv->features & disable_features & (1 << i)) 1559 dev_notice(&dev->dev, "%s disabled by user\n", 1560 i801_feature_names[i]); 1561 } 1562 priv->features &= ~disable_features; 1563 1564 err = pcim_enable_device(dev); 1565 if (err) { 1566 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", 1567 err); 1568 return err; 1569 } 1570 pcim_pin_device(dev); 1571 1572 /* Determine the address of the SMBus area */ 1573 priv->smba = pci_resource_start(dev, SMBBAR); 1574 if (!priv->smba) { 1575 dev_err(&dev->dev, 1576 "SMBus base address uninitialized, upgrade BIOS\n"); 1577 return -ENODEV; 1578 } 1579 1580 if (i801_acpi_probe(priv)) 1581 return -ENODEV; 1582 1583 err = pcim_iomap_regions(dev, 1 << SMBBAR, 1584 dev_driver_string(&dev->dev)); 1585 if (err) { 1586 dev_err(&dev->dev, 1587 "Failed to request SMBus region 0x%lx-0x%Lx\n", 1588 priv->smba, 1589 (unsigned long long)pci_resource_end(dev, SMBBAR)); 1590 i801_acpi_remove(priv); 1591 return err; 1592 } 1593 1594 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp); 1595 priv->original_hstcfg = temp; 1596 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ 1597 if (!(temp & SMBHSTCFG_HST_EN)) { 1598 dev_info(&dev->dev, "Enabling SMBus device\n"); 1599 temp |= SMBHSTCFG_HST_EN; 1600 } 1601 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp); 1602 1603 if (temp & SMBHSTCFG_SMB_SMI_EN) { 1604 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); 1605 /* Disable SMBus interrupt feature if SMBus using SMI# */ 1606 priv->features &= ~FEATURE_IRQ; 1607 } 1608 if (temp & SMBHSTCFG_SPD_WD) 1609 dev_info(&dev->dev, "SPD Write Disable is set\n"); 1610 1611 /* Clear special mode bits */ 1612 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) 1613 outb_p(inb_p(SMBAUXCTL(priv)) & 1614 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 1615 1616 /* Remember original Host Notify setting */ 1617 if (priv->features & FEATURE_HOST_NOTIFY) 1618 priv->original_slvcmd = inb_p(SMBSLVCMD(priv)); 1619 1620 /* Default timeout in interrupt mode: 200 ms */ 1621 priv->adapter.timeout = HZ / 5; 1622 1623 if (dev->irq == IRQ_NOTCONNECTED) 1624 priv->features &= ~FEATURE_IRQ; 1625 1626 if (priv->features & FEATURE_IRQ) { 1627 u16 pcictl, pcists; 1628 1629 /* Complain if an interrupt is already pending */ 1630 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); 1631 if (pcists & SMBPCISTS_INTS) 1632 dev_warn(&dev->dev, "An interrupt is pending!\n"); 1633 1634 /* Check if interrupts have been disabled */ 1635 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl); 1636 if (pcictl & SMBPCICTL_INTDIS) { 1637 dev_info(&dev->dev, "Interrupts are disabled\n"); 1638 priv->features &= ~FEATURE_IRQ; 1639 } 1640 } 1641 1642 if (priv->features & FEATURE_IRQ) { 1643 init_waitqueue_head(&priv->waitq); 1644 1645 err = devm_request_irq(&dev->dev, dev->irq, i801_isr, 1646 IRQF_SHARED, 1647 dev_driver_string(&dev->dev), priv); 1648 if (err) { 1649 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n", 1650 dev->irq, err); 1651 priv->features &= ~FEATURE_IRQ; 1652 } 1653 } 1654 dev_info(&dev->dev, "SMBus using %s\n", 1655 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling"); 1656 1657 i801_add_tco(priv); 1658 1659 snprintf(priv->adapter.name, sizeof(priv->adapter.name), 1660 "SMBus I801 adapter at %04lx", priv->smba); 1661 err = i2c_add_adapter(&priv->adapter); 1662 if (err) { 1663 i801_acpi_remove(priv); 1664 return err; 1665 } 1666 1667 i801_enable_host_notify(&priv->adapter); 1668 1669 i801_probe_optional_slaves(priv); 1670 /* We ignore errors - multiplexing is optional */ 1671 i801_add_mux(priv); 1672 1673 pci_set_drvdata(dev, priv); 1674 1675 pm_runtime_set_autosuspend_delay(&dev->dev, 1000); 1676 pm_runtime_use_autosuspend(&dev->dev); 1677 pm_runtime_put_autosuspend(&dev->dev); 1678 pm_runtime_allow(&dev->dev); 1679 1680 return 0; 1681 } 1682 1683 static void i801_remove(struct pci_dev *dev) 1684 { 1685 struct i801_priv *priv = pci_get_drvdata(dev); 1686 1687 pm_runtime_forbid(&dev->dev); 1688 pm_runtime_get_noresume(&dev->dev); 1689 1690 i801_disable_host_notify(priv); 1691 i801_del_mux(priv); 1692 i2c_del_adapter(&priv->adapter); 1693 i801_acpi_remove(priv); 1694 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); 1695 1696 platform_device_unregister(priv->tco_pdev); 1697 1698 /* 1699 * do not call pci_disable_device(dev) since it can cause hard hangs on 1700 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) 1701 */ 1702 } 1703 1704 static void i801_shutdown(struct pci_dev *dev) 1705 { 1706 struct i801_priv *priv = pci_get_drvdata(dev); 1707 1708 /* Restore config registers to avoid hard hang on some systems */ 1709 i801_disable_host_notify(priv); 1710 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); 1711 } 1712 1713 #ifdef CONFIG_PM_SLEEP 1714 static int i801_suspend(struct device *dev) 1715 { 1716 struct pci_dev *pci_dev = to_pci_dev(dev); 1717 struct i801_priv *priv = pci_get_drvdata(pci_dev); 1718 1719 pci_write_config_byte(pci_dev, SMBHSTCFG, priv->original_hstcfg); 1720 return 0; 1721 } 1722 1723 static int i801_resume(struct device *dev) 1724 { 1725 struct pci_dev *pci_dev = to_pci_dev(dev); 1726 struct i801_priv *priv = pci_get_drvdata(pci_dev); 1727 1728 i801_enable_host_notify(&priv->adapter); 1729 1730 return 0; 1731 } 1732 #endif 1733 1734 static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume); 1735 1736 static struct pci_driver i801_driver = { 1737 .name = "i801_smbus", 1738 .id_table = i801_ids, 1739 .probe = i801_probe, 1740 .remove = i801_remove, 1741 .shutdown = i801_shutdown, 1742 .driver = { 1743 .pm = &i801_pm_ops, 1744 }, 1745 }; 1746 1747 static int __init i2c_i801_init(void) 1748 { 1749 if (dmi_name_in_vendors("FUJITSU")) 1750 input_apanel_init(); 1751 return pci_register_driver(&i801_driver); 1752 } 1753 1754 static void __exit i2c_i801_exit(void) 1755 { 1756 pci_unregister_driver(&i801_driver); 1757 } 1758 1759 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>"); 1760 MODULE_DESCRIPTION("I801 SMBus driver"); 1761 MODULE_LICENSE("GPL"); 1762 1763 module_init(i2c_i801_init); 1764 module_exit(i2c_i801_exit); 1765