1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, 4 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker 5 <mdsxyz123@yahoo.com> 6 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de> 7 Copyright (C) 2010 Intel Corporation, 8 David Woodhouse <dwmw2@infradead.org> 9 10 */ 11 12 /* 13 * Supports the following Intel I/O Controller Hubs (ICH): 14 * 15 * I/O Block I2C 16 * region SMBus Block proc. block 17 * Chip name PCI ID size PEC buffer call read 18 * --------------------------------------------------------------------------- 19 * 82801AA (ICH) 0x2413 16 no no no no 20 * 82801AB (ICH0) 0x2423 16 no no no no 21 * 82801BA (ICH2) 0x2443 16 no no no no 22 * 82801CA (ICH3) 0x2483 32 soft no no no 23 * 82801DB (ICH4) 0x24c3 32 hard yes no no 24 * 82801E (ICH5) 0x24d3 32 hard yes yes yes 25 * 6300ESB 0x25a4 32 hard yes yes yes 26 * 82801F (ICH6) 0x266a 32 hard yes yes yes 27 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes 28 * 82801G (ICH7) 0x27da 32 hard yes yes yes 29 * 82801H (ICH8) 0x283e 32 hard yes yes yes 30 * 82801I (ICH9) 0x2930 32 hard yes yes yes 31 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes 32 * ICH10 0x3a30 32 hard yes yes yes 33 * ICH10 0x3a60 32 hard yes yes yes 34 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes 35 * 6 Series (PCH) 0x1c22 32 hard yes yes yes 36 * Patsburg (PCH) 0x1d22 32 hard yes yes yes 37 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes 38 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes 39 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes 40 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes 41 * Panther Point (PCH) 0x1e22 32 hard yes yes yes 42 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes 43 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes 44 * Avoton (SOC) 0x1f3c 32 hard yes yes yes 45 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes 46 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes 47 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes 48 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes 49 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes 50 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes 51 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes 52 * BayTrail (SOC) 0x0f12 32 hard yes yes yes 53 * Braswell (SOC) 0x2292 32 hard yes yes yes 54 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes 55 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes 56 * DNV (SOC) 0x19df 32 hard yes yes yes 57 * Emmitsburg (PCH) 0x1bc9 32 hard yes yes yes 58 * Broxton (SOC) 0x5ad4 32 hard yes yes yes 59 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes 60 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes 61 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes 62 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes 63 * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes 64 * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes 65 * Cedar Fork (PCH) 0x18df 32 hard yes yes yes 66 * Ice Lake-LP (PCH) 0x34a3 32 hard yes yes yes 67 * Ice Lake-N (PCH) 0x38a3 32 hard yes yes yes 68 * Comet Lake (PCH) 0x02a3 32 hard yes yes yes 69 * Comet Lake-H (PCH) 0x06a3 32 hard yes yes yes 70 * Elkhart Lake (PCH) 0x4b23 32 hard yes yes yes 71 * Tiger Lake-LP (PCH) 0xa0a3 32 hard yes yes yes 72 * Tiger Lake-H (PCH) 0x43a3 32 hard yes yes yes 73 * Jasper Lake (SOC) 0x4da3 32 hard yes yes yes 74 * Comet Lake-V (PCH) 0xa3a3 32 hard yes yes yes 75 * Alder Lake-S (PCH) 0x7aa3 32 hard yes yes yes 76 * Alder Lake-P (PCH) 0x51a3 32 hard yes yes yes 77 * Alder Lake-M (PCH) 0x54a3 32 hard yes yes yes 78 * Raptor Lake-S (PCH) 0x7a23 32 hard yes yes yes 79 * 80 * Features supported by this driver: 81 * Software PEC no 82 * Hardware PEC yes 83 * Block buffer yes 84 * Block process call transaction yes 85 * I2C block read transaction yes (doesn't use the block buffer) 86 * Slave mode no 87 * SMBus Host Notify yes 88 * Interrupt processing yes 89 * 90 * See the file Documentation/i2c/busses/i2c-i801.rst for details. 91 */ 92 93 #define DRV_NAME "i801_smbus" 94 95 #include <linux/interrupt.h> 96 #include <linux/module.h> 97 #include <linux/pci.h> 98 #include <linux/kernel.h> 99 #include <linux/stddef.h> 100 #include <linux/delay.h> 101 #include <linux/ioport.h> 102 #include <linux/init.h> 103 #include <linux/i2c.h> 104 #include <linux/i2c-smbus.h> 105 #include <linux/acpi.h> 106 #include <linux/io.h> 107 #include <linux/dmi.h> 108 #include <linux/slab.h> 109 #include <linux/string.h> 110 #include <linux/completion.h> 111 #include <linux/err.h> 112 #include <linux/platform_device.h> 113 #include <linux/platform_data/itco_wdt.h> 114 #include <linux/pm_runtime.h> 115 #include <linux/mutex.h> 116 117 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 118 #include <linux/gpio/machine.h> 119 #include <linux/platform_data/i2c-mux-gpio.h> 120 #endif 121 122 /* I801 SMBus address offsets */ 123 #define SMBHSTSTS(p) (0 + (p)->smba) 124 #define SMBHSTCNT(p) (2 + (p)->smba) 125 #define SMBHSTCMD(p) (3 + (p)->smba) 126 #define SMBHSTADD(p) (4 + (p)->smba) 127 #define SMBHSTDAT0(p) (5 + (p)->smba) 128 #define SMBHSTDAT1(p) (6 + (p)->smba) 129 #define SMBBLKDAT(p) (7 + (p)->smba) 130 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */ 131 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */ 132 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */ 133 #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */ 134 #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */ 135 #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */ 136 137 /* PCI Address Constants */ 138 #define SMBBAR 4 139 #define SMBHSTCFG 0x040 140 #define TCOBASE 0x050 141 #define TCOCTL 0x054 142 143 #define SBREG_BAR 0x10 144 #define SBREG_SMBCTRL 0xc6000c 145 #define SBREG_SMBCTRL_DNV 0xcf000c 146 147 /* Host configuration bits for SMBHSTCFG */ 148 #define SMBHSTCFG_HST_EN BIT(0) 149 #define SMBHSTCFG_SMB_SMI_EN BIT(1) 150 #define SMBHSTCFG_I2C_EN BIT(2) 151 #define SMBHSTCFG_SPD_WD BIT(4) 152 153 /* TCO configuration bits for TCOCTL */ 154 #define TCOCTL_EN BIT(8) 155 156 /* Auxiliary status register bits, ICH4+ only */ 157 #define SMBAUXSTS_CRCE BIT(0) 158 #define SMBAUXSTS_STCO BIT(1) 159 160 /* Auxiliary control register bits, ICH4+ only */ 161 #define SMBAUXCTL_CRC BIT(0) 162 #define SMBAUXCTL_E32B BIT(1) 163 164 /* I801 command constants */ 165 #define I801_QUICK 0x00 166 #define I801_BYTE 0x04 167 #define I801_BYTE_DATA 0x08 168 #define I801_WORD_DATA 0x0C 169 #define I801_PROC_CALL 0x10 170 #define I801_BLOCK_DATA 0x14 171 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ 172 #define I801_BLOCK_PROC_CALL 0x1C 173 174 /* I801 Host Control register bits */ 175 #define SMBHSTCNT_INTREN BIT(0) 176 #define SMBHSTCNT_KILL BIT(1) 177 #define SMBHSTCNT_LAST_BYTE BIT(5) 178 #define SMBHSTCNT_START BIT(6) 179 #define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */ 180 181 /* I801 Hosts Status register bits */ 182 #define SMBHSTSTS_BYTE_DONE BIT(7) 183 #define SMBHSTSTS_INUSE_STS BIT(6) 184 #define SMBHSTSTS_SMBALERT_STS BIT(5) 185 #define SMBHSTSTS_FAILED BIT(4) 186 #define SMBHSTSTS_BUS_ERR BIT(3) 187 #define SMBHSTSTS_DEV_ERR BIT(2) 188 #define SMBHSTSTS_INTR BIT(1) 189 #define SMBHSTSTS_HOST_BUSY BIT(0) 190 191 /* Host Notify Status register bits */ 192 #define SMBSLVSTS_HST_NTFY_STS BIT(0) 193 194 /* Host Notify Command register bits */ 195 #define SMBSLVCMD_SMBALERT_DISABLE BIT(2) 196 #define SMBSLVCMD_HST_NTFY_INTREN BIT(0) 197 198 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \ 199 SMBHSTSTS_DEV_ERR) 200 201 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \ 202 STATUS_ERROR_FLAGS) 203 204 /* Older devices have their ID defined in <linux/pci_ids.h> */ 205 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS 0x02a3 206 #define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS 0x06a3 207 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12 208 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df 209 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df 210 #define PCI_DEVICE_ID_INTEL_EBG_SMBUS 0x1bc9 211 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 212 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 213 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */ 214 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70 215 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71 216 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72 217 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 218 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c 219 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292 220 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 221 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0 222 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4 223 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS 0x34a3 224 #define PCI_DEVICE_ID_INTEL_ICELAKE_N_SMBUS 0x38a3 225 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 226 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS 0x43a3 227 #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS 0x4b23 228 #define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS 0x4da3 229 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS 0x51a3 230 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS 0x54a3 231 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4 232 #define PCI_DEVICE_ID_INTEL_RAPTOR_LAKE_S_SMBUS 0x7a23 233 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS 0x7aa3 234 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 235 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2 236 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22 237 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d 238 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e 239 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f 240 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22 241 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2 242 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23 243 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3 244 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS 0xa0a3 245 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123 246 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3 247 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223 248 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3 249 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323 250 #define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS 0xa3a3 251 252 struct i801_mux_config { 253 char *gpio_chip; 254 unsigned values[3]; 255 int n_values; 256 unsigned classes[3]; 257 unsigned gpios[2]; /* Relative to gpio_chip->base */ 258 int n_gpios; 259 }; 260 261 struct i801_priv { 262 struct i2c_adapter adapter; 263 unsigned long smba; 264 unsigned char original_hstcfg; 265 unsigned char original_hstcnt; 266 unsigned char original_slvcmd; 267 struct pci_dev *pci_dev; 268 unsigned int features; 269 270 /* isr processing */ 271 struct completion done; 272 u8 status; 273 274 /* Command state used by isr for byte-by-byte block transactions */ 275 u8 cmd; 276 bool is_read; 277 int count; 278 int len; 279 u8 *data; 280 281 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 282 const struct i801_mux_config *mux_drvdata; 283 struct platform_device *mux_pdev; 284 struct gpiod_lookup_table *lookup; 285 #endif 286 struct platform_device *tco_pdev; 287 288 /* 289 * If set to true the host controller registers are reserved for 290 * ACPI AML use. Protected by acpi_lock. 291 */ 292 bool acpi_reserved; 293 struct mutex acpi_lock; 294 }; 295 296 #define FEATURE_SMBUS_PEC BIT(0) 297 #define FEATURE_BLOCK_BUFFER BIT(1) 298 #define FEATURE_BLOCK_PROC BIT(2) 299 #define FEATURE_I2C_BLOCK_READ BIT(3) 300 #define FEATURE_IRQ BIT(4) 301 #define FEATURE_HOST_NOTIFY BIT(5) 302 /* Not really a feature, but it's convenient to handle it as such */ 303 #define FEATURE_IDF BIT(15) 304 #define FEATURE_TCO_SPT BIT(16) 305 #define FEATURE_TCO_CNL BIT(17) 306 307 static const char *i801_feature_names[] = { 308 "SMBus PEC", 309 "Block buffer", 310 "Block process call", 311 "I2C block read", 312 "Interrupt", 313 "SMBus Host Notify", 314 }; 315 316 static unsigned int disable_features; 317 module_param(disable_features, uint, S_IRUGO | S_IWUSR); 318 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n" 319 "\t\t 0x01 disable SMBus PEC\n" 320 "\t\t 0x02 disable the block buffer\n" 321 "\t\t 0x08 disable the I2C block read functionality\n" 322 "\t\t 0x10 don't use interrupts\n" 323 "\t\t 0x20 disable SMBus Host Notify "); 324 325 /* Make sure the SMBus host is ready to start transmitting. 326 Return 0 if it is, -EBUSY if it is not. */ 327 static int i801_check_pre(struct i801_priv *priv) 328 { 329 int status; 330 331 status = inb_p(SMBHSTSTS(priv)); 332 if (status & SMBHSTSTS_HOST_BUSY) { 333 pci_err(priv->pci_dev, "SMBus is busy, can't use it!\n"); 334 return -EBUSY; 335 } 336 337 status &= STATUS_FLAGS; 338 if (status) { 339 pci_dbg(priv->pci_dev, "Clearing status flags (%02x)\n", status); 340 outb_p(status, SMBHSTSTS(priv)); 341 } 342 343 /* 344 * Clear CRC status if needed. 345 * During normal operation, i801_check_post() takes care 346 * of it after every operation. We do it here only in case 347 * the hardware was already in this state when the driver 348 * started. 349 */ 350 if (priv->features & FEATURE_SMBUS_PEC) { 351 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE; 352 if (status) { 353 pci_dbg(priv->pci_dev, "Clearing aux status flags (%02x)\n", status); 354 outb_p(status, SMBAUXSTS(priv)); 355 } 356 } 357 358 return 0; 359 } 360 361 static int i801_check_post(struct i801_priv *priv, int status) 362 { 363 int result = 0; 364 365 /* 366 * If the SMBus is still busy, we give up 367 */ 368 if (unlikely(status < 0)) { 369 dev_err(&priv->pci_dev->dev, "Transaction timeout\n"); 370 /* try to stop the current command */ 371 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n"); 372 outb_p(SMBHSTCNT_KILL, SMBHSTCNT(priv)); 373 usleep_range(1000, 2000); 374 outb_p(0, SMBHSTCNT(priv)); 375 376 /* Check if it worked */ 377 status = inb_p(SMBHSTSTS(priv)); 378 if ((status & SMBHSTSTS_HOST_BUSY) || 379 !(status & SMBHSTSTS_FAILED)) 380 dev_err(&priv->pci_dev->dev, 381 "Failed terminating the transaction\n"); 382 return -ETIMEDOUT; 383 } 384 385 if (status & SMBHSTSTS_FAILED) { 386 result = -EIO; 387 dev_err(&priv->pci_dev->dev, "Transaction failed\n"); 388 } 389 if (status & SMBHSTSTS_DEV_ERR) { 390 /* 391 * This may be a PEC error, check and clear it. 392 * 393 * AUXSTS is handled differently from HSTSTS. 394 * For HSTSTS, i801_isr() or i801_wait_intr() 395 * has already cleared the error bits in hardware, 396 * and we are passed a copy of the original value 397 * in "status". 398 * For AUXSTS, the hardware register is left 399 * for us to handle here. 400 * This is asymmetric, slightly iffy, but safe, 401 * since all this code is serialized and the CRCE 402 * bit is harmless as long as it's cleared before 403 * the next operation. 404 */ 405 if ((priv->features & FEATURE_SMBUS_PEC) && 406 (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) { 407 outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv)); 408 result = -EBADMSG; 409 dev_dbg(&priv->pci_dev->dev, "PEC error\n"); 410 } else { 411 result = -ENXIO; 412 dev_dbg(&priv->pci_dev->dev, "No response\n"); 413 } 414 } 415 if (status & SMBHSTSTS_BUS_ERR) { 416 result = -EAGAIN; 417 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n"); 418 } 419 420 return result; 421 } 422 423 /* Wait for BUSY being cleared and either INTR or an error flag being set */ 424 static int i801_wait_intr(struct i801_priv *priv) 425 { 426 unsigned long timeout = jiffies + priv->adapter.timeout; 427 int status, busy; 428 429 do { 430 usleep_range(250, 500); 431 status = inb_p(SMBHSTSTS(priv)); 432 busy = status & SMBHSTSTS_HOST_BUSY; 433 status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR; 434 if (!busy && status) 435 return status; 436 } while (time_is_after_eq_jiffies(timeout)); 437 438 return -ETIMEDOUT; 439 } 440 441 /* Wait for either BYTE_DONE or an error flag being set */ 442 static int i801_wait_byte_done(struct i801_priv *priv) 443 { 444 unsigned long timeout = jiffies + priv->adapter.timeout; 445 int status; 446 447 do { 448 usleep_range(250, 500); 449 status = inb_p(SMBHSTSTS(priv)); 450 if (status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) 451 return status & STATUS_ERROR_FLAGS; 452 } while (time_is_after_eq_jiffies(timeout)); 453 454 return -ETIMEDOUT; 455 } 456 457 static int i801_transaction(struct i801_priv *priv, int xact) 458 { 459 int status; 460 unsigned long result; 461 const struct i2c_adapter *adap = &priv->adapter; 462 463 status = i801_check_pre(priv); 464 if (status < 0) 465 return status; 466 467 if (priv->features & FEATURE_IRQ) { 468 reinit_completion(&priv->done); 469 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START, 470 SMBHSTCNT(priv)); 471 result = wait_for_completion_timeout(&priv->done, adap->timeout); 472 return i801_check_post(priv, result ? priv->status : -ETIMEDOUT); 473 } 474 475 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv)); 476 477 status = i801_wait_intr(priv); 478 return i801_check_post(priv, status); 479 } 480 481 static int i801_block_transaction_by_block(struct i801_priv *priv, 482 union i2c_smbus_data *data, 483 char read_write, int command) 484 { 485 int i, len, status, xact; 486 487 switch (command) { 488 case I2C_SMBUS_BLOCK_PROC_CALL: 489 xact = I801_BLOCK_PROC_CALL; 490 break; 491 case I2C_SMBUS_BLOCK_DATA: 492 xact = I801_BLOCK_DATA; 493 break; 494 default: 495 return -EOPNOTSUPP; 496 } 497 498 /* Set block buffer mode */ 499 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv)); 500 501 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ 502 503 if (read_write == I2C_SMBUS_WRITE) { 504 len = data->block[0]; 505 outb_p(len, SMBHSTDAT0(priv)); 506 for (i = 0; i < len; i++) 507 outb_p(data->block[i+1], SMBBLKDAT(priv)); 508 } 509 510 status = i801_transaction(priv, xact); 511 if (status) 512 return status; 513 514 if (read_write == I2C_SMBUS_READ || 515 command == I2C_SMBUS_BLOCK_PROC_CALL) { 516 len = inb_p(SMBHSTDAT0(priv)); 517 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) 518 return -EPROTO; 519 520 data->block[0] = len; 521 for (i = 0; i < len; i++) 522 data->block[i + 1] = inb_p(SMBBLKDAT(priv)); 523 } 524 return 0; 525 } 526 527 static void i801_isr_byte_done(struct i801_priv *priv) 528 { 529 if (priv->is_read) { 530 /* For SMBus block reads, length is received with first byte */ 531 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) && 532 (priv->count == 0)) { 533 priv->len = inb_p(SMBHSTDAT0(priv)); 534 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) { 535 dev_err(&priv->pci_dev->dev, 536 "Illegal SMBus block read size %d\n", 537 priv->len); 538 /* FIXME: Recover */ 539 priv->len = I2C_SMBUS_BLOCK_MAX; 540 } 541 priv->data[-1] = priv->len; 542 } 543 544 /* Read next byte */ 545 if (priv->count < priv->len) 546 priv->data[priv->count++] = inb(SMBBLKDAT(priv)); 547 else 548 dev_dbg(&priv->pci_dev->dev, 549 "Discarding extra byte on block read\n"); 550 551 /* Set LAST_BYTE for last byte of read transaction */ 552 if (priv->count == priv->len - 1) 553 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE, 554 SMBHSTCNT(priv)); 555 } else if (priv->count < priv->len - 1) { 556 /* Write next byte, except for IRQ after last byte */ 557 outb_p(priv->data[++priv->count], SMBBLKDAT(priv)); 558 } 559 560 /* Clear BYTE_DONE to continue with next byte */ 561 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 562 } 563 564 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv) 565 { 566 unsigned short addr; 567 568 addr = inb_p(SMBNTFDADD(priv)) >> 1; 569 570 /* 571 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba) 572 * always returns 0. Our current implementation doesn't provide 573 * data, so we just ignore it. 574 */ 575 i2c_handle_smbus_host_notify(&priv->adapter, addr); 576 577 /* clear Host Notify bit and return */ 578 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 579 return IRQ_HANDLED; 580 } 581 582 /* 583 * There are three kinds of interrupts: 584 * 585 * 1) i801 signals transaction completion with one of these interrupts: 586 * INTR - Success 587 * DEV_ERR - Invalid command, NAK or communication timeout 588 * BUS_ERR - SMI# transaction collision 589 * FAILED - transaction was canceled due to a KILL request 590 * When any of these occur, update ->status and signal completion. 591 * ->status must be cleared before kicking off the next transaction. 592 * 593 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt 594 * occurs for each byte of a byte-by-byte to prepare the next byte. 595 * 596 * 3) Host Notify interrupts 597 */ 598 static irqreturn_t i801_isr(int irq, void *dev_id) 599 { 600 struct i801_priv *priv = dev_id; 601 u16 pcists; 602 u8 status; 603 604 /* Confirm this is our interrupt */ 605 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists); 606 if (!(pcists & PCI_STATUS_INTERRUPT)) 607 return IRQ_NONE; 608 609 if (priv->features & FEATURE_HOST_NOTIFY) { 610 status = inb_p(SMBSLVSTS(priv)); 611 if (status & SMBSLVSTS_HST_NTFY_STS) 612 return i801_host_notify_isr(priv); 613 } 614 615 status = inb_p(SMBHSTSTS(priv)); 616 if (status & SMBHSTSTS_BYTE_DONE) 617 i801_isr_byte_done(priv); 618 619 /* 620 * Clear remaining IRQ sources: Completion of last command, errors 621 * and the SMB_ALERT signal. SMB_ALERT status is set after signal 622 * assertion independently of the interrupt generation being blocked 623 * or not so clear it always when the status is set. 624 */ 625 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS | SMBHSTSTS_SMBALERT_STS; 626 if (status) 627 outb_p(status, SMBHSTSTS(priv)); 628 status &= ~SMBHSTSTS_SMBALERT_STS; /* SMB_ALERT not reported */ 629 /* 630 * Report transaction result. 631 * ->status must be cleared before the next transaction is started. 632 */ 633 if (status) { 634 priv->status = status; 635 complete(&priv->done); 636 } 637 638 return IRQ_HANDLED; 639 } 640 641 /* 642 * For "byte-by-byte" block transactions: 643 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1 644 * I2C read uses cmd=I801_I2C_BLOCK_DATA 645 */ 646 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, 647 union i2c_smbus_data *data, 648 char read_write, int command) 649 { 650 int i, len; 651 int smbcmd; 652 int status; 653 unsigned long result; 654 const struct i2c_adapter *adap = &priv->adapter; 655 656 if (command == I2C_SMBUS_BLOCK_PROC_CALL) 657 return -EOPNOTSUPP; 658 659 status = i801_check_pre(priv); 660 if (status < 0) 661 return status; 662 663 len = data->block[0]; 664 665 if (read_write == I2C_SMBUS_WRITE) { 666 outb_p(len, SMBHSTDAT0(priv)); 667 outb_p(data->block[1], SMBBLKDAT(priv)); 668 } 669 670 if (command == I2C_SMBUS_I2C_BLOCK_DATA && 671 read_write == I2C_SMBUS_READ) 672 smbcmd = I801_I2C_BLOCK_DATA; 673 else 674 smbcmd = I801_BLOCK_DATA; 675 676 if (priv->features & FEATURE_IRQ) { 677 priv->is_read = (read_write == I2C_SMBUS_READ); 678 if (len == 1 && priv->is_read) 679 smbcmd |= SMBHSTCNT_LAST_BYTE; 680 priv->cmd = smbcmd | SMBHSTCNT_INTREN; 681 priv->len = len; 682 priv->count = 0; 683 priv->data = &data->block[1]; 684 685 reinit_completion(&priv->done); 686 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv)); 687 result = wait_for_completion_timeout(&priv->done, adap->timeout); 688 return i801_check_post(priv, result ? priv->status : -ETIMEDOUT); 689 } 690 691 for (i = 1; i <= len; i++) { 692 if (i == len && read_write == I2C_SMBUS_READ) 693 smbcmd |= SMBHSTCNT_LAST_BYTE; 694 outb_p(smbcmd, SMBHSTCNT(priv)); 695 696 if (i == 1) 697 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START, 698 SMBHSTCNT(priv)); 699 700 status = i801_wait_byte_done(priv); 701 if (status) 702 goto exit; 703 704 if (i == 1 && read_write == I2C_SMBUS_READ 705 && command != I2C_SMBUS_I2C_BLOCK_DATA) { 706 len = inb_p(SMBHSTDAT0(priv)); 707 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { 708 dev_err(&priv->pci_dev->dev, 709 "Illegal SMBus block read size %d\n", 710 len); 711 /* Recover */ 712 while (inb_p(SMBHSTSTS(priv)) & 713 SMBHSTSTS_HOST_BUSY) 714 outb_p(SMBHSTSTS_BYTE_DONE, 715 SMBHSTSTS(priv)); 716 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); 717 return -EPROTO; 718 } 719 data->block[0] = len; 720 } 721 722 /* Retrieve/store value in SMBBLKDAT */ 723 if (read_write == I2C_SMBUS_READ) 724 data->block[i] = inb_p(SMBBLKDAT(priv)); 725 if (read_write == I2C_SMBUS_WRITE && i+1 <= len) 726 outb_p(data->block[i+1], SMBBLKDAT(priv)); 727 728 /* signals SMBBLKDAT ready */ 729 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 730 } 731 732 status = i801_wait_intr(priv); 733 exit: 734 return i801_check_post(priv, status); 735 } 736 737 /* Block transaction function */ 738 static int i801_block_transaction(struct i801_priv *priv, union i2c_smbus_data *data, 739 char read_write, int command) 740 { 741 int result = 0; 742 unsigned char hostc; 743 744 if (read_write == I2C_SMBUS_READ && command == I2C_SMBUS_BLOCK_DATA) 745 data->block[0] = I2C_SMBUS_BLOCK_MAX; 746 else if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX) 747 return -EPROTO; 748 749 if (command == I2C_SMBUS_I2C_BLOCK_DATA) { 750 if (read_write == I2C_SMBUS_WRITE) { 751 /* set I2C_EN bit in configuration register */ 752 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc); 753 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, 754 hostc | SMBHSTCFG_I2C_EN); 755 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) { 756 dev_err(&priv->pci_dev->dev, 757 "I2C block read is unsupported!\n"); 758 return -EOPNOTSUPP; 759 } 760 } 761 762 /* Experience has shown that the block buffer can only be used for 763 SMBus (not I2C) block transactions, even though the datasheet 764 doesn't mention this limitation. */ 765 if ((priv->features & FEATURE_BLOCK_BUFFER) && 766 command != I2C_SMBUS_I2C_BLOCK_DATA) 767 result = i801_block_transaction_by_block(priv, data, 768 read_write, 769 command); 770 else 771 result = i801_block_transaction_byte_by_byte(priv, data, 772 read_write, 773 command); 774 775 if (command == I2C_SMBUS_I2C_BLOCK_DATA 776 && read_write == I2C_SMBUS_WRITE) { 777 /* restore saved configuration register value */ 778 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc); 779 } 780 return result; 781 } 782 783 /* Return negative errno on error. */ 784 static s32 i801_access(struct i2c_adapter *adap, u16 addr, 785 unsigned short flags, char read_write, u8 command, 786 int size, union i2c_smbus_data *data) 787 { 788 int hwpec; 789 int block = 0; 790 int ret, xact; 791 struct i801_priv *priv = i2c_get_adapdata(adap); 792 793 mutex_lock(&priv->acpi_lock); 794 if (priv->acpi_reserved) { 795 mutex_unlock(&priv->acpi_lock); 796 return -EBUSY; 797 } 798 799 pm_runtime_get_sync(&priv->pci_dev->dev); 800 801 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) 802 && size != I2C_SMBUS_QUICK 803 && size != I2C_SMBUS_I2C_BLOCK_DATA; 804 805 switch (size) { 806 case I2C_SMBUS_QUICK: 807 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 808 SMBHSTADD(priv)); 809 xact = I801_QUICK; 810 break; 811 case I2C_SMBUS_BYTE: 812 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 813 SMBHSTADD(priv)); 814 if (read_write == I2C_SMBUS_WRITE) 815 outb_p(command, SMBHSTCMD(priv)); 816 xact = I801_BYTE; 817 break; 818 case I2C_SMBUS_BYTE_DATA: 819 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 820 SMBHSTADD(priv)); 821 outb_p(command, SMBHSTCMD(priv)); 822 if (read_write == I2C_SMBUS_WRITE) 823 outb_p(data->byte, SMBHSTDAT0(priv)); 824 xact = I801_BYTE_DATA; 825 break; 826 case I2C_SMBUS_WORD_DATA: 827 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 828 SMBHSTADD(priv)); 829 outb_p(command, SMBHSTCMD(priv)); 830 if (read_write == I2C_SMBUS_WRITE) { 831 outb_p(data->word & 0xff, SMBHSTDAT0(priv)); 832 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); 833 } 834 xact = I801_WORD_DATA; 835 break; 836 case I2C_SMBUS_PROC_CALL: 837 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv)); 838 outb_p(command, SMBHSTCMD(priv)); 839 outb_p(data->word & 0xff, SMBHSTDAT0(priv)); 840 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); 841 xact = I801_PROC_CALL; 842 read_write = I2C_SMBUS_READ; 843 break; 844 case I2C_SMBUS_BLOCK_DATA: 845 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 846 SMBHSTADD(priv)); 847 outb_p(command, SMBHSTCMD(priv)); 848 block = 1; 849 break; 850 case I2C_SMBUS_I2C_BLOCK_DATA: 851 /* 852 * NB: page 240 of ICH5 datasheet shows that the R/#W 853 * bit should be cleared here, even when reading. 854 * However if SPD Write Disable is set (Lynx Point and later), 855 * the read will fail if we don't set the R/#W bit. 856 */ 857 outb_p(((addr & 0x7f) << 1) | 858 ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ? 859 (read_write & 0x01) : 0), 860 SMBHSTADD(priv)); 861 if (read_write == I2C_SMBUS_READ) { 862 /* NB: page 240 of ICH5 datasheet also shows 863 * that DATA1 is the cmd field when reading */ 864 outb_p(command, SMBHSTDAT1(priv)); 865 } else 866 outb_p(command, SMBHSTCMD(priv)); 867 block = 1; 868 break; 869 case I2C_SMBUS_BLOCK_PROC_CALL: 870 /* 871 * Bit 0 of the slave address register always indicate a write 872 * command. 873 */ 874 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv)); 875 outb_p(command, SMBHSTCMD(priv)); 876 block = 1; 877 break; 878 default: 879 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n", 880 size); 881 ret = -EOPNOTSUPP; 882 goto out; 883 } 884 885 if (hwpec) /* enable/disable hardware PEC */ 886 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv)); 887 else 888 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC), 889 SMBAUXCTL(priv)); 890 891 if (block) 892 ret = i801_block_transaction(priv, data, read_write, size); 893 else 894 ret = i801_transaction(priv, xact); 895 896 /* Some BIOSes don't like it when PEC is enabled at reboot or resume 897 time, so we forcibly disable it after every transaction. Turn off 898 E32B for the same reason. */ 899 if (hwpec || block) 900 outb_p(inb_p(SMBAUXCTL(priv)) & 901 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 902 903 if (block) 904 goto out; 905 if (ret) 906 goto out; 907 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK)) 908 goto out; 909 910 switch (xact) { 911 case I801_BYTE: /* Result put in SMBHSTDAT0 */ 912 case I801_BYTE_DATA: 913 data->byte = inb_p(SMBHSTDAT0(priv)); 914 break; 915 case I801_WORD_DATA: 916 case I801_PROC_CALL: 917 data->word = inb_p(SMBHSTDAT0(priv)) + 918 (inb_p(SMBHSTDAT1(priv)) << 8); 919 break; 920 } 921 922 out: 923 /* 924 * Unlock the SMBus device for use by BIOS/ACPI, 925 * and clear status flags if not done already. 926 */ 927 outb_p(SMBHSTSTS_INUSE_STS | STATUS_FLAGS, SMBHSTSTS(priv)); 928 929 pm_runtime_mark_last_busy(&priv->pci_dev->dev); 930 pm_runtime_put_autosuspend(&priv->pci_dev->dev); 931 mutex_unlock(&priv->acpi_lock); 932 return ret; 933 } 934 935 936 static u32 i801_func(struct i2c_adapter *adapter) 937 { 938 struct i801_priv *priv = i2c_get_adapdata(adapter); 939 940 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 941 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 942 I2C_FUNC_SMBUS_PROC_CALL | 943 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | 944 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | 945 ((priv->features & FEATURE_BLOCK_PROC) ? 946 I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) | 947 ((priv->features & FEATURE_I2C_BLOCK_READ) ? 948 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) | 949 ((priv->features & FEATURE_HOST_NOTIFY) ? 950 I2C_FUNC_SMBUS_HOST_NOTIFY : 0); 951 } 952 953 static void i801_enable_host_notify(struct i2c_adapter *adapter) 954 { 955 struct i801_priv *priv = i2c_get_adapdata(adapter); 956 957 if (!(priv->features & FEATURE_HOST_NOTIFY)) 958 return; 959 960 /* 961 * Enable host notify interrupt and block the generation of interrupt 962 * from the SMB_ALERT signal because the driver does not support 963 * SMBus Alert. 964 */ 965 outb_p(SMBSLVCMD_HST_NTFY_INTREN | SMBSLVCMD_SMBALERT_DISABLE | 966 priv->original_slvcmd, SMBSLVCMD(priv)); 967 968 /* clear Host Notify bit to allow a new notification */ 969 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 970 } 971 972 static void i801_disable_host_notify(struct i801_priv *priv) 973 { 974 if (!(priv->features & FEATURE_HOST_NOTIFY)) 975 return; 976 977 outb_p(priv->original_slvcmd, SMBSLVCMD(priv)); 978 } 979 980 static const struct i2c_algorithm smbus_algorithm = { 981 .smbus_xfer = i801_access, 982 .functionality = i801_func, 983 }; 984 985 #define FEATURES_ICH5 (FEATURE_BLOCK_PROC | FEATURE_I2C_BLOCK_READ | \ 986 FEATURE_IRQ | FEATURE_SMBUS_PEC | \ 987 FEATURE_BLOCK_BUFFER | FEATURE_HOST_NOTIFY) 988 #define FEATURES_ICH4 (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER | \ 989 FEATURE_HOST_NOTIFY) 990 991 static const struct pci_device_id i801_ids[] = { 992 { PCI_DEVICE_DATA(INTEL, 82801AA_3, 0) }, 993 { PCI_DEVICE_DATA(INTEL, 82801AB_3, 0) }, 994 { PCI_DEVICE_DATA(INTEL, 82801BA_2, 0) }, 995 { PCI_DEVICE_DATA(INTEL, 82801CA_3, FEATURE_HOST_NOTIFY) }, 996 { PCI_DEVICE_DATA(INTEL, 82801DB_3, FEATURES_ICH4) }, 997 { PCI_DEVICE_DATA(INTEL, 82801EB_3, FEATURES_ICH5) }, 998 { PCI_DEVICE_DATA(INTEL, ESB_4, FEATURES_ICH5) }, 999 { PCI_DEVICE_DATA(INTEL, ICH6_16, FEATURES_ICH5) }, 1000 { PCI_DEVICE_DATA(INTEL, ICH7_17, FEATURES_ICH5) }, 1001 { PCI_DEVICE_DATA(INTEL, ESB2_17, FEATURES_ICH5) }, 1002 { PCI_DEVICE_DATA(INTEL, ICH8_5, FEATURES_ICH5) }, 1003 { PCI_DEVICE_DATA(INTEL, ICH9_6, FEATURES_ICH5) }, 1004 { PCI_DEVICE_DATA(INTEL, EP80579_1, FEATURES_ICH5) }, 1005 { PCI_DEVICE_DATA(INTEL, ICH10_4, FEATURES_ICH5) }, 1006 { PCI_DEVICE_DATA(INTEL, ICH10_5, FEATURES_ICH5) }, 1007 { PCI_DEVICE_DATA(INTEL, 5_3400_SERIES_SMBUS, FEATURES_ICH5) }, 1008 { PCI_DEVICE_DATA(INTEL, COUGARPOINT_SMBUS, FEATURES_ICH5) }, 1009 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS, FEATURES_ICH5) }, 1010 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF0, FEATURES_ICH5 | FEATURE_IDF) }, 1011 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF1, FEATURES_ICH5 | FEATURE_IDF) }, 1012 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF2, FEATURES_ICH5 | FEATURE_IDF) }, 1013 { PCI_DEVICE_DATA(INTEL, DH89XXCC_SMBUS, FEATURES_ICH5) }, 1014 { PCI_DEVICE_DATA(INTEL, PANTHERPOINT_SMBUS, FEATURES_ICH5) }, 1015 { PCI_DEVICE_DATA(INTEL, LYNXPOINT_SMBUS, FEATURES_ICH5) }, 1016 { PCI_DEVICE_DATA(INTEL, LYNXPOINT_LP_SMBUS, FEATURES_ICH5) }, 1017 { PCI_DEVICE_DATA(INTEL, AVOTON_SMBUS, FEATURES_ICH5) }, 1018 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS, FEATURES_ICH5) }, 1019 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS0, FEATURES_ICH5 | FEATURE_IDF) }, 1020 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS1, FEATURES_ICH5 | FEATURE_IDF) }, 1021 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS2, FEATURES_ICH5 | FEATURE_IDF) }, 1022 { PCI_DEVICE_DATA(INTEL, COLETOCREEK_SMBUS, FEATURES_ICH5) }, 1023 { PCI_DEVICE_DATA(INTEL, GEMINILAKE_SMBUS, FEATURES_ICH5) }, 1024 { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_SMBUS, FEATURES_ICH5) }, 1025 { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_LP_SMBUS, FEATURES_ICH5) }, 1026 { PCI_DEVICE_DATA(INTEL, BAYTRAIL_SMBUS, FEATURES_ICH5) }, 1027 { PCI_DEVICE_DATA(INTEL, BRASWELL_SMBUS, FEATURES_ICH5) }, 1028 { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1029 { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1030 { PCI_DEVICE_DATA(INTEL, CDF_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1031 { PCI_DEVICE_DATA(INTEL, DNV_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1032 { PCI_DEVICE_DATA(INTEL, EBG_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1033 { PCI_DEVICE_DATA(INTEL, BROXTON_SMBUS, FEATURES_ICH5) }, 1034 { PCI_DEVICE_DATA(INTEL, LEWISBURG_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1035 { PCI_DEVICE_DATA(INTEL, LEWISBURG_SSKU_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1036 { PCI_DEVICE_DATA(INTEL, KABYLAKE_PCH_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1037 { PCI_DEVICE_DATA(INTEL, CANNONLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1038 { PCI_DEVICE_DATA(INTEL, CANNONLAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1039 { PCI_DEVICE_DATA(INTEL, ICELAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1040 { PCI_DEVICE_DATA(INTEL, ICELAKE_N_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1041 { PCI_DEVICE_DATA(INTEL, COMETLAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1042 { PCI_DEVICE_DATA(INTEL, COMETLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1043 { PCI_DEVICE_DATA(INTEL, COMETLAKE_V_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1044 { PCI_DEVICE_DATA(INTEL, ELKHART_LAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1045 { PCI_DEVICE_DATA(INTEL, TIGERLAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1046 { PCI_DEVICE_DATA(INTEL, TIGERLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1047 { PCI_DEVICE_DATA(INTEL, JASPER_LAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1048 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1049 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1050 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_M_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1051 { PCI_DEVICE_DATA(INTEL, RAPTOR_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1052 { 0, } 1053 }; 1054 1055 MODULE_DEVICE_TABLE(pci, i801_ids); 1056 1057 #if defined CONFIG_X86 && defined CONFIG_DMI 1058 static unsigned char apanel_addr; 1059 1060 /* Scan the system ROM for the signature "FJKEYINF" */ 1061 static __init const void __iomem *bios_signature(const void __iomem *bios) 1062 { 1063 ssize_t offset; 1064 const unsigned char signature[] = "FJKEYINF"; 1065 1066 for (offset = 0; offset < 0x10000; offset += 0x10) { 1067 if (check_signature(bios + offset, signature, 1068 sizeof(signature)-1)) 1069 return bios + offset; 1070 } 1071 return NULL; 1072 } 1073 1074 static void __init input_apanel_init(void) 1075 { 1076 void __iomem *bios; 1077 const void __iomem *p; 1078 1079 bios = ioremap(0xF0000, 0x10000); /* Can't fail */ 1080 p = bios_signature(bios); 1081 if (p) { 1082 /* just use the first address */ 1083 apanel_addr = readb(p + 8 + 3) >> 1; 1084 } 1085 iounmap(bios); 1086 } 1087 1088 struct dmi_onboard_device_info { 1089 const char *name; 1090 u8 type; 1091 unsigned short i2c_addr; 1092 const char *i2c_type; 1093 }; 1094 1095 static const struct dmi_onboard_device_info dmi_devices[] = { 1096 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" }, 1097 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" }, 1098 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" }, 1099 }; 1100 1101 static void dmi_check_onboard_device(u8 type, const char *name, 1102 struct i2c_adapter *adap) 1103 { 1104 int i; 1105 struct i2c_board_info info; 1106 1107 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) { 1108 /* & ~0x80, ignore enabled/disabled bit */ 1109 if ((type & ~0x80) != dmi_devices[i].type) 1110 continue; 1111 if (strcasecmp(name, dmi_devices[i].name)) 1112 continue; 1113 1114 memset(&info, 0, sizeof(struct i2c_board_info)); 1115 info.addr = dmi_devices[i].i2c_addr; 1116 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); 1117 i2c_new_client_device(adap, &info); 1118 break; 1119 } 1120 } 1121 1122 /* We use our own function to check for onboard devices instead of 1123 dmi_find_device() as some buggy BIOS's have the devices we are interested 1124 in marked as disabled */ 1125 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap) 1126 { 1127 int i, count; 1128 1129 if (dm->type != 10) 1130 return; 1131 1132 count = (dm->length - sizeof(struct dmi_header)) / 2; 1133 for (i = 0; i < count; i++) { 1134 const u8 *d = (char *)(dm + 1) + (i * 2); 1135 const char *name = ((char *) dm) + dm->length; 1136 u8 type = d[0]; 1137 u8 s = d[1]; 1138 1139 if (!s) 1140 continue; 1141 s--; 1142 while (s > 0 && name[0]) { 1143 name += strlen(name) + 1; 1144 s--; 1145 } 1146 if (name[0] == 0) /* Bogus string reference */ 1147 continue; 1148 1149 dmi_check_onboard_device(type, name, adap); 1150 } 1151 } 1152 1153 /* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */ 1154 static const char *const acpi_smo8800_ids[] = { 1155 "SMO8800", 1156 "SMO8801", 1157 "SMO8810", 1158 "SMO8811", 1159 "SMO8820", 1160 "SMO8821", 1161 "SMO8830", 1162 "SMO8831", 1163 }; 1164 1165 static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle, 1166 u32 nesting_level, 1167 void *context, 1168 void **return_value) 1169 { 1170 struct acpi_device_info *info; 1171 acpi_status status; 1172 char *hid; 1173 int i; 1174 1175 status = acpi_get_object_info(obj_handle, &info); 1176 if (ACPI_FAILURE(status)) 1177 return AE_OK; 1178 1179 if (!(info->valid & ACPI_VALID_HID)) 1180 goto smo88xx_not_found; 1181 1182 hid = info->hardware_id.string; 1183 if (!hid) 1184 goto smo88xx_not_found; 1185 1186 i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid); 1187 if (i < 0) 1188 goto smo88xx_not_found; 1189 1190 kfree(info); 1191 1192 *return_value = NULL; 1193 return AE_CTRL_TERMINATE; 1194 1195 smo88xx_not_found: 1196 kfree(info); 1197 return AE_OK; 1198 } 1199 1200 static bool is_dell_system_with_lis3lv02d(void) 1201 { 1202 void *err = ERR_PTR(-ENOENT); 1203 1204 if (!dmi_match(DMI_SYS_VENDOR, "Dell Inc.")) 1205 return false; 1206 1207 /* 1208 * Check that ACPI device SMO88xx is present and is functioning. 1209 * Function acpi_get_devices() already filters all ACPI devices 1210 * which are not present or are not functioning. 1211 * ACPI device SMO88xx represents our ST microelectronics lis3lv02d 1212 * accelerometer but unfortunately ACPI does not provide any other 1213 * information (like I2C address). 1214 */ 1215 acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL, &err); 1216 1217 return !IS_ERR(err); 1218 } 1219 1220 /* 1221 * Accelerometer's I2C address is not specified in DMI nor ACPI, 1222 * so it is needed to define mapping table based on DMI product names. 1223 */ 1224 static const struct { 1225 const char *dmi_product_name; 1226 unsigned short i2c_addr; 1227 } dell_lis3lv02d_devices[] = { 1228 /* 1229 * Dell platform team told us that these Latitude devices have 1230 * ST microelectronics accelerometer at I2C address 0x29. 1231 */ 1232 { "Latitude E5250", 0x29 }, 1233 { "Latitude E5450", 0x29 }, 1234 { "Latitude E5550", 0x29 }, 1235 { "Latitude E6440", 0x29 }, 1236 { "Latitude E6440 ATG", 0x29 }, 1237 { "Latitude E6540", 0x29 }, 1238 /* 1239 * Additional individual entries were added after verification. 1240 */ 1241 { "Latitude 5480", 0x29 }, 1242 { "Vostro V131", 0x1d }, 1243 }; 1244 1245 static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv) 1246 { 1247 struct i2c_board_info info; 1248 const char *dmi_product_name; 1249 int i; 1250 1251 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME); 1252 for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) { 1253 if (strcmp(dmi_product_name, 1254 dell_lis3lv02d_devices[i].dmi_product_name) == 0) 1255 break; 1256 } 1257 1258 if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) { 1259 dev_warn(&priv->pci_dev->dev, 1260 "Accelerometer lis3lv02d is present on SMBus but its" 1261 " address is unknown, skipping registration\n"); 1262 return; 1263 } 1264 1265 memset(&info, 0, sizeof(struct i2c_board_info)); 1266 info.addr = dell_lis3lv02d_devices[i].i2c_addr; 1267 strlcpy(info.type, "lis3lv02d", I2C_NAME_SIZE); 1268 i2c_new_client_device(&priv->adapter, &info); 1269 } 1270 1271 /* Register optional slaves */ 1272 static void i801_probe_optional_slaves(struct i801_priv *priv) 1273 { 1274 /* Only register slaves on main SMBus channel */ 1275 if (priv->features & FEATURE_IDF) 1276 return; 1277 1278 if (apanel_addr) { 1279 struct i2c_board_info info = { 1280 .addr = apanel_addr, 1281 .type = "fujitsu_apanel", 1282 }; 1283 1284 i2c_new_client_device(&priv->adapter, &info); 1285 } 1286 1287 if (dmi_name_in_vendors("FUJITSU")) 1288 dmi_walk(dmi_check_onboard_devices, &priv->adapter); 1289 1290 if (is_dell_system_with_lis3lv02d()) 1291 register_dell_lis3lv02d_i2c_device(priv); 1292 1293 /* Instantiate SPD EEPROMs unless the SMBus is multiplexed */ 1294 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) 1295 if (!priv->mux_drvdata) 1296 #endif 1297 i2c_register_spd(&priv->adapter); 1298 } 1299 #else 1300 static void __init input_apanel_init(void) {} 1301 static void i801_probe_optional_slaves(struct i801_priv *priv) {} 1302 #endif /* CONFIG_X86 && CONFIG_DMI */ 1303 1304 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 1305 static struct i801_mux_config i801_mux_config_asus_z8_d12 = { 1306 .gpio_chip = "gpio_ich", 1307 .values = { 0x02, 0x03 }, 1308 .n_values = 2, 1309 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD }, 1310 .gpios = { 52, 53 }, 1311 .n_gpios = 2, 1312 }; 1313 1314 static struct i801_mux_config i801_mux_config_asus_z8_d18 = { 1315 .gpio_chip = "gpio_ich", 1316 .values = { 0x02, 0x03, 0x01 }, 1317 .n_values = 3, 1318 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD }, 1319 .gpios = { 52, 53 }, 1320 .n_gpios = 2, 1321 }; 1322 1323 static const struct dmi_system_id mux_dmi_table[] = { 1324 { 1325 .matches = { 1326 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1327 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"), 1328 }, 1329 .driver_data = &i801_mux_config_asus_z8_d12, 1330 }, 1331 { 1332 .matches = { 1333 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1334 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"), 1335 }, 1336 .driver_data = &i801_mux_config_asus_z8_d12, 1337 }, 1338 { 1339 .matches = { 1340 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1341 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"), 1342 }, 1343 .driver_data = &i801_mux_config_asus_z8_d12, 1344 }, 1345 { 1346 .matches = { 1347 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1348 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"), 1349 }, 1350 .driver_data = &i801_mux_config_asus_z8_d12, 1351 }, 1352 { 1353 .matches = { 1354 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1355 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"), 1356 }, 1357 .driver_data = &i801_mux_config_asus_z8_d12, 1358 }, 1359 { 1360 .matches = { 1361 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1362 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"), 1363 }, 1364 .driver_data = &i801_mux_config_asus_z8_d12, 1365 }, 1366 { 1367 .matches = { 1368 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1369 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"), 1370 }, 1371 .driver_data = &i801_mux_config_asus_z8_d18, 1372 }, 1373 { 1374 .matches = { 1375 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1376 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"), 1377 }, 1378 .driver_data = &i801_mux_config_asus_z8_d18, 1379 }, 1380 { 1381 .matches = { 1382 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1383 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"), 1384 }, 1385 .driver_data = &i801_mux_config_asus_z8_d12, 1386 }, 1387 { } 1388 }; 1389 1390 /* Setup multiplexing if needed */ 1391 static void i801_add_mux(struct i801_priv *priv) 1392 { 1393 struct device *dev = &priv->adapter.dev; 1394 const struct i801_mux_config *mux_config; 1395 struct i2c_mux_gpio_platform_data gpio_data; 1396 struct gpiod_lookup_table *lookup; 1397 int i; 1398 1399 if (!priv->mux_drvdata) 1400 return; 1401 mux_config = priv->mux_drvdata; 1402 1403 /* Prepare the platform data */ 1404 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data)); 1405 gpio_data.parent = priv->adapter.nr; 1406 gpio_data.values = mux_config->values; 1407 gpio_data.n_values = mux_config->n_values; 1408 gpio_data.classes = mux_config->classes; 1409 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE; 1410 1411 /* Register GPIO descriptor lookup table */ 1412 lookup = devm_kzalloc(dev, 1413 struct_size(lookup, table, mux_config->n_gpios + 1), 1414 GFP_KERNEL); 1415 if (!lookup) 1416 return; 1417 lookup->dev_id = "i2c-mux-gpio"; 1418 for (i = 0; i < mux_config->n_gpios; i++) 1419 lookup->table[i] = GPIO_LOOKUP(mux_config->gpio_chip, 1420 mux_config->gpios[i], "mux", 0); 1421 gpiod_add_lookup_table(lookup); 1422 priv->lookup = lookup; 1423 1424 /* 1425 * Register the mux device, we use PLATFORM_DEVID_NONE here 1426 * because since we are referring to the GPIO chip by name we are 1427 * anyways in deep trouble if there is more than one of these 1428 * devices, and there should likely only be one platform controller 1429 * hub. 1430 */ 1431 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio", 1432 PLATFORM_DEVID_NONE, &gpio_data, 1433 sizeof(struct i2c_mux_gpio_platform_data)); 1434 if (IS_ERR(priv->mux_pdev)) { 1435 gpiod_remove_lookup_table(lookup); 1436 dev_err(dev, "Failed to register i2c-mux-gpio device\n"); 1437 } 1438 } 1439 1440 static void i801_del_mux(struct i801_priv *priv) 1441 { 1442 platform_device_unregister(priv->mux_pdev); 1443 gpiod_remove_lookup_table(priv->lookup); 1444 } 1445 1446 static unsigned int i801_get_adapter_class(struct i801_priv *priv) 1447 { 1448 const struct dmi_system_id *id; 1449 const struct i801_mux_config *mux_config; 1450 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 1451 int i; 1452 1453 id = dmi_first_match(mux_dmi_table); 1454 if (id) { 1455 /* Remove branch classes from trunk */ 1456 mux_config = id->driver_data; 1457 for (i = 0; i < mux_config->n_values; i++) 1458 class &= ~mux_config->classes[i]; 1459 1460 /* Remember for later */ 1461 priv->mux_drvdata = mux_config; 1462 } 1463 1464 return class; 1465 } 1466 #else 1467 static inline void i801_add_mux(struct i801_priv *priv) { } 1468 static inline void i801_del_mux(struct i801_priv *priv) { } 1469 1470 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv) 1471 { 1472 return I2C_CLASS_HWMON | I2C_CLASS_SPD; 1473 } 1474 #endif 1475 1476 static struct platform_device * 1477 i801_add_tco_spt(struct i801_priv *priv, struct pci_dev *pci_dev, 1478 struct resource *tco_res) 1479 { 1480 static const struct itco_wdt_platform_data pldata = { 1481 .name = "Intel PCH", 1482 .version = 4, 1483 }; 1484 struct resource *res; 1485 unsigned int devfn; 1486 u64 base64_addr; 1487 u32 base_addr; 1488 u8 hidden; 1489 1490 /* 1491 * We must access the NO_REBOOT bit over the Primary to Sideband 1492 * bridge (P2SB). The BIOS prevents the P2SB device from being 1493 * enumerated by the PCI subsystem, so we need to unhide/hide it 1494 * to lookup the P2SB BAR. 1495 */ 1496 pci_lock_rescan_remove(); 1497 1498 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1); 1499 1500 /* Unhide the P2SB device, if it is hidden */ 1501 pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden); 1502 if (hidden) 1503 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0); 1504 1505 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr); 1506 base64_addr = base_addr & 0xfffffff0; 1507 1508 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr); 1509 base64_addr |= (u64)base_addr << 32; 1510 1511 /* Hide the P2SB device, if it was hidden before */ 1512 if (hidden) 1513 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden); 1514 pci_unlock_rescan_remove(); 1515 1516 res = &tco_res[1]; 1517 if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS) 1518 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV; 1519 else 1520 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL; 1521 1522 res->end = res->start + 3; 1523 res->flags = IORESOURCE_MEM; 1524 1525 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1, 1526 tco_res, 2, &pldata, sizeof(pldata)); 1527 } 1528 1529 static struct platform_device * 1530 i801_add_tco_cnl(struct i801_priv *priv, struct pci_dev *pci_dev, 1531 struct resource *tco_res) 1532 { 1533 static const struct itco_wdt_platform_data pldata = { 1534 .name = "Intel PCH", 1535 .version = 6, 1536 }; 1537 1538 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1, 1539 tco_res, 1, &pldata, sizeof(pldata)); 1540 } 1541 1542 static void i801_add_tco(struct i801_priv *priv) 1543 { 1544 struct pci_dev *pci_dev = priv->pci_dev; 1545 struct resource tco_res[2], *res; 1546 u32 tco_base, tco_ctl; 1547 1548 /* If we have ACPI based watchdog use that instead */ 1549 if (acpi_has_watchdog()) 1550 return; 1551 1552 if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL))) 1553 return; 1554 1555 pci_read_config_dword(pci_dev, TCOBASE, &tco_base); 1556 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl); 1557 if (!(tco_ctl & TCOCTL_EN)) 1558 return; 1559 1560 memset(tco_res, 0, sizeof(tco_res)); 1561 /* 1562 * Always populate the main iTCO IO resource here. The second entry 1563 * for NO_REBOOT MMIO is filled by the SPT specific function. 1564 */ 1565 res = &tco_res[0]; 1566 res->start = tco_base & ~1; 1567 res->end = res->start + 32 - 1; 1568 res->flags = IORESOURCE_IO; 1569 1570 if (priv->features & FEATURE_TCO_CNL) 1571 priv->tco_pdev = i801_add_tco_cnl(priv, pci_dev, tco_res); 1572 else 1573 priv->tco_pdev = i801_add_tco_spt(priv, pci_dev, tco_res); 1574 1575 if (IS_ERR(priv->tco_pdev)) 1576 dev_warn(&pci_dev->dev, "failed to create iTCO device\n"); 1577 } 1578 1579 #ifdef CONFIG_ACPI 1580 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv, 1581 acpi_physical_address address) 1582 { 1583 return address >= priv->smba && 1584 address <= pci_resource_end(priv->pci_dev, SMBBAR); 1585 } 1586 1587 static acpi_status 1588 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits, 1589 u64 *value, void *handler_context, void *region_context) 1590 { 1591 struct i801_priv *priv = handler_context; 1592 struct pci_dev *pdev = priv->pci_dev; 1593 acpi_status status; 1594 1595 /* 1596 * Once BIOS AML code touches the OpRegion we warn and inhibit any 1597 * further access from the driver itself. This device is now owned 1598 * by the system firmware. 1599 */ 1600 mutex_lock(&priv->acpi_lock); 1601 1602 if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) { 1603 priv->acpi_reserved = true; 1604 1605 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n"); 1606 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n"); 1607 1608 /* 1609 * BIOS is accessing the host controller so prevent it from 1610 * suspending automatically from now on. 1611 */ 1612 pm_runtime_get_sync(&pdev->dev); 1613 } 1614 1615 if ((function & ACPI_IO_MASK) == ACPI_READ) 1616 status = acpi_os_read_port(address, (u32 *)value, bits); 1617 else 1618 status = acpi_os_write_port(address, (u32)*value, bits); 1619 1620 mutex_unlock(&priv->acpi_lock); 1621 1622 return status; 1623 } 1624 1625 static int i801_acpi_probe(struct i801_priv *priv) 1626 { 1627 acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev); 1628 acpi_status status; 1629 1630 status = acpi_install_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO, 1631 i801_acpi_io_handler, NULL, priv); 1632 if (ACPI_SUCCESS(status)) 1633 return 0; 1634 1635 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]); 1636 } 1637 1638 static void i801_acpi_remove(struct i801_priv *priv) 1639 { 1640 acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev); 1641 1642 acpi_remove_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler); 1643 } 1644 #else 1645 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; } 1646 static inline void i801_acpi_remove(struct i801_priv *priv) { } 1647 #endif 1648 1649 static void i801_setup_hstcfg(struct i801_priv *priv) 1650 { 1651 unsigned char hstcfg = priv->original_hstcfg; 1652 1653 hstcfg &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ 1654 hstcfg |= SMBHSTCFG_HST_EN; 1655 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hstcfg); 1656 } 1657 1658 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id) 1659 { 1660 int err, i; 1661 struct i801_priv *priv; 1662 1663 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL); 1664 if (!priv) 1665 return -ENOMEM; 1666 1667 i2c_set_adapdata(&priv->adapter, priv); 1668 priv->adapter.owner = THIS_MODULE; 1669 priv->adapter.class = i801_get_adapter_class(priv); 1670 priv->adapter.algo = &smbus_algorithm; 1671 priv->adapter.dev.parent = &dev->dev; 1672 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev)); 1673 priv->adapter.retries = 3; 1674 mutex_init(&priv->acpi_lock); 1675 1676 priv->pci_dev = dev; 1677 priv->features = id->driver_data; 1678 1679 /* Disable features on user request */ 1680 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) { 1681 if (priv->features & disable_features & (1 << i)) 1682 dev_notice(&dev->dev, "%s disabled by user\n", 1683 i801_feature_names[i]); 1684 } 1685 priv->features &= ~disable_features; 1686 1687 err = pcim_enable_device(dev); 1688 if (err) { 1689 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", 1690 err); 1691 return err; 1692 } 1693 pcim_pin_device(dev); 1694 1695 /* Determine the address of the SMBus area */ 1696 priv->smba = pci_resource_start(dev, SMBBAR); 1697 if (!priv->smba) { 1698 dev_err(&dev->dev, 1699 "SMBus base address uninitialized, upgrade BIOS\n"); 1700 return -ENODEV; 1701 } 1702 1703 if (i801_acpi_probe(priv)) 1704 return -ENODEV; 1705 1706 err = pcim_iomap_regions(dev, 1 << SMBBAR, DRV_NAME); 1707 if (err) { 1708 dev_err(&dev->dev, 1709 "Failed to request SMBus region 0x%lx-0x%Lx\n", 1710 priv->smba, 1711 (unsigned long long)pci_resource_end(dev, SMBBAR)); 1712 i801_acpi_remove(priv); 1713 return err; 1714 } 1715 1716 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &priv->original_hstcfg); 1717 i801_setup_hstcfg(priv); 1718 if (!(priv->original_hstcfg & SMBHSTCFG_HST_EN)) 1719 dev_info(&dev->dev, "Enabling SMBus device\n"); 1720 1721 if (priv->original_hstcfg & SMBHSTCFG_SMB_SMI_EN) { 1722 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); 1723 /* Disable SMBus interrupt feature if SMBus using SMI# */ 1724 priv->features &= ~FEATURE_IRQ; 1725 } 1726 if (priv->original_hstcfg & SMBHSTCFG_SPD_WD) 1727 dev_info(&dev->dev, "SPD Write Disable is set\n"); 1728 1729 /* Clear special mode bits */ 1730 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) 1731 outb_p(inb_p(SMBAUXCTL(priv)) & 1732 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 1733 1734 /* Remember original Interrupt and Host Notify settings */ 1735 priv->original_hstcnt = inb_p(SMBHSTCNT(priv)) & ~SMBHSTCNT_KILL; 1736 if (priv->features & FEATURE_HOST_NOTIFY) 1737 priv->original_slvcmd = inb_p(SMBSLVCMD(priv)); 1738 1739 /* Default timeout in interrupt mode: 200 ms */ 1740 priv->adapter.timeout = HZ / 5; 1741 1742 if (dev->irq == IRQ_NOTCONNECTED) 1743 priv->features &= ~FEATURE_IRQ; 1744 1745 if (priv->features & FEATURE_IRQ) { 1746 u16 pcists; 1747 1748 /* Complain if an interrupt is already pending */ 1749 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists); 1750 if (pcists & PCI_STATUS_INTERRUPT) 1751 dev_warn(&dev->dev, "An interrupt is pending!\n"); 1752 } 1753 1754 if (priv->features & FEATURE_IRQ) { 1755 init_completion(&priv->done); 1756 1757 err = devm_request_irq(&dev->dev, dev->irq, i801_isr, 1758 IRQF_SHARED, DRV_NAME, priv); 1759 if (err) { 1760 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n", 1761 dev->irq, err); 1762 priv->features &= ~FEATURE_IRQ; 1763 } 1764 } 1765 dev_info(&dev->dev, "SMBus using %s\n", 1766 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling"); 1767 1768 i801_add_tco(priv); 1769 1770 snprintf(priv->adapter.name, sizeof(priv->adapter.name), 1771 "SMBus I801 adapter at %04lx", priv->smba); 1772 err = i2c_add_adapter(&priv->adapter); 1773 if (err) { 1774 i801_acpi_remove(priv); 1775 return err; 1776 } 1777 1778 i801_enable_host_notify(&priv->adapter); 1779 1780 i801_probe_optional_slaves(priv); 1781 /* We ignore errors - multiplexing is optional */ 1782 i801_add_mux(priv); 1783 1784 pci_set_drvdata(dev, priv); 1785 1786 dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 1787 pm_runtime_set_autosuspend_delay(&dev->dev, 1000); 1788 pm_runtime_use_autosuspend(&dev->dev); 1789 pm_runtime_put_autosuspend(&dev->dev); 1790 pm_runtime_allow(&dev->dev); 1791 1792 return 0; 1793 } 1794 1795 static void i801_remove(struct pci_dev *dev) 1796 { 1797 struct i801_priv *priv = pci_get_drvdata(dev); 1798 1799 outb_p(priv->original_hstcnt, SMBHSTCNT(priv)); 1800 i801_disable_host_notify(priv); 1801 i801_del_mux(priv); 1802 i2c_del_adapter(&priv->adapter); 1803 i801_acpi_remove(priv); 1804 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); 1805 1806 platform_device_unregister(priv->tco_pdev); 1807 1808 /* if acpi_reserved is set then usage_count is incremented already */ 1809 if (!priv->acpi_reserved) 1810 pm_runtime_get_noresume(&dev->dev); 1811 1812 /* 1813 * do not call pci_disable_device(dev) since it can cause hard hangs on 1814 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) 1815 */ 1816 } 1817 1818 static void i801_shutdown(struct pci_dev *dev) 1819 { 1820 struct i801_priv *priv = pci_get_drvdata(dev); 1821 1822 /* Restore config registers to avoid hard hang on some systems */ 1823 outb_p(priv->original_hstcnt, SMBHSTCNT(priv)); 1824 i801_disable_host_notify(priv); 1825 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); 1826 } 1827 1828 #ifdef CONFIG_PM_SLEEP 1829 static int i801_suspend(struct device *dev) 1830 { 1831 struct i801_priv *priv = dev_get_drvdata(dev); 1832 1833 outb_p(priv->original_hstcnt, SMBHSTCNT(priv)); 1834 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, priv->original_hstcfg); 1835 return 0; 1836 } 1837 1838 static int i801_resume(struct device *dev) 1839 { 1840 struct i801_priv *priv = dev_get_drvdata(dev); 1841 1842 i801_setup_hstcfg(priv); 1843 i801_enable_host_notify(&priv->adapter); 1844 1845 return 0; 1846 } 1847 #endif 1848 1849 static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume); 1850 1851 static struct pci_driver i801_driver = { 1852 .name = DRV_NAME, 1853 .id_table = i801_ids, 1854 .probe = i801_probe, 1855 .remove = i801_remove, 1856 .shutdown = i801_shutdown, 1857 .driver = { 1858 .pm = &i801_pm_ops, 1859 }, 1860 }; 1861 1862 static int __init i2c_i801_init(void) 1863 { 1864 if (dmi_name_in_vendors("FUJITSU")) 1865 input_apanel_init(); 1866 return pci_register_driver(&i801_driver); 1867 } 1868 1869 static void __exit i2c_i801_exit(void) 1870 { 1871 pci_unregister_driver(&i801_driver); 1872 } 1873 1874 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>"); 1875 MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>"); 1876 MODULE_DESCRIPTION("I801 SMBus driver"); 1877 MODULE_LICENSE("GPL"); 1878 1879 module_init(i2c_i801_init); 1880 module_exit(i2c_i801_exit); 1881