1 /* 2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, 3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker 4 <mdsxyz123@yahoo.com> 5 Copyright (C) 2007 - 2012 Jean Delvare <jdelvare@suse.de> 6 Copyright (C) 2010 Intel Corporation, 7 David Woodhouse <dwmw2@infradead.org> 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 2 of the License, or 12 (at your option) any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program; if not, write to the Free Software 21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 22 */ 23 24 /* 25 Supports the following Intel I/O Controller Hubs (ICH): 26 27 I/O Block I2C 28 region SMBus Block proc. block 29 Chip name PCI ID size PEC buffer call read 30 ---------------------------------------------------------------------- 31 82801AA (ICH) 0x2413 16 no no no no 32 82801AB (ICH0) 0x2423 16 no no no no 33 82801BA (ICH2) 0x2443 16 no no no no 34 82801CA (ICH3) 0x2483 32 soft no no no 35 82801DB (ICH4) 0x24c3 32 hard yes no no 36 82801E (ICH5) 0x24d3 32 hard yes yes yes 37 6300ESB 0x25a4 32 hard yes yes yes 38 82801F (ICH6) 0x266a 32 hard yes yes yes 39 6310ESB/6320ESB 0x269b 32 hard yes yes yes 40 82801G (ICH7) 0x27da 32 hard yes yes yes 41 82801H (ICH8) 0x283e 32 hard yes yes yes 42 82801I (ICH9) 0x2930 32 hard yes yes yes 43 EP80579 (Tolapai) 0x5032 32 hard yes yes yes 44 ICH10 0x3a30 32 hard yes yes yes 45 ICH10 0x3a60 32 hard yes yes yes 46 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes 47 6 Series (PCH) 0x1c22 32 hard yes yes yes 48 Patsburg (PCH) 0x1d22 32 hard yes yes yes 49 Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes 50 Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes 51 Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes 52 DH89xxCC (PCH) 0x2330 32 hard yes yes yes 53 Panther Point (PCH) 0x1e22 32 hard yes yes yes 54 Lynx Point (PCH) 0x8c22 32 hard yes yes yes 55 Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes 56 Avoton (SOC) 0x1f3c 32 hard yes yes yes 57 Wellsburg (PCH) 0x8d22 32 hard yes yes yes 58 Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes 59 Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes 60 Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes 61 Coleto Creek (PCH) 0x23b0 32 hard yes yes yes 62 Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes 63 BayTrail (SOC) 0x0f12 32 hard yes yes yes 64 65 Features supported by this driver: 66 Software PEC no 67 Hardware PEC yes 68 Block buffer yes 69 Block process call transaction no 70 I2C block read transaction yes (doesn't use the block buffer) 71 Slave mode no 72 Interrupt processing yes 73 74 See the file Documentation/i2c/busses/i2c-i801 for details. 75 */ 76 77 #include <linux/interrupt.h> 78 #include <linux/module.h> 79 #include <linux/pci.h> 80 #include <linux/kernel.h> 81 #include <linux/stddef.h> 82 #include <linux/delay.h> 83 #include <linux/ioport.h> 84 #include <linux/init.h> 85 #include <linux/i2c.h> 86 #include <linux/acpi.h> 87 #include <linux/io.h> 88 #include <linux/dmi.h> 89 #include <linux/slab.h> 90 #include <linux/wait.h> 91 #include <linux/err.h> 92 93 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \ 94 defined CONFIG_DMI 95 #include <linux/gpio.h> 96 #include <linux/i2c-mux-gpio.h> 97 #include <linux/platform_device.h> 98 #endif 99 100 /* I801 SMBus address offsets */ 101 #define SMBHSTSTS(p) (0 + (p)->smba) 102 #define SMBHSTCNT(p) (2 + (p)->smba) 103 #define SMBHSTCMD(p) (3 + (p)->smba) 104 #define SMBHSTADD(p) (4 + (p)->smba) 105 #define SMBHSTDAT0(p) (5 + (p)->smba) 106 #define SMBHSTDAT1(p) (6 + (p)->smba) 107 #define SMBBLKDAT(p) (7 + (p)->smba) 108 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */ 109 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */ 110 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */ 111 112 /* PCI Address Constants */ 113 #define SMBBAR 4 114 #define SMBPCISTS 0x006 115 #define SMBHSTCFG 0x040 116 117 /* Host status bits for SMBPCISTS */ 118 #define SMBPCISTS_INTS 0x08 119 120 /* Host configuration bits for SMBHSTCFG */ 121 #define SMBHSTCFG_HST_EN 1 122 #define SMBHSTCFG_SMB_SMI_EN 2 123 #define SMBHSTCFG_I2C_EN 4 124 125 /* Auxiliary control register bits, ICH4+ only */ 126 #define SMBAUXCTL_CRC 1 127 #define SMBAUXCTL_E32B 2 128 129 /* Other settings */ 130 #define MAX_RETRIES 400 131 132 /* I801 command constants */ 133 #define I801_QUICK 0x00 134 #define I801_BYTE 0x04 135 #define I801_BYTE_DATA 0x08 136 #define I801_WORD_DATA 0x0C 137 #define I801_PROC_CALL 0x10 /* unimplemented */ 138 #define I801_BLOCK_DATA 0x14 139 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ 140 141 /* I801 Host Control register bits */ 142 #define SMBHSTCNT_INTREN 0x01 143 #define SMBHSTCNT_KILL 0x02 144 #define SMBHSTCNT_LAST_BYTE 0x20 145 #define SMBHSTCNT_START 0x40 146 #define SMBHSTCNT_PEC_EN 0x80 /* ICH3 and later */ 147 148 /* I801 Hosts Status register bits */ 149 #define SMBHSTSTS_BYTE_DONE 0x80 150 #define SMBHSTSTS_INUSE_STS 0x40 151 #define SMBHSTSTS_SMBALERT_STS 0x20 152 #define SMBHSTSTS_FAILED 0x10 153 #define SMBHSTSTS_BUS_ERR 0x08 154 #define SMBHSTSTS_DEV_ERR 0x04 155 #define SMBHSTSTS_INTR 0x02 156 #define SMBHSTSTS_HOST_BUSY 0x01 157 158 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \ 159 SMBHSTSTS_DEV_ERR) 160 161 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \ 162 STATUS_ERROR_FLAGS) 163 164 /* Older devices have their ID defined in <linux/pci_ids.h> */ 165 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12 166 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 167 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 168 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */ 169 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70 170 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71 171 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72 172 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 173 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c 174 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 175 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0 176 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 177 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 178 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22 179 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d 180 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e 181 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f 182 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22 183 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2 184 185 struct i801_mux_config { 186 char *gpio_chip; 187 unsigned values[3]; 188 int n_values; 189 unsigned classes[3]; 190 unsigned gpios[2]; /* Relative to gpio_chip->base */ 191 int n_gpios; 192 }; 193 194 struct i801_priv { 195 struct i2c_adapter adapter; 196 unsigned long smba; 197 unsigned char original_hstcfg; 198 struct pci_dev *pci_dev; 199 unsigned int features; 200 201 /* isr processing */ 202 wait_queue_head_t waitq; 203 u8 status; 204 205 /* Command state used by isr for byte-by-byte block transactions */ 206 u8 cmd; 207 bool is_read; 208 int count; 209 int len; 210 u8 *data; 211 212 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \ 213 defined CONFIG_DMI 214 const struct i801_mux_config *mux_drvdata; 215 struct platform_device *mux_pdev; 216 #endif 217 }; 218 219 static struct pci_driver i801_driver; 220 221 #define FEATURE_SMBUS_PEC (1 << 0) 222 #define FEATURE_BLOCK_BUFFER (1 << 1) 223 #define FEATURE_BLOCK_PROC (1 << 2) 224 #define FEATURE_I2C_BLOCK_READ (1 << 3) 225 #define FEATURE_IRQ (1 << 4) 226 /* Not really a feature, but it's convenient to handle it as such */ 227 #define FEATURE_IDF (1 << 15) 228 229 static const char *i801_feature_names[] = { 230 "SMBus PEC", 231 "Block buffer", 232 "Block process call", 233 "I2C block read", 234 "Interrupt", 235 }; 236 237 static unsigned int disable_features; 238 module_param(disable_features, uint, S_IRUGO | S_IWUSR); 239 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n" 240 "\t\t 0x01 disable SMBus PEC\n" 241 "\t\t 0x02 disable the block buffer\n" 242 "\t\t 0x08 disable the I2C block read functionality\n" 243 "\t\t 0x10 don't use interrupts "); 244 245 /* Make sure the SMBus host is ready to start transmitting. 246 Return 0 if it is, -EBUSY if it is not. */ 247 static int i801_check_pre(struct i801_priv *priv) 248 { 249 int status; 250 251 status = inb_p(SMBHSTSTS(priv)); 252 if (status & SMBHSTSTS_HOST_BUSY) { 253 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n"); 254 return -EBUSY; 255 } 256 257 status &= STATUS_FLAGS; 258 if (status) { 259 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n", 260 status); 261 outb_p(status, SMBHSTSTS(priv)); 262 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS; 263 if (status) { 264 dev_err(&priv->pci_dev->dev, 265 "Failed clearing status flags (%02x)\n", 266 status); 267 return -EBUSY; 268 } 269 } 270 271 return 0; 272 } 273 274 /* 275 * Convert the status register to an error code, and clear it. 276 * Note that status only contains the bits we want to clear, not the 277 * actual register value. 278 */ 279 static int i801_check_post(struct i801_priv *priv, int status) 280 { 281 int result = 0; 282 283 /* 284 * If the SMBus is still busy, we give up 285 * Note: This timeout condition only happens when using polling 286 * transactions. For interrupt operation, NAK/timeout is indicated by 287 * DEV_ERR. 288 */ 289 if (unlikely(status < 0)) { 290 dev_err(&priv->pci_dev->dev, "Transaction timeout\n"); 291 /* try to stop the current command */ 292 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n"); 293 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL, 294 SMBHSTCNT(priv)); 295 usleep_range(1000, 2000); 296 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL), 297 SMBHSTCNT(priv)); 298 299 /* Check if it worked */ 300 status = inb_p(SMBHSTSTS(priv)); 301 if ((status & SMBHSTSTS_HOST_BUSY) || 302 !(status & SMBHSTSTS_FAILED)) 303 dev_err(&priv->pci_dev->dev, 304 "Failed terminating the transaction\n"); 305 outb_p(STATUS_FLAGS, SMBHSTSTS(priv)); 306 return -ETIMEDOUT; 307 } 308 309 if (status & SMBHSTSTS_FAILED) { 310 result = -EIO; 311 dev_err(&priv->pci_dev->dev, "Transaction failed\n"); 312 } 313 if (status & SMBHSTSTS_DEV_ERR) { 314 result = -ENXIO; 315 dev_dbg(&priv->pci_dev->dev, "No response\n"); 316 } 317 if (status & SMBHSTSTS_BUS_ERR) { 318 result = -EAGAIN; 319 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n"); 320 } 321 322 /* Clear status flags except BYTE_DONE, to be cleared by caller */ 323 outb_p(status, SMBHSTSTS(priv)); 324 325 return result; 326 } 327 328 /* Wait for BUSY being cleared and either INTR or an error flag being set */ 329 static int i801_wait_intr(struct i801_priv *priv) 330 { 331 int timeout = 0; 332 int status; 333 334 /* We will always wait for a fraction of a second! */ 335 do { 336 usleep_range(250, 500); 337 status = inb_p(SMBHSTSTS(priv)); 338 } while (((status & SMBHSTSTS_HOST_BUSY) || 339 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) && 340 (timeout++ < MAX_RETRIES)); 341 342 if (timeout > MAX_RETRIES) { 343 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n"); 344 return -ETIMEDOUT; 345 } 346 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR); 347 } 348 349 /* Wait for either BYTE_DONE or an error flag being set */ 350 static int i801_wait_byte_done(struct i801_priv *priv) 351 { 352 int timeout = 0; 353 int status; 354 355 /* We will always wait for a fraction of a second! */ 356 do { 357 usleep_range(250, 500); 358 status = inb_p(SMBHSTSTS(priv)); 359 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) && 360 (timeout++ < MAX_RETRIES)); 361 362 if (timeout > MAX_RETRIES) { 363 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n"); 364 return -ETIMEDOUT; 365 } 366 return status & STATUS_ERROR_FLAGS; 367 } 368 369 static int i801_transaction(struct i801_priv *priv, int xact) 370 { 371 int status; 372 int result; 373 374 result = i801_check_pre(priv); 375 if (result < 0) 376 return result; 377 378 if (priv->features & FEATURE_IRQ) { 379 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START, 380 SMBHSTCNT(priv)); 381 wait_event(priv->waitq, (status = priv->status)); 382 priv->status = 0; 383 return i801_check_post(priv, status); 384 } 385 386 /* the current contents of SMBHSTCNT can be overwritten, since PEC, 387 * SMBSCMD are passed in xact */ 388 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv)); 389 390 status = i801_wait_intr(priv); 391 return i801_check_post(priv, status); 392 } 393 394 static int i801_block_transaction_by_block(struct i801_priv *priv, 395 union i2c_smbus_data *data, 396 char read_write, int hwpec) 397 { 398 int i, len; 399 int status; 400 401 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ 402 403 /* Use 32-byte buffer to process this transaction */ 404 if (read_write == I2C_SMBUS_WRITE) { 405 len = data->block[0]; 406 outb_p(len, SMBHSTDAT0(priv)); 407 for (i = 0; i < len; i++) 408 outb_p(data->block[i+1], SMBBLKDAT(priv)); 409 } 410 411 status = i801_transaction(priv, I801_BLOCK_DATA | 412 (hwpec ? SMBHSTCNT_PEC_EN : 0)); 413 if (status) 414 return status; 415 416 if (read_write == I2C_SMBUS_READ) { 417 len = inb_p(SMBHSTDAT0(priv)); 418 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) 419 return -EPROTO; 420 421 data->block[0] = len; 422 for (i = 0; i < len; i++) 423 data->block[i + 1] = inb_p(SMBBLKDAT(priv)); 424 } 425 return 0; 426 } 427 428 static void i801_isr_byte_done(struct i801_priv *priv) 429 { 430 if (priv->is_read) { 431 /* For SMBus block reads, length is received with first byte */ 432 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) && 433 (priv->count == 0)) { 434 priv->len = inb_p(SMBHSTDAT0(priv)); 435 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) { 436 dev_err(&priv->pci_dev->dev, 437 "Illegal SMBus block read size %d\n", 438 priv->len); 439 /* FIXME: Recover */ 440 priv->len = I2C_SMBUS_BLOCK_MAX; 441 } else { 442 dev_dbg(&priv->pci_dev->dev, 443 "SMBus block read size is %d\n", 444 priv->len); 445 } 446 priv->data[-1] = priv->len; 447 } 448 449 /* Read next byte */ 450 if (priv->count < priv->len) 451 priv->data[priv->count++] = inb(SMBBLKDAT(priv)); 452 else 453 dev_dbg(&priv->pci_dev->dev, 454 "Discarding extra byte on block read\n"); 455 456 /* Set LAST_BYTE for last byte of read transaction */ 457 if (priv->count == priv->len - 1) 458 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE, 459 SMBHSTCNT(priv)); 460 } else if (priv->count < priv->len - 1) { 461 /* Write next byte, except for IRQ after last byte */ 462 outb_p(priv->data[++priv->count], SMBBLKDAT(priv)); 463 } 464 465 /* Clear BYTE_DONE to continue with next byte */ 466 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 467 } 468 469 /* 470 * There are two kinds of interrupts: 471 * 472 * 1) i801 signals transaction completion with one of these interrupts: 473 * INTR - Success 474 * DEV_ERR - Invalid command, NAK or communication timeout 475 * BUS_ERR - SMI# transaction collision 476 * FAILED - transaction was canceled due to a KILL request 477 * When any of these occur, update ->status and wake up the waitq. 478 * ->status must be cleared before kicking off the next transaction. 479 * 480 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt 481 * occurs for each byte of a byte-by-byte to prepare the next byte. 482 */ 483 static irqreturn_t i801_isr(int irq, void *dev_id) 484 { 485 struct i801_priv *priv = dev_id; 486 u16 pcists; 487 u8 status; 488 489 /* Confirm this is our interrupt */ 490 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); 491 if (!(pcists & SMBPCISTS_INTS)) 492 return IRQ_NONE; 493 494 status = inb_p(SMBHSTSTS(priv)); 495 if (status != 0x42) 496 dev_dbg(&priv->pci_dev->dev, "irq: status = %02x\n", status); 497 498 if (status & SMBHSTSTS_BYTE_DONE) 499 i801_isr_byte_done(priv); 500 501 /* 502 * Clear irq sources and report transaction result. 503 * ->status must be cleared before the next transaction is started. 504 */ 505 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS; 506 if (status) { 507 outb_p(status, SMBHSTSTS(priv)); 508 priv->status |= status; 509 wake_up(&priv->waitq); 510 } 511 512 return IRQ_HANDLED; 513 } 514 515 /* 516 * For "byte-by-byte" block transactions: 517 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1 518 * I2C read uses cmd=I801_I2C_BLOCK_DATA 519 */ 520 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, 521 union i2c_smbus_data *data, 522 char read_write, int command, 523 int hwpec) 524 { 525 int i, len; 526 int smbcmd; 527 int status; 528 int result; 529 530 result = i801_check_pre(priv); 531 if (result < 0) 532 return result; 533 534 len = data->block[0]; 535 536 if (read_write == I2C_SMBUS_WRITE) { 537 outb_p(len, SMBHSTDAT0(priv)); 538 outb_p(data->block[1], SMBBLKDAT(priv)); 539 } 540 541 if (command == I2C_SMBUS_I2C_BLOCK_DATA && 542 read_write == I2C_SMBUS_READ) 543 smbcmd = I801_I2C_BLOCK_DATA; 544 else 545 smbcmd = I801_BLOCK_DATA; 546 547 if (priv->features & FEATURE_IRQ) { 548 priv->is_read = (read_write == I2C_SMBUS_READ); 549 if (len == 1 && priv->is_read) 550 smbcmd |= SMBHSTCNT_LAST_BYTE; 551 priv->cmd = smbcmd | SMBHSTCNT_INTREN; 552 priv->len = len; 553 priv->count = 0; 554 priv->data = &data->block[1]; 555 556 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv)); 557 wait_event(priv->waitq, (status = priv->status)); 558 priv->status = 0; 559 return i801_check_post(priv, status); 560 } 561 562 for (i = 1; i <= len; i++) { 563 if (i == len && read_write == I2C_SMBUS_READ) 564 smbcmd |= SMBHSTCNT_LAST_BYTE; 565 outb_p(smbcmd, SMBHSTCNT(priv)); 566 567 if (i == 1) 568 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START, 569 SMBHSTCNT(priv)); 570 571 status = i801_wait_byte_done(priv); 572 if (status) 573 goto exit; 574 575 if (i == 1 && read_write == I2C_SMBUS_READ 576 && command != I2C_SMBUS_I2C_BLOCK_DATA) { 577 len = inb_p(SMBHSTDAT0(priv)); 578 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { 579 dev_err(&priv->pci_dev->dev, 580 "Illegal SMBus block read size %d\n", 581 len); 582 /* Recover */ 583 while (inb_p(SMBHSTSTS(priv)) & 584 SMBHSTSTS_HOST_BUSY) 585 outb_p(SMBHSTSTS_BYTE_DONE, 586 SMBHSTSTS(priv)); 587 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); 588 return -EPROTO; 589 } 590 data->block[0] = len; 591 } 592 593 /* Retrieve/store value in SMBBLKDAT */ 594 if (read_write == I2C_SMBUS_READ) 595 data->block[i] = inb_p(SMBBLKDAT(priv)); 596 if (read_write == I2C_SMBUS_WRITE && i+1 <= len) 597 outb_p(data->block[i+1], SMBBLKDAT(priv)); 598 599 /* signals SMBBLKDAT ready */ 600 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 601 } 602 603 status = i801_wait_intr(priv); 604 exit: 605 return i801_check_post(priv, status); 606 } 607 608 static int i801_set_block_buffer_mode(struct i801_priv *priv) 609 { 610 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv)); 611 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0) 612 return -EIO; 613 return 0; 614 } 615 616 /* Block transaction function */ 617 static int i801_block_transaction(struct i801_priv *priv, 618 union i2c_smbus_data *data, char read_write, 619 int command, int hwpec) 620 { 621 int result = 0; 622 unsigned char hostc; 623 624 if (command == I2C_SMBUS_I2C_BLOCK_DATA) { 625 if (read_write == I2C_SMBUS_WRITE) { 626 /* set I2C_EN bit in configuration register */ 627 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc); 628 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, 629 hostc | SMBHSTCFG_I2C_EN); 630 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) { 631 dev_err(&priv->pci_dev->dev, 632 "I2C block read is unsupported!\n"); 633 return -EOPNOTSUPP; 634 } 635 } 636 637 if (read_write == I2C_SMBUS_WRITE 638 || command == I2C_SMBUS_I2C_BLOCK_DATA) { 639 if (data->block[0] < 1) 640 data->block[0] = 1; 641 if (data->block[0] > I2C_SMBUS_BLOCK_MAX) 642 data->block[0] = I2C_SMBUS_BLOCK_MAX; 643 } else { 644 data->block[0] = 32; /* max for SMBus block reads */ 645 } 646 647 /* Experience has shown that the block buffer can only be used for 648 SMBus (not I2C) block transactions, even though the datasheet 649 doesn't mention this limitation. */ 650 if ((priv->features & FEATURE_BLOCK_BUFFER) 651 && command != I2C_SMBUS_I2C_BLOCK_DATA 652 && i801_set_block_buffer_mode(priv) == 0) 653 result = i801_block_transaction_by_block(priv, data, 654 read_write, hwpec); 655 else 656 result = i801_block_transaction_byte_by_byte(priv, data, 657 read_write, 658 command, hwpec); 659 660 if (command == I2C_SMBUS_I2C_BLOCK_DATA 661 && read_write == I2C_SMBUS_WRITE) { 662 /* restore saved configuration register value */ 663 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc); 664 } 665 return result; 666 } 667 668 /* Return negative errno on error. */ 669 static s32 i801_access(struct i2c_adapter *adap, u16 addr, 670 unsigned short flags, char read_write, u8 command, 671 int size, union i2c_smbus_data *data) 672 { 673 int hwpec; 674 int block = 0; 675 int ret, xact = 0; 676 struct i801_priv *priv = i2c_get_adapdata(adap); 677 678 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) 679 && size != I2C_SMBUS_QUICK 680 && size != I2C_SMBUS_I2C_BLOCK_DATA; 681 682 switch (size) { 683 case I2C_SMBUS_QUICK: 684 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 685 SMBHSTADD(priv)); 686 xact = I801_QUICK; 687 break; 688 case I2C_SMBUS_BYTE: 689 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 690 SMBHSTADD(priv)); 691 if (read_write == I2C_SMBUS_WRITE) 692 outb_p(command, SMBHSTCMD(priv)); 693 xact = I801_BYTE; 694 break; 695 case I2C_SMBUS_BYTE_DATA: 696 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 697 SMBHSTADD(priv)); 698 outb_p(command, SMBHSTCMD(priv)); 699 if (read_write == I2C_SMBUS_WRITE) 700 outb_p(data->byte, SMBHSTDAT0(priv)); 701 xact = I801_BYTE_DATA; 702 break; 703 case I2C_SMBUS_WORD_DATA: 704 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 705 SMBHSTADD(priv)); 706 outb_p(command, SMBHSTCMD(priv)); 707 if (read_write == I2C_SMBUS_WRITE) { 708 outb_p(data->word & 0xff, SMBHSTDAT0(priv)); 709 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); 710 } 711 xact = I801_WORD_DATA; 712 break; 713 case I2C_SMBUS_BLOCK_DATA: 714 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 715 SMBHSTADD(priv)); 716 outb_p(command, SMBHSTCMD(priv)); 717 block = 1; 718 break; 719 case I2C_SMBUS_I2C_BLOCK_DATA: 720 /* NB: page 240 of ICH5 datasheet shows that the R/#W 721 * bit should be cleared here, even when reading */ 722 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv)); 723 if (read_write == I2C_SMBUS_READ) { 724 /* NB: page 240 of ICH5 datasheet also shows 725 * that DATA1 is the cmd field when reading */ 726 outb_p(command, SMBHSTDAT1(priv)); 727 } else 728 outb_p(command, SMBHSTCMD(priv)); 729 block = 1; 730 break; 731 default: 732 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n", 733 size); 734 return -EOPNOTSUPP; 735 } 736 737 if (hwpec) /* enable/disable hardware PEC */ 738 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv)); 739 else 740 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC), 741 SMBAUXCTL(priv)); 742 743 if (block) 744 ret = i801_block_transaction(priv, data, read_write, size, 745 hwpec); 746 else 747 ret = i801_transaction(priv, xact); 748 749 /* Some BIOSes don't like it when PEC is enabled at reboot or resume 750 time, so we forcibly disable it after every transaction. Turn off 751 E32B for the same reason. */ 752 if (hwpec || block) 753 outb_p(inb_p(SMBAUXCTL(priv)) & 754 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 755 756 if (block) 757 return ret; 758 if (ret) 759 return ret; 760 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK)) 761 return 0; 762 763 switch (xact & 0x7f) { 764 case I801_BYTE: /* Result put in SMBHSTDAT0 */ 765 case I801_BYTE_DATA: 766 data->byte = inb_p(SMBHSTDAT0(priv)); 767 break; 768 case I801_WORD_DATA: 769 data->word = inb_p(SMBHSTDAT0(priv)) + 770 (inb_p(SMBHSTDAT1(priv)) << 8); 771 break; 772 } 773 return 0; 774 } 775 776 777 static u32 i801_func(struct i2c_adapter *adapter) 778 { 779 struct i801_priv *priv = i2c_get_adapdata(adapter); 780 781 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 782 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 783 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | 784 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | 785 ((priv->features & FEATURE_I2C_BLOCK_READ) ? 786 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0); 787 } 788 789 static const struct i2c_algorithm smbus_algorithm = { 790 .smbus_xfer = i801_access, 791 .functionality = i801_func, 792 }; 793 794 static const struct pci_device_id i801_ids[] = { 795 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) }, 796 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) }, 797 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) }, 798 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) }, 799 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) }, 800 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) }, 801 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) }, 802 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) }, 803 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) }, 804 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) }, 805 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) }, 806 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) }, 807 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) }, 808 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) }, 809 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) }, 810 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) }, 811 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) }, 812 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) }, 813 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) }, 814 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) }, 815 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) }, 816 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) }, 817 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) }, 818 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) }, 819 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) }, 820 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) }, 821 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) }, 822 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) }, 823 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) }, 824 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) }, 825 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) }, 826 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) }, 827 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) }, 828 { 0, } 829 }; 830 831 MODULE_DEVICE_TABLE(pci, i801_ids); 832 833 #if defined CONFIG_X86 && defined CONFIG_DMI 834 static unsigned char apanel_addr; 835 836 /* Scan the system ROM for the signature "FJKEYINF" */ 837 static __init const void __iomem *bios_signature(const void __iomem *bios) 838 { 839 ssize_t offset; 840 const unsigned char signature[] = "FJKEYINF"; 841 842 for (offset = 0; offset < 0x10000; offset += 0x10) { 843 if (check_signature(bios + offset, signature, 844 sizeof(signature)-1)) 845 return bios + offset; 846 } 847 return NULL; 848 } 849 850 static void __init input_apanel_init(void) 851 { 852 void __iomem *bios; 853 const void __iomem *p; 854 855 bios = ioremap(0xF0000, 0x10000); /* Can't fail */ 856 p = bios_signature(bios); 857 if (p) { 858 /* just use the first address */ 859 apanel_addr = readb(p + 8 + 3) >> 1; 860 } 861 iounmap(bios); 862 } 863 864 struct dmi_onboard_device_info { 865 const char *name; 866 u8 type; 867 unsigned short i2c_addr; 868 const char *i2c_type; 869 }; 870 871 static const struct dmi_onboard_device_info dmi_devices[] = { 872 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" }, 873 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" }, 874 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" }, 875 }; 876 877 static void dmi_check_onboard_device(u8 type, const char *name, 878 struct i2c_adapter *adap) 879 { 880 int i; 881 struct i2c_board_info info; 882 883 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) { 884 /* & ~0x80, ignore enabled/disabled bit */ 885 if ((type & ~0x80) != dmi_devices[i].type) 886 continue; 887 if (strcasecmp(name, dmi_devices[i].name)) 888 continue; 889 890 memset(&info, 0, sizeof(struct i2c_board_info)); 891 info.addr = dmi_devices[i].i2c_addr; 892 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); 893 i2c_new_device(adap, &info); 894 break; 895 } 896 } 897 898 /* We use our own function to check for onboard devices instead of 899 dmi_find_device() as some buggy BIOS's have the devices we are interested 900 in marked as disabled */ 901 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap) 902 { 903 int i, count; 904 905 if (dm->type != 10) 906 return; 907 908 count = (dm->length - sizeof(struct dmi_header)) / 2; 909 for (i = 0; i < count; i++) { 910 const u8 *d = (char *)(dm + 1) + (i * 2); 911 const char *name = ((char *) dm) + dm->length; 912 u8 type = d[0]; 913 u8 s = d[1]; 914 915 if (!s) 916 continue; 917 s--; 918 while (s > 0 && name[0]) { 919 name += strlen(name) + 1; 920 s--; 921 } 922 if (name[0] == 0) /* Bogus string reference */ 923 continue; 924 925 dmi_check_onboard_device(type, name, adap); 926 } 927 } 928 929 /* Register optional slaves */ 930 static void i801_probe_optional_slaves(struct i801_priv *priv) 931 { 932 /* Only register slaves on main SMBus channel */ 933 if (priv->features & FEATURE_IDF) 934 return; 935 936 if (apanel_addr) { 937 struct i2c_board_info info; 938 939 memset(&info, 0, sizeof(struct i2c_board_info)); 940 info.addr = apanel_addr; 941 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE); 942 i2c_new_device(&priv->adapter, &info); 943 } 944 945 if (dmi_name_in_vendors("FUJITSU")) 946 dmi_walk(dmi_check_onboard_devices, &priv->adapter); 947 } 948 #else 949 static void __init input_apanel_init(void) {} 950 static void i801_probe_optional_slaves(struct i801_priv *priv) {} 951 #endif /* CONFIG_X86 && CONFIG_DMI */ 952 953 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \ 954 defined CONFIG_DMI 955 static struct i801_mux_config i801_mux_config_asus_z8_d12 = { 956 .gpio_chip = "gpio_ich", 957 .values = { 0x02, 0x03 }, 958 .n_values = 2, 959 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD }, 960 .gpios = { 52, 53 }, 961 .n_gpios = 2, 962 }; 963 964 static struct i801_mux_config i801_mux_config_asus_z8_d18 = { 965 .gpio_chip = "gpio_ich", 966 .values = { 0x02, 0x03, 0x01 }, 967 .n_values = 3, 968 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD }, 969 .gpios = { 52, 53 }, 970 .n_gpios = 2, 971 }; 972 973 static const struct dmi_system_id mux_dmi_table[] = { 974 { 975 .matches = { 976 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 977 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"), 978 }, 979 .driver_data = &i801_mux_config_asus_z8_d12, 980 }, 981 { 982 .matches = { 983 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 984 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"), 985 }, 986 .driver_data = &i801_mux_config_asus_z8_d12, 987 }, 988 { 989 .matches = { 990 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 991 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"), 992 }, 993 .driver_data = &i801_mux_config_asus_z8_d12, 994 }, 995 { 996 .matches = { 997 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 998 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"), 999 }, 1000 .driver_data = &i801_mux_config_asus_z8_d12, 1001 }, 1002 { 1003 .matches = { 1004 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1005 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"), 1006 }, 1007 .driver_data = &i801_mux_config_asus_z8_d12, 1008 }, 1009 { 1010 .matches = { 1011 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1012 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"), 1013 }, 1014 .driver_data = &i801_mux_config_asus_z8_d12, 1015 }, 1016 { 1017 .matches = { 1018 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1019 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"), 1020 }, 1021 .driver_data = &i801_mux_config_asus_z8_d18, 1022 }, 1023 { 1024 .matches = { 1025 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1026 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"), 1027 }, 1028 .driver_data = &i801_mux_config_asus_z8_d18, 1029 }, 1030 { 1031 .matches = { 1032 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1033 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"), 1034 }, 1035 .driver_data = &i801_mux_config_asus_z8_d12, 1036 }, 1037 { } 1038 }; 1039 1040 /* Setup multiplexing if needed */ 1041 static int i801_add_mux(struct i801_priv *priv) 1042 { 1043 struct device *dev = &priv->adapter.dev; 1044 const struct i801_mux_config *mux_config; 1045 struct i2c_mux_gpio_platform_data gpio_data; 1046 int err; 1047 1048 if (!priv->mux_drvdata) 1049 return 0; 1050 mux_config = priv->mux_drvdata; 1051 1052 /* Prepare the platform data */ 1053 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data)); 1054 gpio_data.parent = priv->adapter.nr; 1055 gpio_data.values = mux_config->values; 1056 gpio_data.n_values = mux_config->n_values; 1057 gpio_data.classes = mux_config->classes; 1058 gpio_data.gpio_chip = mux_config->gpio_chip; 1059 gpio_data.gpios = mux_config->gpios; 1060 gpio_data.n_gpios = mux_config->n_gpios; 1061 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE; 1062 1063 /* Register the mux device */ 1064 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio", 1065 PLATFORM_DEVID_AUTO, &gpio_data, 1066 sizeof(struct i2c_mux_gpio_platform_data)); 1067 if (IS_ERR(priv->mux_pdev)) { 1068 err = PTR_ERR(priv->mux_pdev); 1069 priv->mux_pdev = NULL; 1070 dev_err(dev, "Failed to register i2c-mux-gpio device\n"); 1071 return err; 1072 } 1073 1074 return 0; 1075 } 1076 1077 static void i801_del_mux(struct i801_priv *priv) 1078 { 1079 if (priv->mux_pdev) 1080 platform_device_unregister(priv->mux_pdev); 1081 } 1082 1083 static unsigned int i801_get_adapter_class(struct i801_priv *priv) 1084 { 1085 const struct dmi_system_id *id; 1086 const struct i801_mux_config *mux_config; 1087 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 1088 int i; 1089 1090 id = dmi_first_match(mux_dmi_table); 1091 if (id) { 1092 /* Remove branch classes from trunk */ 1093 mux_config = id->driver_data; 1094 for (i = 0; i < mux_config->n_values; i++) 1095 class &= ~mux_config->classes[i]; 1096 1097 /* Remember for later */ 1098 priv->mux_drvdata = mux_config; 1099 } 1100 1101 return class; 1102 } 1103 #else 1104 static inline int i801_add_mux(struct i801_priv *priv) { return 0; } 1105 static inline void i801_del_mux(struct i801_priv *priv) { } 1106 1107 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv) 1108 { 1109 return I2C_CLASS_HWMON | I2C_CLASS_SPD; 1110 } 1111 #endif 1112 1113 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id) 1114 { 1115 unsigned char temp; 1116 int err, i; 1117 struct i801_priv *priv; 1118 1119 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 1120 if (!priv) 1121 return -ENOMEM; 1122 1123 i2c_set_adapdata(&priv->adapter, priv); 1124 priv->adapter.owner = THIS_MODULE; 1125 priv->adapter.class = i801_get_adapter_class(priv); 1126 priv->adapter.algo = &smbus_algorithm; 1127 1128 priv->pci_dev = dev; 1129 switch (dev->device) { 1130 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0: 1131 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1: 1132 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2: 1133 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0: 1134 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1: 1135 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2: 1136 priv->features |= FEATURE_IDF; 1137 /* fall through */ 1138 default: 1139 priv->features |= FEATURE_I2C_BLOCK_READ; 1140 priv->features |= FEATURE_IRQ; 1141 /* fall through */ 1142 case PCI_DEVICE_ID_INTEL_82801DB_3: 1143 priv->features |= FEATURE_SMBUS_PEC; 1144 priv->features |= FEATURE_BLOCK_BUFFER; 1145 /* fall through */ 1146 case PCI_DEVICE_ID_INTEL_82801CA_3: 1147 case PCI_DEVICE_ID_INTEL_82801BA_2: 1148 case PCI_DEVICE_ID_INTEL_82801AB_3: 1149 case PCI_DEVICE_ID_INTEL_82801AA_3: 1150 break; 1151 } 1152 1153 /* Disable features on user request */ 1154 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) { 1155 if (priv->features & disable_features & (1 << i)) 1156 dev_notice(&dev->dev, "%s disabled by user\n", 1157 i801_feature_names[i]); 1158 } 1159 priv->features &= ~disable_features; 1160 1161 err = pci_enable_device(dev); 1162 if (err) { 1163 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", 1164 err); 1165 goto exit; 1166 } 1167 1168 /* Determine the address of the SMBus area */ 1169 priv->smba = pci_resource_start(dev, SMBBAR); 1170 if (!priv->smba) { 1171 dev_err(&dev->dev, "SMBus base address uninitialized, " 1172 "upgrade BIOS\n"); 1173 err = -ENODEV; 1174 goto exit; 1175 } 1176 1177 err = acpi_check_resource_conflict(&dev->resource[SMBBAR]); 1178 if (err) { 1179 err = -ENODEV; 1180 goto exit; 1181 } 1182 1183 err = pci_request_region(dev, SMBBAR, i801_driver.name); 1184 if (err) { 1185 dev_err(&dev->dev, "Failed to request SMBus region " 1186 "0x%lx-0x%Lx\n", priv->smba, 1187 (unsigned long long)pci_resource_end(dev, SMBBAR)); 1188 goto exit; 1189 } 1190 1191 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp); 1192 priv->original_hstcfg = temp; 1193 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ 1194 if (!(temp & SMBHSTCFG_HST_EN)) { 1195 dev_info(&dev->dev, "Enabling SMBus device\n"); 1196 temp |= SMBHSTCFG_HST_EN; 1197 } 1198 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp); 1199 1200 if (temp & SMBHSTCFG_SMB_SMI_EN) { 1201 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); 1202 /* Disable SMBus interrupt feature if SMBus using SMI# */ 1203 priv->features &= ~FEATURE_IRQ; 1204 } 1205 1206 /* Clear special mode bits */ 1207 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) 1208 outb_p(inb_p(SMBAUXCTL(priv)) & 1209 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 1210 1211 if (priv->features & FEATURE_IRQ) { 1212 init_waitqueue_head(&priv->waitq); 1213 1214 err = request_irq(dev->irq, i801_isr, IRQF_SHARED, 1215 i801_driver.name, priv); 1216 if (err) { 1217 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n", 1218 dev->irq, err); 1219 goto exit_release; 1220 } 1221 dev_info(&dev->dev, "SMBus using PCI Interrupt\n"); 1222 } 1223 1224 /* set up the sysfs linkage to our parent device */ 1225 priv->adapter.dev.parent = &dev->dev; 1226 1227 /* Retry up to 3 times on lost arbitration */ 1228 priv->adapter.retries = 3; 1229 1230 snprintf(priv->adapter.name, sizeof(priv->adapter.name), 1231 "SMBus I801 adapter at %04lx", priv->smba); 1232 err = i2c_add_adapter(&priv->adapter); 1233 if (err) { 1234 dev_err(&dev->dev, "Failed to add SMBus adapter\n"); 1235 goto exit_free_irq; 1236 } 1237 1238 i801_probe_optional_slaves(priv); 1239 /* We ignore errors - multiplexing is optional */ 1240 i801_add_mux(priv); 1241 1242 pci_set_drvdata(dev, priv); 1243 1244 return 0; 1245 1246 exit_free_irq: 1247 if (priv->features & FEATURE_IRQ) 1248 free_irq(dev->irq, priv); 1249 exit_release: 1250 pci_release_region(dev, SMBBAR); 1251 exit: 1252 kfree(priv); 1253 return err; 1254 } 1255 1256 static void i801_remove(struct pci_dev *dev) 1257 { 1258 struct i801_priv *priv = pci_get_drvdata(dev); 1259 1260 i801_del_mux(priv); 1261 i2c_del_adapter(&priv->adapter); 1262 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); 1263 1264 if (priv->features & FEATURE_IRQ) 1265 free_irq(dev->irq, priv); 1266 pci_release_region(dev, SMBBAR); 1267 1268 kfree(priv); 1269 /* 1270 * do not call pci_disable_device(dev) since it can cause hard hangs on 1271 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) 1272 */ 1273 } 1274 1275 #ifdef CONFIG_PM 1276 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg) 1277 { 1278 struct i801_priv *priv = pci_get_drvdata(dev); 1279 1280 pci_save_state(dev); 1281 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); 1282 pci_set_power_state(dev, pci_choose_state(dev, mesg)); 1283 return 0; 1284 } 1285 1286 static int i801_resume(struct pci_dev *dev) 1287 { 1288 pci_set_power_state(dev, PCI_D0); 1289 pci_restore_state(dev); 1290 return pci_enable_device(dev); 1291 } 1292 #else 1293 #define i801_suspend NULL 1294 #define i801_resume NULL 1295 #endif 1296 1297 static struct pci_driver i801_driver = { 1298 .name = "i801_smbus", 1299 .id_table = i801_ids, 1300 .probe = i801_probe, 1301 .remove = i801_remove, 1302 .suspend = i801_suspend, 1303 .resume = i801_resume, 1304 }; 1305 1306 static int __init i2c_i801_init(void) 1307 { 1308 if (dmi_name_in_vendors("FUJITSU")) 1309 input_apanel_init(); 1310 return pci_register_driver(&i801_driver); 1311 } 1312 1313 static void __exit i2c_i801_exit(void) 1314 { 1315 pci_unregister_driver(&i801_driver); 1316 } 1317 1318 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>"); 1319 MODULE_DESCRIPTION("I801 SMBus driver"); 1320 MODULE_LICENSE("GPL"); 1321 1322 module_init(i2c_i801_init); 1323 module_exit(i2c_i801_exit); 1324