1 /* 2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, 3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker 4 <mdsxyz123@yahoo.com> 5 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de> 6 Copyright (C) 2010 Intel Corporation, 7 David Woodhouse <dwmw2@infradead.org> 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 2 of the License, or 12 (at your option) any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 */ 19 20 /* 21 * Supports the following Intel I/O Controller Hubs (ICH): 22 * 23 * I/O Block I2C 24 * region SMBus Block proc. block 25 * Chip name PCI ID size PEC buffer call read 26 * --------------------------------------------------------------------------- 27 * 82801AA (ICH) 0x2413 16 no no no no 28 * 82801AB (ICH0) 0x2423 16 no no no no 29 * 82801BA (ICH2) 0x2443 16 no no no no 30 * 82801CA (ICH3) 0x2483 32 soft no no no 31 * 82801DB (ICH4) 0x24c3 32 hard yes no no 32 * 82801E (ICH5) 0x24d3 32 hard yes yes yes 33 * 6300ESB 0x25a4 32 hard yes yes yes 34 * 82801F (ICH6) 0x266a 32 hard yes yes yes 35 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes 36 * 82801G (ICH7) 0x27da 32 hard yes yes yes 37 * 82801H (ICH8) 0x283e 32 hard yes yes yes 38 * 82801I (ICH9) 0x2930 32 hard yes yes yes 39 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes 40 * ICH10 0x3a30 32 hard yes yes yes 41 * ICH10 0x3a60 32 hard yes yes yes 42 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes 43 * 6 Series (PCH) 0x1c22 32 hard yes yes yes 44 * Patsburg (PCH) 0x1d22 32 hard yes yes yes 45 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes 46 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes 47 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes 48 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes 49 * Panther Point (PCH) 0x1e22 32 hard yes yes yes 50 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes 51 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes 52 * Avoton (SOC) 0x1f3c 32 hard yes yes yes 53 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes 54 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes 55 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes 56 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes 57 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes 58 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes 59 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes 60 * BayTrail (SOC) 0x0f12 32 hard yes yes yes 61 * Braswell (SOC) 0x2292 32 hard yes yes yes 62 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes 63 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes 64 * DNV (SOC) 0x19df 32 hard yes yes yes 65 * Broxton (SOC) 0x5ad4 32 hard yes yes yes 66 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes 67 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes 68 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes 69 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes 70 * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes 71 * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes 72 * Cedar Fork (PCH) 0x18df 32 hard yes yes yes 73 * Ice Lake-LP (PCH) 0x34a3 32 hard yes yes yes 74 * Comet Lake (PCH) 0x02a3 32 hard yes yes yes 75 * 76 * Features supported by this driver: 77 * Software PEC no 78 * Hardware PEC yes 79 * Block buffer yes 80 * Block process call transaction no 81 * I2C block read transaction yes (doesn't use the block buffer) 82 * Slave mode no 83 * SMBus Host Notify yes 84 * Interrupt processing yes 85 * 86 * See the file Documentation/i2c/busses/i2c-i801 for details. 87 */ 88 89 #include <linux/interrupt.h> 90 #include <linux/module.h> 91 #include <linux/pci.h> 92 #include <linux/kernel.h> 93 #include <linux/stddef.h> 94 #include <linux/delay.h> 95 #include <linux/ioport.h> 96 #include <linux/init.h> 97 #include <linux/i2c.h> 98 #include <linux/i2c-smbus.h> 99 #include <linux/acpi.h> 100 #include <linux/io.h> 101 #include <linux/dmi.h> 102 #include <linux/slab.h> 103 #include <linux/wait.h> 104 #include <linux/err.h> 105 #include <linux/platform_device.h> 106 #include <linux/platform_data/itco_wdt.h> 107 #include <linux/pm_runtime.h> 108 109 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 110 #include <linux/gpio.h> 111 #include <linux/platform_data/i2c-mux-gpio.h> 112 #endif 113 114 /* I801 SMBus address offsets */ 115 #define SMBHSTSTS(p) (0 + (p)->smba) 116 #define SMBHSTCNT(p) (2 + (p)->smba) 117 #define SMBHSTCMD(p) (3 + (p)->smba) 118 #define SMBHSTADD(p) (4 + (p)->smba) 119 #define SMBHSTDAT0(p) (5 + (p)->smba) 120 #define SMBHSTDAT1(p) (6 + (p)->smba) 121 #define SMBBLKDAT(p) (7 + (p)->smba) 122 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */ 123 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */ 124 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */ 125 #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */ 126 #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */ 127 #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */ 128 129 /* PCI Address Constants */ 130 #define SMBBAR 4 131 #define SMBPCICTL 0x004 132 #define SMBPCISTS 0x006 133 #define SMBHSTCFG 0x040 134 #define TCOBASE 0x050 135 #define TCOCTL 0x054 136 137 #define ACPIBASE 0x040 138 #define ACPIBASE_SMI_OFF 0x030 139 #define ACPICTRL 0x044 140 #define ACPICTRL_EN 0x080 141 142 #define SBREG_BAR 0x10 143 #define SBREG_SMBCTRL 0xc6000c 144 #define SBREG_SMBCTRL_DNV 0xcf000c 145 146 /* Host status bits for SMBPCISTS */ 147 #define SMBPCISTS_INTS BIT(3) 148 149 /* Control bits for SMBPCICTL */ 150 #define SMBPCICTL_INTDIS BIT(10) 151 152 /* Host configuration bits for SMBHSTCFG */ 153 #define SMBHSTCFG_HST_EN BIT(0) 154 #define SMBHSTCFG_SMB_SMI_EN BIT(1) 155 #define SMBHSTCFG_I2C_EN BIT(2) 156 #define SMBHSTCFG_SPD_WD BIT(4) 157 158 /* TCO configuration bits for TCOCTL */ 159 #define TCOCTL_EN BIT(8) 160 161 /* Auxiliary status register bits, ICH4+ only */ 162 #define SMBAUXSTS_CRCE BIT(0) 163 #define SMBAUXSTS_STCO BIT(1) 164 165 /* Auxiliary control register bits, ICH4+ only */ 166 #define SMBAUXCTL_CRC BIT(0) 167 #define SMBAUXCTL_E32B BIT(1) 168 169 /* Other settings */ 170 #define MAX_RETRIES 400 171 172 /* I801 command constants */ 173 #define I801_QUICK 0x00 174 #define I801_BYTE 0x04 175 #define I801_BYTE_DATA 0x08 176 #define I801_WORD_DATA 0x0C 177 #define I801_PROC_CALL 0x10 /* unimplemented */ 178 #define I801_BLOCK_DATA 0x14 179 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ 180 181 /* I801 Host Control register bits */ 182 #define SMBHSTCNT_INTREN BIT(0) 183 #define SMBHSTCNT_KILL BIT(1) 184 #define SMBHSTCNT_LAST_BYTE BIT(5) 185 #define SMBHSTCNT_START BIT(6) 186 #define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */ 187 188 /* I801 Hosts Status register bits */ 189 #define SMBHSTSTS_BYTE_DONE BIT(7) 190 #define SMBHSTSTS_INUSE_STS BIT(6) 191 #define SMBHSTSTS_SMBALERT_STS BIT(5) 192 #define SMBHSTSTS_FAILED BIT(4) 193 #define SMBHSTSTS_BUS_ERR BIT(3) 194 #define SMBHSTSTS_DEV_ERR BIT(2) 195 #define SMBHSTSTS_INTR BIT(1) 196 #define SMBHSTSTS_HOST_BUSY BIT(0) 197 198 /* Host Notify Status register bits */ 199 #define SMBSLVSTS_HST_NTFY_STS BIT(0) 200 201 /* Host Notify Command register bits */ 202 #define SMBSLVCMD_HST_NTFY_INTREN BIT(0) 203 204 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \ 205 SMBHSTSTS_DEV_ERR) 206 207 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \ 208 STATUS_ERROR_FLAGS) 209 210 /* Older devices have their ID defined in <linux/pci_ids.h> */ 211 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12 212 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df 213 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df 214 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 215 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 216 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */ 217 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70 218 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71 219 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72 220 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 221 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c 222 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292 223 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 224 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0 225 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4 226 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS 0x34a3 227 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 228 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4 229 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 230 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2 231 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22 232 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d 233 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e 234 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f 235 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22 236 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2 237 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23 238 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3 239 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123 240 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3 241 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223 242 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3 243 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323 244 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS 0x02a3 245 246 struct i801_mux_config { 247 char *gpio_chip; 248 unsigned values[3]; 249 int n_values; 250 unsigned classes[3]; 251 unsigned gpios[2]; /* Relative to gpio_chip->base */ 252 int n_gpios; 253 }; 254 255 struct i801_priv { 256 struct i2c_adapter adapter; 257 unsigned long smba; 258 unsigned char original_hstcfg; 259 unsigned char original_slvcmd; 260 struct pci_dev *pci_dev; 261 unsigned int features; 262 263 /* isr processing */ 264 wait_queue_head_t waitq; 265 u8 status; 266 267 /* Command state used by isr for byte-by-byte block transactions */ 268 u8 cmd; 269 bool is_read; 270 int count; 271 int len; 272 u8 *data; 273 274 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 275 const struct i801_mux_config *mux_drvdata; 276 struct platform_device *mux_pdev; 277 #endif 278 struct platform_device *tco_pdev; 279 280 /* 281 * If set to true the host controller registers are reserved for 282 * ACPI AML use. Protected by acpi_lock. 283 */ 284 bool acpi_reserved; 285 struct mutex acpi_lock; 286 }; 287 288 #define FEATURE_SMBUS_PEC BIT(0) 289 #define FEATURE_BLOCK_BUFFER BIT(1) 290 #define FEATURE_BLOCK_PROC BIT(2) 291 #define FEATURE_I2C_BLOCK_READ BIT(3) 292 #define FEATURE_IRQ BIT(4) 293 #define FEATURE_HOST_NOTIFY BIT(5) 294 /* Not really a feature, but it's convenient to handle it as such */ 295 #define FEATURE_IDF BIT(15) 296 #define FEATURE_TCO BIT(16) 297 298 static const char *i801_feature_names[] = { 299 "SMBus PEC", 300 "Block buffer", 301 "Block process call", 302 "I2C block read", 303 "Interrupt", 304 "SMBus Host Notify", 305 }; 306 307 static unsigned int disable_features; 308 module_param(disable_features, uint, S_IRUGO | S_IWUSR); 309 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n" 310 "\t\t 0x01 disable SMBus PEC\n" 311 "\t\t 0x02 disable the block buffer\n" 312 "\t\t 0x08 disable the I2C block read functionality\n" 313 "\t\t 0x10 don't use interrupts\n" 314 "\t\t 0x20 disable SMBus Host Notify "); 315 316 /* Make sure the SMBus host is ready to start transmitting. 317 Return 0 if it is, -EBUSY if it is not. */ 318 static int i801_check_pre(struct i801_priv *priv) 319 { 320 int status; 321 322 status = inb_p(SMBHSTSTS(priv)); 323 if (status & SMBHSTSTS_HOST_BUSY) { 324 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n"); 325 return -EBUSY; 326 } 327 328 status &= STATUS_FLAGS; 329 if (status) { 330 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n", 331 status); 332 outb_p(status, SMBHSTSTS(priv)); 333 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS; 334 if (status) { 335 dev_err(&priv->pci_dev->dev, 336 "Failed clearing status flags (%02x)\n", 337 status); 338 return -EBUSY; 339 } 340 } 341 342 /* 343 * Clear CRC status if needed. 344 * During normal operation, i801_check_post() takes care 345 * of it after every operation. We do it here only in case 346 * the hardware was already in this state when the driver 347 * started. 348 */ 349 if (priv->features & FEATURE_SMBUS_PEC) { 350 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE; 351 if (status) { 352 dev_dbg(&priv->pci_dev->dev, 353 "Clearing aux status flags (%02x)\n", status); 354 outb_p(status, SMBAUXSTS(priv)); 355 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE; 356 if (status) { 357 dev_err(&priv->pci_dev->dev, 358 "Failed clearing aux status flags (%02x)\n", 359 status); 360 return -EBUSY; 361 } 362 } 363 } 364 365 return 0; 366 } 367 368 /* 369 * Convert the status register to an error code, and clear it. 370 * Note that status only contains the bits we want to clear, not the 371 * actual register value. 372 */ 373 static int i801_check_post(struct i801_priv *priv, int status) 374 { 375 int result = 0; 376 377 /* 378 * If the SMBus is still busy, we give up 379 * Note: This timeout condition only happens when using polling 380 * transactions. For interrupt operation, NAK/timeout is indicated by 381 * DEV_ERR. 382 */ 383 if (unlikely(status < 0)) { 384 dev_err(&priv->pci_dev->dev, "Transaction timeout\n"); 385 /* try to stop the current command */ 386 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n"); 387 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL, 388 SMBHSTCNT(priv)); 389 usleep_range(1000, 2000); 390 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL), 391 SMBHSTCNT(priv)); 392 393 /* Check if it worked */ 394 status = inb_p(SMBHSTSTS(priv)); 395 if ((status & SMBHSTSTS_HOST_BUSY) || 396 !(status & SMBHSTSTS_FAILED)) 397 dev_err(&priv->pci_dev->dev, 398 "Failed terminating the transaction\n"); 399 outb_p(STATUS_FLAGS, SMBHSTSTS(priv)); 400 return -ETIMEDOUT; 401 } 402 403 if (status & SMBHSTSTS_FAILED) { 404 result = -EIO; 405 dev_err(&priv->pci_dev->dev, "Transaction failed\n"); 406 } 407 if (status & SMBHSTSTS_DEV_ERR) { 408 /* 409 * This may be a PEC error, check and clear it. 410 * 411 * AUXSTS is handled differently from HSTSTS. 412 * For HSTSTS, i801_isr() or i801_wait_intr() 413 * has already cleared the error bits in hardware, 414 * and we are passed a copy of the original value 415 * in "status". 416 * For AUXSTS, the hardware register is left 417 * for us to handle here. 418 * This is asymmetric, slightly iffy, but safe, 419 * since all this code is serialized and the CRCE 420 * bit is harmless as long as it's cleared before 421 * the next operation. 422 */ 423 if ((priv->features & FEATURE_SMBUS_PEC) && 424 (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) { 425 outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv)); 426 result = -EBADMSG; 427 dev_dbg(&priv->pci_dev->dev, "PEC error\n"); 428 } else { 429 result = -ENXIO; 430 dev_dbg(&priv->pci_dev->dev, "No response\n"); 431 } 432 } 433 if (status & SMBHSTSTS_BUS_ERR) { 434 result = -EAGAIN; 435 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n"); 436 } 437 438 /* Clear status flags except BYTE_DONE, to be cleared by caller */ 439 outb_p(status, SMBHSTSTS(priv)); 440 441 return result; 442 } 443 444 /* Wait for BUSY being cleared and either INTR or an error flag being set */ 445 static int i801_wait_intr(struct i801_priv *priv) 446 { 447 int timeout = 0; 448 int status; 449 450 /* We will always wait for a fraction of a second! */ 451 do { 452 usleep_range(250, 500); 453 status = inb_p(SMBHSTSTS(priv)); 454 } while (((status & SMBHSTSTS_HOST_BUSY) || 455 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) && 456 (timeout++ < MAX_RETRIES)); 457 458 if (timeout > MAX_RETRIES) { 459 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n"); 460 return -ETIMEDOUT; 461 } 462 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR); 463 } 464 465 /* Wait for either BYTE_DONE or an error flag being set */ 466 static int i801_wait_byte_done(struct i801_priv *priv) 467 { 468 int timeout = 0; 469 int status; 470 471 /* We will always wait for a fraction of a second! */ 472 do { 473 usleep_range(250, 500); 474 status = inb_p(SMBHSTSTS(priv)); 475 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) && 476 (timeout++ < MAX_RETRIES)); 477 478 if (timeout > MAX_RETRIES) { 479 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n"); 480 return -ETIMEDOUT; 481 } 482 return status & STATUS_ERROR_FLAGS; 483 } 484 485 static int i801_transaction(struct i801_priv *priv, int xact) 486 { 487 int status; 488 int result; 489 const struct i2c_adapter *adap = &priv->adapter; 490 491 result = i801_check_pre(priv); 492 if (result < 0) 493 return result; 494 495 if (priv->features & FEATURE_IRQ) { 496 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START, 497 SMBHSTCNT(priv)); 498 result = wait_event_timeout(priv->waitq, 499 (status = priv->status), 500 adap->timeout); 501 if (!result) { 502 status = -ETIMEDOUT; 503 dev_warn(&priv->pci_dev->dev, 504 "Timeout waiting for interrupt!\n"); 505 } 506 priv->status = 0; 507 return i801_check_post(priv, status); 508 } 509 510 /* the current contents of SMBHSTCNT can be overwritten, since PEC, 511 * SMBSCMD are passed in xact */ 512 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv)); 513 514 status = i801_wait_intr(priv); 515 return i801_check_post(priv, status); 516 } 517 518 static int i801_block_transaction_by_block(struct i801_priv *priv, 519 union i2c_smbus_data *data, 520 char read_write, int hwpec) 521 { 522 int i, len; 523 int status; 524 525 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ 526 527 /* Use 32-byte buffer to process this transaction */ 528 if (read_write == I2C_SMBUS_WRITE) { 529 len = data->block[0]; 530 outb_p(len, SMBHSTDAT0(priv)); 531 for (i = 0; i < len; i++) 532 outb_p(data->block[i+1], SMBBLKDAT(priv)); 533 } 534 535 status = i801_transaction(priv, I801_BLOCK_DATA | 536 (hwpec ? SMBHSTCNT_PEC_EN : 0)); 537 if (status) 538 return status; 539 540 if (read_write == I2C_SMBUS_READ) { 541 len = inb_p(SMBHSTDAT0(priv)); 542 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) 543 return -EPROTO; 544 545 data->block[0] = len; 546 for (i = 0; i < len; i++) 547 data->block[i + 1] = inb_p(SMBBLKDAT(priv)); 548 } 549 return 0; 550 } 551 552 static void i801_isr_byte_done(struct i801_priv *priv) 553 { 554 if (priv->is_read) { 555 /* For SMBus block reads, length is received with first byte */ 556 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) && 557 (priv->count == 0)) { 558 priv->len = inb_p(SMBHSTDAT0(priv)); 559 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) { 560 dev_err(&priv->pci_dev->dev, 561 "Illegal SMBus block read size %d\n", 562 priv->len); 563 /* FIXME: Recover */ 564 priv->len = I2C_SMBUS_BLOCK_MAX; 565 } else { 566 dev_dbg(&priv->pci_dev->dev, 567 "SMBus block read size is %d\n", 568 priv->len); 569 } 570 priv->data[-1] = priv->len; 571 } 572 573 /* Read next byte */ 574 if (priv->count < priv->len) 575 priv->data[priv->count++] = inb(SMBBLKDAT(priv)); 576 else 577 dev_dbg(&priv->pci_dev->dev, 578 "Discarding extra byte on block read\n"); 579 580 /* Set LAST_BYTE for last byte of read transaction */ 581 if (priv->count == priv->len - 1) 582 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE, 583 SMBHSTCNT(priv)); 584 } else if (priv->count < priv->len - 1) { 585 /* Write next byte, except for IRQ after last byte */ 586 outb_p(priv->data[++priv->count], SMBBLKDAT(priv)); 587 } 588 589 /* Clear BYTE_DONE to continue with next byte */ 590 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 591 } 592 593 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv) 594 { 595 unsigned short addr; 596 597 addr = inb_p(SMBNTFDADD(priv)) >> 1; 598 599 /* 600 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba) 601 * always returns 0. Our current implementation doesn't provide 602 * data, so we just ignore it. 603 */ 604 i2c_handle_smbus_host_notify(&priv->adapter, addr); 605 606 /* clear Host Notify bit and return */ 607 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 608 return IRQ_HANDLED; 609 } 610 611 /* 612 * There are three kinds of interrupts: 613 * 614 * 1) i801 signals transaction completion with one of these interrupts: 615 * INTR - Success 616 * DEV_ERR - Invalid command, NAK or communication timeout 617 * BUS_ERR - SMI# transaction collision 618 * FAILED - transaction was canceled due to a KILL request 619 * When any of these occur, update ->status and wake up the waitq. 620 * ->status must be cleared before kicking off the next transaction. 621 * 622 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt 623 * occurs for each byte of a byte-by-byte to prepare the next byte. 624 * 625 * 3) Host Notify interrupts 626 */ 627 static irqreturn_t i801_isr(int irq, void *dev_id) 628 { 629 struct i801_priv *priv = dev_id; 630 u16 pcists; 631 u8 status; 632 633 /* Confirm this is our interrupt */ 634 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); 635 if (!(pcists & SMBPCISTS_INTS)) 636 return IRQ_NONE; 637 638 if (priv->features & FEATURE_HOST_NOTIFY) { 639 status = inb_p(SMBSLVSTS(priv)); 640 if (status & SMBSLVSTS_HST_NTFY_STS) 641 return i801_host_notify_isr(priv); 642 } 643 644 status = inb_p(SMBHSTSTS(priv)); 645 if (status & SMBHSTSTS_BYTE_DONE) 646 i801_isr_byte_done(priv); 647 648 /* 649 * Clear irq sources and report transaction result. 650 * ->status must be cleared before the next transaction is started. 651 */ 652 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS; 653 if (status) { 654 outb_p(status, SMBHSTSTS(priv)); 655 priv->status = status; 656 wake_up(&priv->waitq); 657 } 658 659 return IRQ_HANDLED; 660 } 661 662 /* 663 * For "byte-by-byte" block transactions: 664 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1 665 * I2C read uses cmd=I801_I2C_BLOCK_DATA 666 */ 667 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, 668 union i2c_smbus_data *data, 669 char read_write, int command, 670 int hwpec) 671 { 672 int i, len; 673 int smbcmd; 674 int status; 675 int result; 676 const struct i2c_adapter *adap = &priv->adapter; 677 678 result = i801_check_pre(priv); 679 if (result < 0) 680 return result; 681 682 len = data->block[0]; 683 684 if (read_write == I2C_SMBUS_WRITE) { 685 outb_p(len, SMBHSTDAT0(priv)); 686 outb_p(data->block[1], SMBBLKDAT(priv)); 687 } 688 689 if (command == I2C_SMBUS_I2C_BLOCK_DATA && 690 read_write == I2C_SMBUS_READ) 691 smbcmd = I801_I2C_BLOCK_DATA; 692 else 693 smbcmd = I801_BLOCK_DATA; 694 695 if (priv->features & FEATURE_IRQ) { 696 priv->is_read = (read_write == I2C_SMBUS_READ); 697 if (len == 1 && priv->is_read) 698 smbcmd |= SMBHSTCNT_LAST_BYTE; 699 priv->cmd = smbcmd | SMBHSTCNT_INTREN; 700 priv->len = len; 701 priv->count = 0; 702 priv->data = &data->block[1]; 703 704 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv)); 705 result = wait_event_timeout(priv->waitq, 706 (status = priv->status), 707 adap->timeout); 708 if (!result) { 709 status = -ETIMEDOUT; 710 dev_warn(&priv->pci_dev->dev, 711 "Timeout waiting for interrupt!\n"); 712 } 713 priv->status = 0; 714 return i801_check_post(priv, status); 715 } 716 717 for (i = 1; i <= len; i++) { 718 if (i == len && read_write == I2C_SMBUS_READ) 719 smbcmd |= SMBHSTCNT_LAST_BYTE; 720 outb_p(smbcmd, SMBHSTCNT(priv)); 721 722 if (i == 1) 723 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START, 724 SMBHSTCNT(priv)); 725 726 status = i801_wait_byte_done(priv); 727 if (status) 728 goto exit; 729 730 if (i == 1 && read_write == I2C_SMBUS_READ 731 && command != I2C_SMBUS_I2C_BLOCK_DATA) { 732 len = inb_p(SMBHSTDAT0(priv)); 733 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { 734 dev_err(&priv->pci_dev->dev, 735 "Illegal SMBus block read size %d\n", 736 len); 737 /* Recover */ 738 while (inb_p(SMBHSTSTS(priv)) & 739 SMBHSTSTS_HOST_BUSY) 740 outb_p(SMBHSTSTS_BYTE_DONE, 741 SMBHSTSTS(priv)); 742 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); 743 return -EPROTO; 744 } 745 data->block[0] = len; 746 } 747 748 /* Retrieve/store value in SMBBLKDAT */ 749 if (read_write == I2C_SMBUS_READ) 750 data->block[i] = inb_p(SMBBLKDAT(priv)); 751 if (read_write == I2C_SMBUS_WRITE && i+1 <= len) 752 outb_p(data->block[i+1], SMBBLKDAT(priv)); 753 754 /* signals SMBBLKDAT ready */ 755 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 756 } 757 758 status = i801_wait_intr(priv); 759 exit: 760 return i801_check_post(priv, status); 761 } 762 763 static int i801_set_block_buffer_mode(struct i801_priv *priv) 764 { 765 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv)); 766 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0) 767 return -EIO; 768 return 0; 769 } 770 771 /* Block transaction function */ 772 static int i801_block_transaction(struct i801_priv *priv, 773 union i2c_smbus_data *data, char read_write, 774 int command, int hwpec) 775 { 776 int result = 0; 777 unsigned char hostc; 778 779 if (command == I2C_SMBUS_I2C_BLOCK_DATA) { 780 if (read_write == I2C_SMBUS_WRITE) { 781 /* set I2C_EN bit in configuration register */ 782 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc); 783 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, 784 hostc | SMBHSTCFG_I2C_EN); 785 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) { 786 dev_err(&priv->pci_dev->dev, 787 "I2C block read is unsupported!\n"); 788 return -EOPNOTSUPP; 789 } 790 } 791 792 if (read_write == I2C_SMBUS_WRITE 793 || command == I2C_SMBUS_I2C_BLOCK_DATA) { 794 if (data->block[0] < 1) 795 data->block[0] = 1; 796 if (data->block[0] > I2C_SMBUS_BLOCK_MAX) 797 data->block[0] = I2C_SMBUS_BLOCK_MAX; 798 } else { 799 data->block[0] = 32; /* max for SMBus block reads */ 800 } 801 802 /* Experience has shown that the block buffer can only be used for 803 SMBus (not I2C) block transactions, even though the datasheet 804 doesn't mention this limitation. */ 805 if ((priv->features & FEATURE_BLOCK_BUFFER) 806 && command != I2C_SMBUS_I2C_BLOCK_DATA 807 && i801_set_block_buffer_mode(priv) == 0) 808 result = i801_block_transaction_by_block(priv, data, 809 read_write, hwpec); 810 else 811 result = i801_block_transaction_byte_by_byte(priv, data, 812 read_write, 813 command, hwpec); 814 815 if (command == I2C_SMBUS_I2C_BLOCK_DATA 816 && read_write == I2C_SMBUS_WRITE) { 817 /* restore saved configuration register value */ 818 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc); 819 } 820 return result; 821 } 822 823 /* Return negative errno on error. */ 824 static s32 i801_access(struct i2c_adapter *adap, u16 addr, 825 unsigned short flags, char read_write, u8 command, 826 int size, union i2c_smbus_data *data) 827 { 828 int hwpec; 829 int block = 0; 830 int ret = 0, xact = 0; 831 struct i801_priv *priv = i2c_get_adapdata(adap); 832 833 mutex_lock(&priv->acpi_lock); 834 if (priv->acpi_reserved) { 835 mutex_unlock(&priv->acpi_lock); 836 return -EBUSY; 837 } 838 839 pm_runtime_get_sync(&priv->pci_dev->dev); 840 841 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) 842 && size != I2C_SMBUS_QUICK 843 && size != I2C_SMBUS_I2C_BLOCK_DATA; 844 845 switch (size) { 846 case I2C_SMBUS_QUICK: 847 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 848 SMBHSTADD(priv)); 849 xact = I801_QUICK; 850 break; 851 case I2C_SMBUS_BYTE: 852 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 853 SMBHSTADD(priv)); 854 if (read_write == I2C_SMBUS_WRITE) 855 outb_p(command, SMBHSTCMD(priv)); 856 xact = I801_BYTE; 857 break; 858 case I2C_SMBUS_BYTE_DATA: 859 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 860 SMBHSTADD(priv)); 861 outb_p(command, SMBHSTCMD(priv)); 862 if (read_write == I2C_SMBUS_WRITE) 863 outb_p(data->byte, SMBHSTDAT0(priv)); 864 xact = I801_BYTE_DATA; 865 break; 866 case I2C_SMBUS_WORD_DATA: 867 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 868 SMBHSTADD(priv)); 869 outb_p(command, SMBHSTCMD(priv)); 870 if (read_write == I2C_SMBUS_WRITE) { 871 outb_p(data->word & 0xff, SMBHSTDAT0(priv)); 872 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); 873 } 874 xact = I801_WORD_DATA; 875 break; 876 case I2C_SMBUS_BLOCK_DATA: 877 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 878 SMBHSTADD(priv)); 879 outb_p(command, SMBHSTCMD(priv)); 880 block = 1; 881 break; 882 case I2C_SMBUS_I2C_BLOCK_DATA: 883 /* 884 * NB: page 240 of ICH5 datasheet shows that the R/#W 885 * bit should be cleared here, even when reading. 886 * However if SPD Write Disable is set (Lynx Point and later), 887 * the read will fail if we don't set the R/#W bit. 888 */ 889 outb_p(((addr & 0x7f) << 1) | 890 ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ? 891 (read_write & 0x01) : 0), 892 SMBHSTADD(priv)); 893 if (read_write == I2C_SMBUS_READ) { 894 /* NB: page 240 of ICH5 datasheet also shows 895 * that DATA1 is the cmd field when reading */ 896 outb_p(command, SMBHSTDAT1(priv)); 897 } else 898 outb_p(command, SMBHSTCMD(priv)); 899 block = 1; 900 break; 901 default: 902 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n", 903 size); 904 ret = -EOPNOTSUPP; 905 goto out; 906 } 907 908 if (hwpec) /* enable/disable hardware PEC */ 909 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv)); 910 else 911 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC), 912 SMBAUXCTL(priv)); 913 914 if (block) 915 ret = i801_block_transaction(priv, data, read_write, size, 916 hwpec); 917 else 918 ret = i801_transaction(priv, xact); 919 920 /* Some BIOSes don't like it when PEC is enabled at reboot or resume 921 time, so we forcibly disable it after every transaction. Turn off 922 E32B for the same reason. */ 923 if (hwpec || block) 924 outb_p(inb_p(SMBAUXCTL(priv)) & 925 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 926 927 if (block) 928 goto out; 929 if (ret) 930 goto out; 931 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK)) 932 goto out; 933 934 switch (xact & 0x7f) { 935 case I801_BYTE: /* Result put in SMBHSTDAT0 */ 936 case I801_BYTE_DATA: 937 data->byte = inb_p(SMBHSTDAT0(priv)); 938 break; 939 case I801_WORD_DATA: 940 data->word = inb_p(SMBHSTDAT0(priv)) + 941 (inb_p(SMBHSTDAT1(priv)) << 8); 942 break; 943 } 944 945 out: 946 pm_runtime_mark_last_busy(&priv->pci_dev->dev); 947 pm_runtime_put_autosuspend(&priv->pci_dev->dev); 948 mutex_unlock(&priv->acpi_lock); 949 return ret; 950 } 951 952 953 static u32 i801_func(struct i2c_adapter *adapter) 954 { 955 struct i801_priv *priv = i2c_get_adapdata(adapter); 956 957 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 958 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 959 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | 960 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | 961 ((priv->features & FEATURE_I2C_BLOCK_READ) ? 962 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) | 963 ((priv->features & FEATURE_HOST_NOTIFY) ? 964 I2C_FUNC_SMBUS_HOST_NOTIFY : 0); 965 } 966 967 static void i801_enable_host_notify(struct i2c_adapter *adapter) 968 { 969 struct i801_priv *priv = i2c_get_adapdata(adapter); 970 971 if (!(priv->features & FEATURE_HOST_NOTIFY)) 972 return; 973 974 if (!(SMBSLVCMD_HST_NTFY_INTREN & priv->original_slvcmd)) 975 outb_p(SMBSLVCMD_HST_NTFY_INTREN | priv->original_slvcmd, 976 SMBSLVCMD(priv)); 977 978 /* clear Host Notify bit to allow a new notification */ 979 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 980 } 981 982 static void i801_disable_host_notify(struct i801_priv *priv) 983 { 984 if (!(priv->features & FEATURE_HOST_NOTIFY)) 985 return; 986 987 outb_p(priv->original_slvcmd, SMBSLVCMD(priv)); 988 } 989 990 static const struct i2c_algorithm smbus_algorithm = { 991 .smbus_xfer = i801_access, 992 .functionality = i801_func, 993 }; 994 995 static const struct pci_device_id i801_ids[] = { 996 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) }, 997 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) }, 998 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) }, 999 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) }, 1000 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) }, 1001 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) }, 1002 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) }, 1003 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) }, 1004 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) }, 1005 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) }, 1006 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) }, 1007 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) }, 1008 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) }, 1009 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) }, 1010 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) }, 1011 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) }, 1012 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) }, 1013 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) }, 1014 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) }, 1015 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) }, 1016 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) }, 1017 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) }, 1018 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) }, 1019 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) }, 1020 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) }, 1021 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) }, 1022 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) }, 1023 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) }, 1024 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) }, 1025 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) }, 1026 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) }, 1027 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS) }, 1028 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) }, 1029 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) }, 1030 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) }, 1031 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) }, 1032 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) }, 1033 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) }, 1034 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMBUS) }, 1035 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) }, 1036 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) }, 1037 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) }, 1038 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) }, 1039 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) }, 1040 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS) }, 1041 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS) }, 1042 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS) }, 1043 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS) }, 1044 { 0, } 1045 }; 1046 1047 MODULE_DEVICE_TABLE(pci, i801_ids); 1048 1049 #if defined CONFIG_X86 && defined CONFIG_DMI 1050 static unsigned char apanel_addr; 1051 1052 /* Scan the system ROM for the signature "FJKEYINF" */ 1053 static __init const void __iomem *bios_signature(const void __iomem *bios) 1054 { 1055 ssize_t offset; 1056 const unsigned char signature[] = "FJKEYINF"; 1057 1058 for (offset = 0; offset < 0x10000; offset += 0x10) { 1059 if (check_signature(bios + offset, signature, 1060 sizeof(signature)-1)) 1061 return bios + offset; 1062 } 1063 return NULL; 1064 } 1065 1066 static void __init input_apanel_init(void) 1067 { 1068 void __iomem *bios; 1069 const void __iomem *p; 1070 1071 bios = ioremap(0xF0000, 0x10000); /* Can't fail */ 1072 p = bios_signature(bios); 1073 if (p) { 1074 /* just use the first address */ 1075 apanel_addr = readb(p + 8 + 3) >> 1; 1076 } 1077 iounmap(bios); 1078 } 1079 1080 struct dmi_onboard_device_info { 1081 const char *name; 1082 u8 type; 1083 unsigned short i2c_addr; 1084 const char *i2c_type; 1085 }; 1086 1087 static const struct dmi_onboard_device_info dmi_devices[] = { 1088 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" }, 1089 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" }, 1090 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" }, 1091 }; 1092 1093 static void dmi_check_onboard_device(u8 type, const char *name, 1094 struct i2c_adapter *adap) 1095 { 1096 int i; 1097 struct i2c_board_info info; 1098 1099 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) { 1100 /* & ~0x80, ignore enabled/disabled bit */ 1101 if ((type & ~0x80) != dmi_devices[i].type) 1102 continue; 1103 if (strcasecmp(name, dmi_devices[i].name)) 1104 continue; 1105 1106 memset(&info, 0, sizeof(struct i2c_board_info)); 1107 info.addr = dmi_devices[i].i2c_addr; 1108 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); 1109 i2c_new_device(adap, &info); 1110 break; 1111 } 1112 } 1113 1114 /* We use our own function to check for onboard devices instead of 1115 dmi_find_device() as some buggy BIOS's have the devices we are interested 1116 in marked as disabled */ 1117 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap) 1118 { 1119 int i, count; 1120 1121 if (dm->type != 10) 1122 return; 1123 1124 count = (dm->length - sizeof(struct dmi_header)) / 2; 1125 for (i = 0; i < count; i++) { 1126 const u8 *d = (char *)(dm + 1) + (i * 2); 1127 const char *name = ((char *) dm) + dm->length; 1128 u8 type = d[0]; 1129 u8 s = d[1]; 1130 1131 if (!s) 1132 continue; 1133 s--; 1134 while (s > 0 && name[0]) { 1135 name += strlen(name) + 1; 1136 s--; 1137 } 1138 if (name[0] == 0) /* Bogus string reference */ 1139 continue; 1140 1141 dmi_check_onboard_device(type, name, adap); 1142 } 1143 } 1144 1145 /* Register optional slaves */ 1146 static void i801_probe_optional_slaves(struct i801_priv *priv) 1147 { 1148 /* Only register slaves on main SMBus channel */ 1149 if (priv->features & FEATURE_IDF) 1150 return; 1151 1152 if (apanel_addr) { 1153 struct i2c_board_info info; 1154 1155 memset(&info, 0, sizeof(struct i2c_board_info)); 1156 info.addr = apanel_addr; 1157 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE); 1158 i2c_new_device(&priv->adapter, &info); 1159 } 1160 1161 if (dmi_name_in_vendors("FUJITSU")) 1162 dmi_walk(dmi_check_onboard_devices, &priv->adapter); 1163 } 1164 #else 1165 static void __init input_apanel_init(void) {} 1166 static void i801_probe_optional_slaves(struct i801_priv *priv) {} 1167 #endif /* CONFIG_X86 && CONFIG_DMI */ 1168 1169 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 1170 static struct i801_mux_config i801_mux_config_asus_z8_d12 = { 1171 .gpio_chip = "gpio_ich", 1172 .values = { 0x02, 0x03 }, 1173 .n_values = 2, 1174 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD }, 1175 .gpios = { 52, 53 }, 1176 .n_gpios = 2, 1177 }; 1178 1179 static struct i801_mux_config i801_mux_config_asus_z8_d18 = { 1180 .gpio_chip = "gpio_ich", 1181 .values = { 0x02, 0x03, 0x01 }, 1182 .n_values = 3, 1183 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD }, 1184 .gpios = { 52, 53 }, 1185 .n_gpios = 2, 1186 }; 1187 1188 static const struct dmi_system_id mux_dmi_table[] = { 1189 { 1190 .matches = { 1191 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1192 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"), 1193 }, 1194 .driver_data = &i801_mux_config_asus_z8_d12, 1195 }, 1196 { 1197 .matches = { 1198 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1199 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"), 1200 }, 1201 .driver_data = &i801_mux_config_asus_z8_d12, 1202 }, 1203 { 1204 .matches = { 1205 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1206 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"), 1207 }, 1208 .driver_data = &i801_mux_config_asus_z8_d12, 1209 }, 1210 { 1211 .matches = { 1212 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1213 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"), 1214 }, 1215 .driver_data = &i801_mux_config_asus_z8_d12, 1216 }, 1217 { 1218 .matches = { 1219 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1220 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"), 1221 }, 1222 .driver_data = &i801_mux_config_asus_z8_d12, 1223 }, 1224 { 1225 .matches = { 1226 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1227 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"), 1228 }, 1229 .driver_data = &i801_mux_config_asus_z8_d12, 1230 }, 1231 { 1232 .matches = { 1233 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1234 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"), 1235 }, 1236 .driver_data = &i801_mux_config_asus_z8_d18, 1237 }, 1238 { 1239 .matches = { 1240 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1241 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"), 1242 }, 1243 .driver_data = &i801_mux_config_asus_z8_d18, 1244 }, 1245 { 1246 .matches = { 1247 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1248 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"), 1249 }, 1250 .driver_data = &i801_mux_config_asus_z8_d12, 1251 }, 1252 { } 1253 }; 1254 1255 /* Setup multiplexing if needed */ 1256 static int i801_add_mux(struct i801_priv *priv) 1257 { 1258 struct device *dev = &priv->adapter.dev; 1259 const struct i801_mux_config *mux_config; 1260 struct i2c_mux_gpio_platform_data gpio_data; 1261 int err; 1262 1263 if (!priv->mux_drvdata) 1264 return 0; 1265 mux_config = priv->mux_drvdata; 1266 1267 /* Prepare the platform data */ 1268 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data)); 1269 gpio_data.parent = priv->adapter.nr; 1270 gpio_data.values = mux_config->values; 1271 gpio_data.n_values = mux_config->n_values; 1272 gpio_data.classes = mux_config->classes; 1273 gpio_data.gpio_chip = mux_config->gpio_chip; 1274 gpio_data.gpios = mux_config->gpios; 1275 gpio_data.n_gpios = mux_config->n_gpios; 1276 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE; 1277 1278 /* Register the mux device */ 1279 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio", 1280 PLATFORM_DEVID_AUTO, &gpio_data, 1281 sizeof(struct i2c_mux_gpio_platform_data)); 1282 if (IS_ERR(priv->mux_pdev)) { 1283 err = PTR_ERR(priv->mux_pdev); 1284 priv->mux_pdev = NULL; 1285 dev_err(dev, "Failed to register i2c-mux-gpio device\n"); 1286 return err; 1287 } 1288 1289 return 0; 1290 } 1291 1292 static void i801_del_mux(struct i801_priv *priv) 1293 { 1294 if (priv->mux_pdev) 1295 platform_device_unregister(priv->mux_pdev); 1296 } 1297 1298 static unsigned int i801_get_adapter_class(struct i801_priv *priv) 1299 { 1300 const struct dmi_system_id *id; 1301 const struct i801_mux_config *mux_config; 1302 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 1303 int i; 1304 1305 id = dmi_first_match(mux_dmi_table); 1306 if (id) { 1307 /* Remove branch classes from trunk */ 1308 mux_config = id->driver_data; 1309 for (i = 0; i < mux_config->n_values; i++) 1310 class &= ~mux_config->classes[i]; 1311 1312 /* Remember for later */ 1313 priv->mux_drvdata = mux_config; 1314 } 1315 1316 return class; 1317 } 1318 #else 1319 static inline int i801_add_mux(struct i801_priv *priv) { return 0; } 1320 static inline void i801_del_mux(struct i801_priv *priv) { } 1321 1322 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv) 1323 { 1324 return I2C_CLASS_HWMON | I2C_CLASS_SPD; 1325 } 1326 #endif 1327 1328 static const struct itco_wdt_platform_data tco_platform_data = { 1329 .name = "Intel PCH", 1330 .version = 4, 1331 }; 1332 1333 static DEFINE_SPINLOCK(p2sb_spinlock); 1334 1335 static void i801_add_tco(struct i801_priv *priv) 1336 { 1337 struct pci_dev *pci_dev = priv->pci_dev; 1338 struct resource tco_res[3], *res; 1339 struct platform_device *pdev; 1340 unsigned int devfn; 1341 u32 tco_base, tco_ctl; 1342 u32 base_addr, ctrl_val; 1343 u64 base64_addr; 1344 u8 hidden; 1345 1346 if (!(priv->features & FEATURE_TCO)) 1347 return; 1348 1349 pci_read_config_dword(pci_dev, TCOBASE, &tco_base); 1350 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl); 1351 if (!(tco_ctl & TCOCTL_EN)) 1352 return; 1353 1354 memset(tco_res, 0, sizeof(tco_res)); 1355 1356 res = &tco_res[ICH_RES_IO_TCO]; 1357 res->start = tco_base & ~1; 1358 res->end = res->start + 32 - 1; 1359 res->flags = IORESOURCE_IO; 1360 1361 /* 1362 * Power Management registers. 1363 */ 1364 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 2); 1365 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPIBASE, &base_addr); 1366 1367 res = &tco_res[ICH_RES_IO_SMI]; 1368 res->start = (base_addr & ~1) + ACPIBASE_SMI_OFF; 1369 res->end = res->start + 3; 1370 res->flags = IORESOURCE_IO; 1371 1372 /* 1373 * Enable the ACPI I/O space. 1374 */ 1375 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPICTRL, &ctrl_val); 1376 ctrl_val |= ACPICTRL_EN; 1377 pci_bus_write_config_dword(pci_dev->bus, devfn, ACPICTRL, ctrl_val); 1378 1379 /* 1380 * We must access the NO_REBOOT bit over the Primary to Sideband 1381 * bridge (P2SB). The BIOS prevents the P2SB device from being 1382 * enumerated by the PCI subsystem, so we need to unhide/hide it 1383 * to lookup the P2SB BAR. 1384 */ 1385 spin_lock(&p2sb_spinlock); 1386 1387 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1); 1388 1389 /* Unhide the P2SB device, if it is hidden */ 1390 pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden); 1391 if (hidden) 1392 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0); 1393 1394 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr); 1395 base64_addr = base_addr & 0xfffffff0; 1396 1397 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr); 1398 base64_addr |= (u64)base_addr << 32; 1399 1400 /* Hide the P2SB device, if it was hidden before */ 1401 if (hidden) 1402 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden); 1403 spin_unlock(&p2sb_spinlock); 1404 1405 res = &tco_res[ICH_RES_MEM_OFF]; 1406 if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS) 1407 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV; 1408 else 1409 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL; 1410 1411 res->end = res->start + 3; 1412 res->flags = IORESOURCE_MEM; 1413 1414 pdev = platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1, 1415 tco_res, 3, &tco_platform_data, 1416 sizeof(tco_platform_data)); 1417 if (IS_ERR(pdev)) { 1418 dev_warn(&pci_dev->dev, "failed to create iTCO device\n"); 1419 return; 1420 } 1421 1422 priv->tco_pdev = pdev; 1423 } 1424 1425 #ifdef CONFIG_ACPI 1426 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv, 1427 acpi_physical_address address) 1428 { 1429 return address >= priv->smba && 1430 address <= pci_resource_end(priv->pci_dev, SMBBAR); 1431 } 1432 1433 static acpi_status 1434 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits, 1435 u64 *value, void *handler_context, void *region_context) 1436 { 1437 struct i801_priv *priv = handler_context; 1438 struct pci_dev *pdev = priv->pci_dev; 1439 acpi_status status; 1440 1441 /* 1442 * Once BIOS AML code touches the OpRegion we warn and inhibit any 1443 * further access from the driver itself. This device is now owned 1444 * by the system firmware. 1445 */ 1446 mutex_lock(&priv->acpi_lock); 1447 1448 if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) { 1449 priv->acpi_reserved = true; 1450 1451 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n"); 1452 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n"); 1453 1454 /* 1455 * BIOS is accessing the host controller so prevent it from 1456 * suspending automatically from now on. 1457 */ 1458 pm_runtime_get_sync(&pdev->dev); 1459 } 1460 1461 if ((function & ACPI_IO_MASK) == ACPI_READ) 1462 status = acpi_os_read_port(address, (u32 *)value, bits); 1463 else 1464 status = acpi_os_write_port(address, (u32)*value, bits); 1465 1466 mutex_unlock(&priv->acpi_lock); 1467 1468 return status; 1469 } 1470 1471 static int i801_acpi_probe(struct i801_priv *priv) 1472 { 1473 struct acpi_device *adev; 1474 acpi_status status; 1475 1476 adev = ACPI_COMPANION(&priv->pci_dev->dev); 1477 if (adev) { 1478 status = acpi_install_address_space_handler(adev->handle, 1479 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler, 1480 NULL, priv); 1481 if (ACPI_SUCCESS(status)) 1482 return 0; 1483 } 1484 1485 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]); 1486 } 1487 1488 static void i801_acpi_remove(struct i801_priv *priv) 1489 { 1490 struct acpi_device *adev; 1491 1492 adev = ACPI_COMPANION(&priv->pci_dev->dev); 1493 if (!adev) 1494 return; 1495 1496 acpi_remove_address_space_handler(adev->handle, 1497 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler); 1498 1499 mutex_lock(&priv->acpi_lock); 1500 if (priv->acpi_reserved) 1501 pm_runtime_put(&priv->pci_dev->dev); 1502 mutex_unlock(&priv->acpi_lock); 1503 } 1504 #else 1505 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; } 1506 static inline void i801_acpi_remove(struct i801_priv *priv) { } 1507 #endif 1508 1509 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id) 1510 { 1511 unsigned char temp; 1512 int err, i; 1513 struct i801_priv *priv; 1514 1515 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL); 1516 if (!priv) 1517 return -ENOMEM; 1518 1519 i2c_set_adapdata(&priv->adapter, priv); 1520 priv->adapter.owner = THIS_MODULE; 1521 priv->adapter.class = i801_get_adapter_class(priv); 1522 priv->adapter.algo = &smbus_algorithm; 1523 priv->adapter.dev.parent = &dev->dev; 1524 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev)); 1525 priv->adapter.retries = 3; 1526 mutex_init(&priv->acpi_lock); 1527 1528 priv->pci_dev = dev; 1529 switch (dev->device) { 1530 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS: 1531 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS: 1532 case PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS: 1533 case PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS: 1534 case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS: 1535 case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS: 1536 case PCI_DEVICE_ID_INTEL_CDF_SMBUS: 1537 case PCI_DEVICE_ID_INTEL_DNV_SMBUS: 1538 case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS: 1539 case PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS: 1540 case PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS: 1541 priv->features |= FEATURE_I2C_BLOCK_READ; 1542 priv->features |= FEATURE_IRQ; 1543 priv->features |= FEATURE_SMBUS_PEC; 1544 priv->features |= FEATURE_BLOCK_BUFFER; 1545 /* If we have ACPI based watchdog use that instead */ 1546 if (!acpi_has_watchdog()) 1547 priv->features |= FEATURE_TCO; 1548 priv->features |= FEATURE_HOST_NOTIFY; 1549 break; 1550 1551 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0: 1552 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1: 1553 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2: 1554 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0: 1555 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1: 1556 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2: 1557 priv->features |= FEATURE_IDF; 1558 /* fall through */ 1559 default: 1560 priv->features |= FEATURE_I2C_BLOCK_READ; 1561 priv->features |= FEATURE_IRQ; 1562 /* fall through */ 1563 case PCI_DEVICE_ID_INTEL_82801DB_3: 1564 priv->features |= FEATURE_SMBUS_PEC; 1565 priv->features |= FEATURE_BLOCK_BUFFER; 1566 /* fall through */ 1567 case PCI_DEVICE_ID_INTEL_82801CA_3: 1568 priv->features |= FEATURE_HOST_NOTIFY; 1569 /* fall through */ 1570 case PCI_DEVICE_ID_INTEL_82801BA_2: 1571 case PCI_DEVICE_ID_INTEL_82801AB_3: 1572 case PCI_DEVICE_ID_INTEL_82801AA_3: 1573 break; 1574 } 1575 1576 /* Disable features on user request */ 1577 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) { 1578 if (priv->features & disable_features & (1 << i)) 1579 dev_notice(&dev->dev, "%s disabled by user\n", 1580 i801_feature_names[i]); 1581 } 1582 priv->features &= ~disable_features; 1583 1584 err = pcim_enable_device(dev); 1585 if (err) { 1586 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", 1587 err); 1588 return err; 1589 } 1590 pcim_pin_device(dev); 1591 1592 /* Determine the address of the SMBus area */ 1593 priv->smba = pci_resource_start(dev, SMBBAR); 1594 if (!priv->smba) { 1595 dev_err(&dev->dev, 1596 "SMBus base address uninitialized, upgrade BIOS\n"); 1597 return -ENODEV; 1598 } 1599 1600 if (i801_acpi_probe(priv)) 1601 return -ENODEV; 1602 1603 err = pcim_iomap_regions(dev, 1 << SMBBAR, 1604 dev_driver_string(&dev->dev)); 1605 if (err) { 1606 dev_err(&dev->dev, 1607 "Failed to request SMBus region 0x%lx-0x%Lx\n", 1608 priv->smba, 1609 (unsigned long long)pci_resource_end(dev, SMBBAR)); 1610 i801_acpi_remove(priv); 1611 return err; 1612 } 1613 1614 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp); 1615 priv->original_hstcfg = temp; 1616 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ 1617 if (!(temp & SMBHSTCFG_HST_EN)) { 1618 dev_info(&dev->dev, "Enabling SMBus device\n"); 1619 temp |= SMBHSTCFG_HST_EN; 1620 } 1621 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp); 1622 1623 if (temp & SMBHSTCFG_SMB_SMI_EN) { 1624 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); 1625 /* Disable SMBus interrupt feature if SMBus using SMI# */ 1626 priv->features &= ~FEATURE_IRQ; 1627 } 1628 if (temp & SMBHSTCFG_SPD_WD) 1629 dev_info(&dev->dev, "SPD Write Disable is set\n"); 1630 1631 /* Clear special mode bits */ 1632 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) 1633 outb_p(inb_p(SMBAUXCTL(priv)) & 1634 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 1635 1636 /* Remember original Host Notify setting */ 1637 if (priv->features & FEATURE_HOST_NOTIFY) 1638 priv->original_slvcmd = inb_p(SMBSLVCMD(priv)); 1639 1640 /* Default timeout in interrupt mode: 200 ms */ 1641 priv->adapter.timeout = HZ / 5; 1642 1643 if (dev->irq == IRQ_NOTCONNECTED) 1644 priv->features &= ~FEATURE_IRQ; 1645 1646 if (priv->features & FEATURE_IRQ) { 1647 u16 pcictl, pcists; 1648 1649 /* Complain if an interrupt is already pending */ 1650 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); 1651 if (pcists & SMBPCISTS_INTS) 1652 dev_warn(&dev->dev, "An interrupt is pending!\n"); 1653 1654 /* Check if interrupts have been disabled */ 1655 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl); 1656 if (pcictl & SMBPCICTL_INTDIS) { 1657 dev_info(&dev->dev, "Interrupts are disabled\n"); 1658 priv->features &= ~FEATURE_IRQ; 1659 } 1660 } 1661 1662 if (priv->features & FEATURE_IRQ) { 1663 init_waitqueue_head(&priv->waitq); 1664 1665 err = devm_request_irq(&dev->dev, dev->irq, i801_isr, 1666 IRQF_SHARED, 1667 dev_driver_string(&dev->dev), priv); 1668 if (err) { 1669 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n", 1670 dev->irq, err); 1671 priv->features &= ~FEATURE_IRQ; 1672 } 1673 } 1674 dev_info(&dev->dev, "SMBus using %s\n", 1675 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling"); 1676 1677 i801_add_tco(priv); 1678 1679 snprintf(priv->adapter.name, sizeof(priv->adapter.name), 1680 "SMBus I801 adapter at %04lx", priv->smba); 1681 err = i2c_add_adapter(&priv->adapter); 1682 if (err) { 1683 i801_acpi_remove(priv); 1684 return err; 1685 } 1686 1687 i801_enable_host_notify(&priv->adapter); 1688 1689 i801_probe_optional_slaves(priv); 1690 /* We ignore errors - multiplexing is optional */ 1691 i801_add_mux(priv); 1692 1693 pci_set_drvdata(dev, priv); 1694 1695 pm_runtime_set_autosuspend_delay(&dev->dev, 1000); 1696 pm_runtime_use_autosuspend(&dev->dev); 1697 pm_runtime_put_autosuspend(&dev->dev); 1698 pm_runtime_allow(&dev->dev); 1699 1700 return 0; 1701 } 1702 1703 static void i801_remove(struct pci_dev *dev) 1704 { 1705 struct i801_priv *priv = pci_get_drvdata(dev); 1706 1707 pm_runtime_forbid(&dev->dev); 1708 pm_runtime_get_noresume(&dev->dev); 1709 1710 i801_disable_host_notify(priv); 1711 i801_del_mux(priv); 1712 i2c_del_adapter(&priv->adapter); 1713 i801_acpi_remove(priv); 1714 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); 1715 1716 platform_device_unregister(priv->tco_pdev); 1717 1718 /* 1719 * do not call pci_disable_device(dev) since it can cause hard hangs on 1720 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) 1721 */ 1722 } 1723 1724 static void i801_shutdown(struct pci_dev *dev) 1725 { 1726 struct i801_priv *priv = pci_get_drvdata(dev); 1727 1728 /* Restore config registers to avoid hard hang on some systems */ 1729 i801_disable_host_notify(priv); 1730 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); 1731 } 1732 1733 #ifdef CONFIG_PM_SLEEP 1734 static int i801_suspend(struct device *dev) 1735 { 1736 struct pci_dev *pci_dev = to_pci_dev(dev); 1737 struct i801_priv *priv = pci_get_drvdata(pci_dev); 1738 1739 pci_write_config_byte(pci_dev, SMBHSTCFG, priv->original_hstcfg); 1740 return 0; 1741 } 1742 1743 static int i801_resume(struct device *dev) 1744 { 1745 struct pci_dev *pci_dev = to_pci_dev(dev); 1746 struct i801_priv *priv = pci_get_drvdata(pci_dev); 1747 1748 i801_enable_host_notify(&priv->adapter); 1749 1750 return 0; 1751 } 1752 #endif 1753 1754 static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume); 1755 1756 static struct pci_driver i801_driver = { 1757 .name = "i801_smbus", 1758 .id_table = i801_ids, 1759 .probe = i801_probe, 1760 .remove = i801_remove, 1761 .shutdown = i801_shutdown, 1762 .driver = { 1763 .pm = &i801_pm_ops, 1764 }, 1765 }; 1766 1767 static int __init i2c_i801_init(void) 1768 { 1769 if (dmi_name_in_vendors("FUJITSU")) 1770 input_apanel_init(); 1771 return pci_register_driver(&i801_driver); 1772 } 1773 1774 static void __exit i2c_i801_exit(void) 1775 { 1776 pci_unregister_driver(&i801_driver); 1777 } 1778 1779 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>"); 1780 MODULE_DESCRIPTION("I801 SMBus driver"); 1781 MODULE_LICENSE("GPL"); 1782 1783 module_init(i2c_i801_init); 1784 module_exit(i2c_i801_exit); 1785