1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, 4 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker 5 <mdsxyz123@yahoo.com> 6 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de> 7 Copyright (C) 2010 Intel Corporation, 8 David Woodhouse <dwmw2@infradead.org> 9 10 */ 11 12 /* 13 * Supports the following Intel I/O Controller Hubs (ICH): 14 * 15 * I/O Block I2C 16 * region SMBus Block proc. block 17 * Chip name PCI ID size PEC buffer call read 18 * --------------------------------------------------------------------------- 19 * 82801AA (ICH) 0x2413 16 no no no no 20 * 82801AB (ICH0) 0x2423 16 no no no no 21 * 82801BA (ICH2) 0x2443 16 no no no no 22 * 82801CA (ICH3) 0x2483 32 soft no no no 23 * 82801DB (ICH4) 0x24c3 32 hard yes no no 24 * 82801E (ICH5) 0x24d3 32 hard yes yes yes 25 * 6300ESB 0x25a4 32 hard yes yes yes 26 * 82801F (ICH6) 0x266a 32 hard yes yes yes 27 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes 28 * 82801G (ICH7) 0x27da 32 hard yes yes yes 29 * 82801H (ICH8) 0x283e 32 hard yes yes yes 30 * 82801I (ICH9) 0x2930 32 hard yes yes yes 31 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes 32 * ICH10 0x3a30 32 hard yes yes yes 33 * ICH10 0x3a60 32 hard yes yes yes 34 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes 35 * 6 Series (PCH) 0x1c22 32 hard yes yes yes 36 * Patsburg (PCH) 0x1d22 32 hard yes yes yes 37 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes 38 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes 39 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes 40 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes 41 * Panther Point (PCH) 0x1e22 32 hard yes yes yes 42 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes 43 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes 44 * Avoton (SOC) 0x1f3c 32 hard yes yes yes 45 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes 46 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes 47 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes 48 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes 49 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes 50 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes 51 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes 52 * BayTrail (SOC) 0x0f12 32 hard yes yes yes 53 * Braswell (SOC) 0x2292 32 hard yes yes yes 54 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes 55 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes 56 * DNV (SOC) 0x19df 32 hard yes yes yes 57 * Emmitsburg (PCH) 0x1bc9 32 hard yes yes yes 58 * Broxton (SOC) 0x5ad4 32 hard yes yes yes 59 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes 60 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes 61 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes 62 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes 63 * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes 64 * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes 65 * Cedar Fork (PCH) 0x18df 32 hard yes yes yes 66 * Ice Lake-LP (PCH) 0x34a3 32 hard yes yes yes 67 * Comet Lake (PCH) 0x02a3 32 hard yes yes yes 68 * Comet Lake-H (PCH) 0x06a3 32 hard yes yes yes 69 * Elkhart Lake (PCH) 0x4b23 32 hard yes yes yes 70 * Tiger Lake-LP (PCH) 0xa0a3 32 hard yes yes yes 71 * Tiger Lake-H (PCH) 0x43a3 32 hard yes yes yes 72 * Jasper Lake (SOC) 0x4da3 32 hard yes yes yes 73 * Comet Lake-V (PCH) 0xa3a3 32 hard yes yes yes 74 * Alder Lake-S (PCH) 0x7aa3 32 hard yes yes yes 75 * Alder Lake-P (PCH) 0x51a3 32 hard yes yes yes 76 * Alder Lake-M (PCH) 0x54a3 32 hard yes yes yes 77 * 78 * Features supported by this driver: 79 * Software PEC no 80 * Hardware PEC yes 81 * Block buffer yes 82 * Block process call transaction yes 83 * I2C block read transaction yes (doesn't use the block buffer) 84 * Slave mode no 85 * SMBus Host Notify yes 86 * Interrupt processing yes 87 * 88 * See the file Documentation/i2c/busses/i2c-i801.rst for details. 89 */ 90 91 #define DRV_NAME "i801_smbus" 92 93 #include <linux/interrupt.h> 94 #include <linux/module.h> 95 #include <linux/pci.h> 96 #include <linux/kernel.h> 97 #include <linux/stddef.h> 98 #include <linux/delay.h> 99 #include <linux/ioport.h> 100 #include <linux/init.h> 101 #include <linux/i2c.h> 102 #include <linux/i2c-smbus.h> 103 #include <linux/acpi.h> 104 #include <linux/io.h> 105 #include <linux/dmi.h> 106 #include <linux/slab.h> 107 #include <linux/string.h> 108 #include <linux/completion.h> 109 #include <linux/err.h> 110 #include <linux/platform_device.h> 111 #include <linux/platform_data/itco_wdt.h> 112 #include <linux/pm_runtime.h> 113 114 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 115 #include <linux/gpio/machine.h> 116 #include <linux/platform_data/i2c-mux-gpio.h> 117 #endif 118 119 /* I801 SMBus address offsets */ 120 #define SMBHSTSTS(p) (0 + (p)->smba) 121 #define SMBHSTCNT(p) (2 + (p)->smba) 122 #define SMBHSTCMD(p) (3 + (p)->smba) 123 #define SMBHSTADD(p) (4 + (p)->smba) 124 #define SMBHSTDAT0(p) (5 + (p)->smba) 125 #define SMBHSTDAT1(p) (6 + (p)->smba) 126 #define SMBBLKDAT(p) (7 + (p)->smba) 127 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */ 128 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */ 129 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */ 130 #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */ 131 #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */ 132 #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */ 133 134 /* PCI Address Constants */ 135 #define SMBBAR 4 136 #define SMBHSTCFG 0x040 137 #define TCOBASE 0x050 138 #define TCOCTL 0x054 139 140 #define SBREG_BAR 0x10 141 #define SBREG_SMBCTRL 0xc6000c 142 #define SBREG_SMBCTRL_DNV 0xcf000c 143 144 /* Host configuration bits for SMBHSTCFG */ 145 #define SMBHSTCFG_HST_EN BIT(0) 146 #define SMBHSTCFG_SMB_SMI_EN BIT(1) 147 #define SMBHSTCFG_I2C_EN BIT(2) 148 #define SMBHSTCFG_SPD_WD BIT(4) 149 150 /* TCO configuration bits for TCOCTL */ 151 #define TCOCTL_EN BIT(8) 152 153 /* Auxiliary status register bits, ICH4+ only */ 154 #define SMBAUXSTS_CRCE BIT(0) 155 #define SMBAUXSTS_STCO BIT(1) 156 157 /* Auxiliary control register bits, ICH4+ only */ 158 #define SMBAUXCTL_CRC BIT(0) 159 #define SMBAUXCTL_E32B BIT(1) 160 161 /* I801 command constants */ 162 #define I801_QUICK 0x00 163 #define I801_BYTE 0x04 164 #define I801_BYTE_DATA 0x08 165 #define I801_WORD_DATA 0x0C 166 #define I801_PROC_CALL 0x10 /* unimplemented */ 167 #define I801_BLOCK_DATA 0x14 168 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ 169 #define I801_BLOCK_PROC_CALL 0x1C 170 171 /* I801 Host Control register bits */ 172 #define SMBHSTCNT_INTREN BIT(0) 173 #define SMBHSTCNT_KILL BIT(1) 174 #define SMBHSTCNT_LAST_BYTE BIT(5) 175 #define SMBHSTCNT_START BIT(6) 176 #define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */ 177 178 /* I801 Hosts Status register bits */ 179 #define SMBHSTSTS_BYTE_DONE BIT(7) 180 #define SMBHSTSTS_INUSE_STS BIT(6) 181 #define SMBHSTSTS_SMBALERT_STS BIT(5) 182 #define SMBHSTSTS_FAILED BIT(4) 183 #define SMBHSTSTS_BUS_ERR BIT(3) 184 #define SMBHSTSTS_DEV_ERR BIT(2) 185 #define SMBHSTSTS_INTR BIT(1) 186 #define SMBHSTSTS_HOST_BUSY BIT(0) 187 188 /* Host Notify Status register bits */ 189 #define SMBSLVSTS_HST_NTFY_STS BIT(0) 190 191 /* Host Notify Command register bits */ 192 #define SMBSLVCMD_HST_NTFY_INTREN BIT(0) 193 194 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \ 195 SMBHSTSTS_DEV_ERR) 196 197 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \ 198 STATUS_ERROR_FLAGS) 199 200 /* Older devices have their ID defined in <linux/pci_ids.h> */ 201 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS 0x02a3 202 #define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS 0x06a3 203 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12 204 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df 205 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df 206 #define PCI_DEVICE_ID_INTEL_EBG_SMBUS 0x1bc9 207 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 208 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 209 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */ 210 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70 211 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71 212 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72 213 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 214 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c 215 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292 216 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 217 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0 218 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4 219 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS 0x34a3 220 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 221 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS 0x43a3 222 #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS 0x4b23 223 #define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS 0x4da3 224 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS 0x51a3 225 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS 0x54a3 226 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4 227 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS 0x7aa3 228 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 229 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2 230 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22 231 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d 232 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e 233 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f 234 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22 235 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2 236 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23 237 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3 238 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS 0xa0a3 239 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123 240 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3 241 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223 242 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3 243 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323 244 #define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS 0xa3a3 245 246 struct i801_mux_config { 247 char *gpio_chip; 248 unsigned values[3]; 249 int n_values; 250 unsigned classes[3]; 251 unsigned gpios[2]; /* Relative to gpio_chip->base */ 252 int n_gpios; 253 }; 254 255 struct i801_priv { 256 struct i2c_adapter adapter; 257 unsigned long smba; 258 unsigned char original_hstcfg; 259 unsigned char original_slvcmd; 260 struct pci_dev *pci_dev; 261 unsigned int features; 262 263 /* isr processing */ 264 struct completion done; 265 u8 status; 266 267 /* Command state used by isr for byte-by-byte block transactions */ 268 u8 cmd; 269 bool is_read; 270 int count; 271 int len; 272 u8 *data; 273 274 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 275 const struct i801_mux_config *mux_drvdata; 276 struct platform_device *mux_pdev; 277 struct gpiod_lookup_table *lookup; 278 #endif 279 struct platform_device *tco_pdev; 280 281 /* 282 * If set to true the host controller registers are reserved for 283 * ACPI AML use. Protected by acpi_lock. 284 */ 285 bool acpi_reserved; 286 struct mutex acpi_lock; 287 }; 288 289 #define FEATURE_SMBUS_PEC BIT(0) 290 #define FEATURE_BLOCK_BUFFER BIT(1) 291 #define FEATURE_BLOCK_PROC BIT(2) 292 #define FEATURE_I2C_BLOCK_READ BIT(3) 293 #define FEATURE_IRQ BIT(4) 294 #define FEATURE_HOST_NOTIFY BIT(5) 295 /* Not really a feature, but it's convenient to handle it as such */ 296 #define FEATURE_IDF BIT(15) 297 #define FEATURE_TCO_SPT BIT(16) 298 #define FEATURE_TCO_CNL BIT(17) 299 300 static const char *i801_feature_names[] = { 301 "SMBus PEC", 302 "Block buffer", 303 "Block process call", 304 "I2C block read", 305 "Interrupt", 306 "SMBus Host Notify", 307 }; 308 309 static unsigned int disable_features; 310 module_param(disable_features, uint, S_IRUGO | S_IWUSR); 311 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n" 312 "\t\t 0x01 disable SMBus PEC\n" 313 "\t\t 0x02 disable the block buffer\n" 314 "\t\t 0x08 disable the I2C block read functionality\n" 315 "\t\t 0x10 don't use interrupts\n" 316 "\t\t 0x20 disable SMBus Host Notify "); 317 318 /* Make sure the SMBus host is ready to start transmitting. 319 Return 0 if it is, -EBUSY if it is not. */ 320 static int i801_check_pre(struct i801_priv *priv) 321 { 322 int status; 323 324 status = inb_p(SMBHSTSTS(priv)); 325 if (status & SMBHSTSTS_HOST_BUSY) { 326 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n"); 327 return -EBUSY; 328 } 329 330 status &= STATUS_FLAGS; 331 if (status) { 332 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n", 333 status); 334 outb_p(status, SMBHSTSTS(priv)); 335 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS; 336 if (status) { 337 dev_err(&priv->pci_dev->dev, 338 "Failed clearing status flags (%02x)\n", 339 status); 340 return -EBUSY; 341 } 342 } 343 344 /* 345 * Clear CRC status if needed. 346 * During normal operation, i801_check_post() takes care 347 * of it after every operation. We do it here only in case 348 * the hardware was already in this state when the driver 349 * started. 350 */ 351 if (priv->features & FEATURE_SMBUS_PEC) { 352 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE; 353 if (status) { 354 dev_dbg(&priv->pci_dev->dev, 355 "Clearing aux status flags (%02x)\n", status); 356 outb_p(status, SMBAUXSTS(priv)); 357 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE; 358 if (status) { 359 dev_err(&priv->pci_dev->dev, 360 "Failed clearing aux status flags (%02x)\n", 361 status); 362 return -EBUSY; 363 } 364 } 365 } 366 367 return 0; 368 } 369 370 /* 371 * Convert the status register to an error code, and clear it. 372 * Note that status only contains the bits we want to clear, not the 373 * actual register value. 374 */ 375 static int i801_check_post(struct i801_priv *priv, int status) 376 { 377 int result = 0; 378 379 /* 380 * If the SMBus is still busy, we give up 381 * Note: This timeout condition only happens when using polling 382 * transactions. For interrupt operation, NAK/timeout is indicated by 383 * DEV_ERR. 384 */ 385 if (unlikely(status < 0)) { 386 dev_err(&priv->pci_dev->dev, "Transaction timeout\n"); 387 /* try to stop the current command */ 388 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n"); 389 outb_p(SMBHSTCNT_KILL, SMBHSTCNT(priv)); 390 usleep_range(1000, 2000); 391 outb_p(0, SMBHSTCNT(priv)); 392 393 /* Check if it worked */ 394 status = inb_p(SMBHSTSTS(priv)); 395 if ((status & SMBHSTSTS_HOST_BUSY) || 396 !(status & SMBHSTSTS_FAILED)) 397 dev_err(&priv->pci_dev->dev, 398 "Failed terminating the transaction\n"); 399 outb_p(STATUS_FLAGS, SMBHSTSTS(priv)); 400 return -ETIMEDOUT; 401 } 402 403 if (status & SMBHSTSTS_FAILED) { 404 result = -EIO; 405 dev_err(&priv->pci_dev->dev, "Transaction failed\n"); 406 } 407 if (status & SMBHSTSTS_DEV_ERR) { 408 /* 409 * This may be a PEC error, check and clear it. 410 * 411 * AUXSTS is handled differently from HSTSTS. 412 * For HSTSTS, i801_isr() or i801_wait_intr() 413 * has already cleared the error bits in hardware, 414 * and we are passed a copy of the original value 415 * in "status". 416 * For AUXSTS, the hardware register is left 417 * for us to handle here. 418 * This is asymmetric, slightly iffy, but safe, 419 * since all this code is serialized and the CRCE 420 * bit is harmless as long as it's cleared before 421 * the next operation. 422 */ 423 if ((priv->features & FEATURE_SMBUS_PEC) && 424 (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) { 425 outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv)); 426 result = -EBADMSG; 427 dev_dbg(&priv->pci_dev->dev, "PEC error\n"); 428 } else { 429 result = -ENXIO; 430 dev_dbg(&priv->pci_dev->dev, "No response\n"); 431 } 432 } 433 if (status & SMBHSTSTS_BUS_ERR) { 434 result = -EAGAIN; 435 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n"); 436 } 437 438 /* Clear status flags except BYTE_DONE, to be cleared by caller */ 439 outb_p(status, SMBHSTSTS(priv)); 440 441 return result; 442 } 443 444 /* Wait for BUSY being cleared and either INTR or an error flag being set */ 445 static int i801_wait_intr(struct i801_priv *priv) 446 { 447 unsigned long timeout = jiffies + priv->adapter.timeout; 448 int status, busy; 449 450 do { 451 usleep_range(250, 500); 452 status = inb_p(SMBHSTSTS(priv)); 453 busy = status & SMBHSTSTS_HOST_BUSY; 454 status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR; 455 if (!busy && status) 456 return status; 457 } while (time_is_after_eq_jiffies(timeout)); 458 459 return -ETIMEDOUT; 460 } 461 462 /* Wait for either BYTE_DONE or an error flag being set */ 463 static int i801_wait_byte_done(struct i801_priv *priv) 464 { 465 unsigned long timeout = jiffies + priv->adapter.timeout; 466 int status; 467 468 do { 469 usleep_range(250, 500); 470 status = inb_p(SMBHSTSTS(priv)); 471 if (status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) 472 return status & STATUS_ERROR_FLAGS; 473 } while (time_is_after_eq_jiffies(timeout)); 474 475 return -ETIMEDOUT; 476 } 477 478 static int i801_transaction(struct i801_priv *priv, int xact) 479 { 480 int status; 481 unsigned long result; 482 const struct i2c_adapter *adap = &priv->adapter; 483 484 status = i801_check_pre(priv); 485 if (status < 0) 486 return status; 487 488 if (priv->features & FEATURE_IRQ) { 489 reinit_completion(&priv->done); 490 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START, 491 SMBHSTCNT(priv)); 492 result = wait_for_completion_timeout(&priv->done, adap->timeout); 493 return i801_check_post(priv, result ? priv->status : -ETIMEDOUT); 494 } 495 496 /* the current contents of SMBHSTCNT can be overwritten, since PEC, 497 * SMBSCMD are passed in xact */ 498 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv)); 499 500 status = i801_wait_intr(priv); 501 return i801_check_post(priv, status); 502 } 503 504 static int i801_block_transaction_by_block(struct i801_priv *priv, 505 union i2c_smbus_data *data, 506 char read_write, int command, 507 int hwpec) 508 { 509 int i, len; 510 int status; 511 int xact = hwpec ? SMBHSTCNT_PEC_EN : 0; 512 513 switch (command) { 514 case I2C_SMBUS_BLOCK_PROC_CALL: 515 xact |= I801_BLOCK_PROC_CALL; 516 break; 517 case I2C_SMBUS_BLOCK_DATA: 518 xact |= I801_BLOCK_DATA; 519 break; 520 default: 521 return -EOPNOTSUPP; 522 } 523 524 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ 525 526 /* Use 32-byte buffer to process this transaction */ 527 if (read_write == I2C_SMBUS_WRITE) { 528 len = data->block[0]; 529 outb_p(len, SMBHSTDAT0(priv)); 530 for (i = 0; i < len; i++) 531 outb_p(data->block[i+1], SMBBLKDAT(priv)); 532 } 533 534 status = i801_transaction(priv, xact); 535 if (status) 536 return status; 537 538 if (read_write == I2C_SMBUS_READ || 539 command == I2C_SMBUS_BLOCK_PROC_CALL) { 540 len = inb_p(SMBHSTDAT0(priv)); 541 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) 542 return -EPROTO; 543 544 data->block[0] = len; 545 for (i = 0; i < len; i++) 546 data->block[i + 1] = inb_p(SMBBLKDAT(priv)); 547 } 548 return 0; 549 } 550 551 static void i801_isr_byte_done(struct i801_priv *priv) 552 { 553 if (priv->is_read) { 554 /* For SMBus block reads, length is received with first byte */ 555 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) && 556 (priv->count == 0)) { 557 priv->len = inb_p(SMBHSTDAT0(priv)); 558 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) { 559 dev_err(&priv->pci_dev->dev, 560 "Illegal SMBus block read size %d\n", 561 priv->len); 562 /* FIXME: Recover */ 563 priv->len = I2C_SMBUS_BLOCK_MAX; 564 } else { 565 dev_dbg(&priv->pci_dev->dev, 566 "SMBus block read size is %d\n", 567 priv->len); 568 } 569 priv->data[-1] = priv->len; 570 } 571 572 /* Read next byte */ 573 if (priv->count < priv->len) 574 priv->data[priv->count++] = inb(SMBBLKDAT(priv)); 575 else 576 dev_dbg(&priv->pci_dev->dev, 577 "Discarding extra byte on block read\n"); 578 579 /* Set LAST_BYTE for last byte of read transaction */ 580 if (priv->count == priv->len - 1) 581 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE, 582 SMBHSTCNT(priv)); 583 } else if (priv->count < priv->len - 1) { 584 /* Write next byte, except for IRQ after last byte */ 585 outb_p(priv->data[++priv->count], SMBBLKDAT(priv)); 586 } 587 588 /* Clear BYTE_DONE to continue with next byte */ 589 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 590 } 591 592 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv) 593 { 594 unsigned short addr; 595 596 addr = inb_p(SMBNTFDADD(priv)) >> 1; 597 598 /* 599 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba) 600 * always returns 0. Our current implementation doesn't provide 601 * data, so we just ignore it. 602 */ 603 i2c_handle_smbus_host_notify(&priv->adapter, addr); 604 605 /* clear Host Notify bit and return */ 606 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 607 return IRQ_HANDLED; 608 } 609 610 /* 611 * There are three kinds of interrupts: 612 * 613 * 1) i801 signals transaction completion with one of these interrupts: 614 * INTR - Success 615 * DEV_ERR - Invalid command, NAK or communication timeout 616 * BUS_ERR - SMI# transaction collision 617 * FAILED - transaction was canceled due to a KILL request 618 * When any of these occur, update ->status and signal completion. 619 * ->status must be cleared before kicking off the next transaction. 620 * 621 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt 622 * occurs for each byte of a byte-by-byte to prepare the next byte. 623 * 624 * 3) Host Notify interrupts 625 */ 626 static irqreturn_t i801_isr(int irq, void *dev_id) 627 { 628 struct i801_priv *priv = dev_id; 629 u16 pcists; 630 u8 status; 631 632 /* Confirm this is our interrupt */ 633 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists); 634 if (!(pcists & PCI_STATUS_INTERRUPT)) 635 return IRQ_NONE; 636 637 if (priv->features & FEATURE_HOST_NOTIFY) { 638 status = inb_p(SMBSLVSTS(priv)); 639 if (status & SMBSLVSTS_HST_NTFY_STS) 640 return i801_host_notify_isr(priv); 641 } 642 643 status = inb_p(SMBHSTSTS(priv)); 644 if (status & SMBHSTSTS_BYTE_DONE) 645 i801_isr_byte_done(priv); 646 647 /* 648 * Clear irq sources and report transaction result. 649 * ->status must be cleared before the next transaction is started. 650 */ 651 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS; 652 if (status) { 653 outb_p(status, SMBHSTSTS(priv)); 654 priv->status = status; 655 complete(&priv->done); 656 } 657 658 return IRQ_HANDLED; 659 } 660 661 /* 662 * For "byte-by-byte" block transactions: 663 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1 664 * I2C read uses cmd=I801_I2C_BLOCK_DATA 665 */ 666 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, 667 union i2c_smbus_data *data, 668 char read_write, int command, 669 int hwpec) 670 { 671 int i, len; 672 int smbcmd; 673 int status; 674 unsigned long result; 675 const struct i2c_adapter *adap = &priv->adapter; 676 677 if (command == I2C_SMBUS_BLOCK_PROC_CALL) 678 return -EOPNOTSUPP; 679 680 status = i801_check_pre(priv); 681 if (status < 0) 682 return status; 683 684 len = data->block[0]; 685 686 if (read_write == I2C_SMBUS_WRITE) { 687 outb_p(len, SMBHSTDAT0(priv)); 688 outb_p(data->block[1], SMBBLKDAT(priv)); 689 } 690 691 if (command == I2C_SMBUS_I2C_BLOCK_DATA && 692 read_write == I2C_SMBUS_READ) 693 smbcmd = I801_I2C_BLOCK_DATA; 694 else 695 smbcmd = I801_BLOCK_DATA; 696 697 if (priv->features & FEATURE_IRQ) { 698 priv->is_read = (read_write == I2C_SMBUS_READ); 699 if (len == 1 && priv->is_read) 700 smbcmd |= SMBHSTCNT_LAST_BYTE; 701 priv->cmd = smbcmd | SMBHSTCNT_INTREN; 702 priv->len = len; 703 priv->count = 0; 704 priv->data = &data->block[1]; 705 706 reinit_completion(&priv->done); 707 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv)); 708 result = wait_for_completion_timeout(&priv->done, adap->timeout); 709 return i801_check_post(priv, result ? priv->status : -ETIMEDOUT); 710 } 711 712 for (i = 1; i <= len; i++) { 713 if (i == len && read_write == I2C_SMBUS_READ) 714 smbcmd |= SMBHSTCNT_LAST_BYTE; 715 outb_p(smbcmd, SMBHSTCNT(priv)); 716 717 if (i == 1) 718 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START, 719 SMBHSTCNT(priv)); 720 721 status = i801_wait_byte_done(priv); 722 if (status) 723 goto exit; 724 725 if (i == 1 && read_write == I2C_SMBUS_READ 726 && command != I2C_SMBUS_I2C_BLOCK_DATA) { 727 len = inb_p(SMBHSTDAT0(priv)); 728 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { 729 dev_err(&priv->pci_dev->dev, 730 "Illegal SMBus block read size %d\n", 731 len); 732 /* Recover */ 733 while (inb_p(SMBHSTSTS(priv)) & 734 SMBHSTSTS_HOST_BUSY) 735 outb_p(SMBHSTSTS_BYTE_DONE, 736 SMBHSTSTS(priv)); 737 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); 738 return -EPROTO; 739 } 740 data->block[0] = len; 741 } 742 743 /* Retrieve/store value in SMBBLKDAT */ 744 if (read_write == I2C_SMBUS_READ) 745 data->block[i] = inb_p(SMBBLKDAT(priv)); 746 if (read_write == I2C_SMBUS_WRITE && i+1 <= len) 747 outb_p(data->block[i+1], SMBBLKDAT(priv)); 748 749 /* signals SMBBLKDAT ready */ 750 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 751 } 752 753 status = i801_wait_intr(priv); 754 exit: 755 return i801_check_post(priv, status); 756 } 757 758 static int i801_set_block_buffer_mode(struct i801_priv *priv) 759 { 760 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv)); 761 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0) 762 return -EIO; 763 return 0; 764 } 765 766 /* Block transaction function */ 767 static int i801_block_transaction(struct i801_priv *priv, 768 union i2c_smbus_data *data, char read_write, 769 int command, int hwpec) 770 { 771 int result = 0; 772 unsigned char hostc; 773 774 if (command == I2C_SMBUS_I2C_BLOCK_DATA) { 775 if (read_write == I2C_SMBUS_WRITE) { 776 /* set I2C_EN bit in configuration register */ 777 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc); 778 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, 779 hostc | SMBHSTCFG_I2C_EN); 780 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) { 781 dev_err(&priv->pci_dev->dev, 782 "I2C block read is unsupported!\n"); 783 return -EOPNOTSUPP; 784 } 785 } 786 787 if (read_write == I2C_SMBUS_WRITE 788 || command == I2C_SMBUS_I2C_BLOCK_DATA) { 789 if (data->block[0] < 1) 790 data->block[0] = 1; 791 if (data->block[0] > I2C_SMBUS_BLOCK_MAX) 792 data->block[0] = I2C_SMBUS_BLOCK_MAX; 793 } else { 794 data->block[0] = 32; /* max for SMBus block reads */ 795 } 796 797 /* Experience has shown that the block buffer can only be used for 798 SMBus (not I2C) block transactions, even though the datasheet 799 doesn't mention this limitation. */ 800 if ((priv->features & FEATURE_BLOCK_BUFFER) 801 && command != I2C_SMBUS_I2C_BLOCK_DATA 802 && i801_set_block_buffer_mode(priv) == 0) 803 result = i801_block_transaction_by_block(priv, data, 804 read_write, 805 command, hwpec); 806 else 807 result = i801_block_transaction_byte_by_byte(priv, data, 808 read_write, 809 command, hwpec); 810 811 if (command == I2C_SMBUS_I2C_BLOCK_DATA 812 && read_write == I2C_SMBUS_WRITE) { 813 /* restore saved configuration register value */ 814 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc); 815 } 816 return result; 817 } 818 819 /* Return negative errno on error. */ 820 static s32 i801_access(struct i2c_adapter *adap, u16 addr, 821 unsigned short flags, char read_write, u8 command, 822 int size, union i2c_smbus_data *data) 823 { 824 int hwpec; 825 int block = 0; 826 int ret = 0, xact = 0; 827 struct i801_priv *priv = i2c_get_adapdata(adap); 828 829 mutex_lock(&priv->acpi_lock); 830 if (priv->acpi_reserved) { 831 mutex_unlock(&priv->acpi_lock); 832 return -EBUSY; 833 } 834 835 pm_runtime_get_sync(&priv->pci_dev->dev); 836 837 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) 838 && size != I2C_SMBUS_QUICK 839 && size != I2C_SMBUS_I2C_BLOCK_DATA; 840 841 switch (size) { 842 case I2C_SMBUS_QUICK: 843 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 844 SMBHSTADD(priv)); 845 xact = I801_QUICK; 846 break; 847 case I2C_SMBUS_BYTE: 848 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 849 SMBHSTADD(priv)); 850 if (read_write == I2C_SMBUS_WRITE) 851 outb_p(command, SMBHSTCMD(priv)); 852 xact = I801_BYTE; 853 break; 854 case I2C_SMBUS_BYTE_DATA: 855 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 856 SMBHSTADD(priv)); 857 outb_p(command, SMBHSTCMD(priv)); 858 if (read_write == I2C_SMBUS_WRITE) 859 outb_p(data->byte, SMBHSTDAT0(priv)); 860 xact = I801_BYTE_DATA; 861 break; 862 case I2C_SMBUS_WORD_DATA: 863 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 864 SMBHSTADD(priv)); 865 outb_p(command, SMBHSTCMD(priv)); 866 if (read_write == I2C_SMBUS_WRITE) { 867 outb_p(data->word & 0xff, SMBHSTDAT0(priv)); 868 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); 869 } 870 xact = I801_WORD_DATA; 871 break; 872 case I2C_SMBUS_BLOCK_DATA: 873 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 874 SMBHSTADD(priv)); 875 outb_p(command, SMBHSTCMD(priv)); 876 block = 1; 877 break; 878 case I2C_SMBUS_I2C_BLOCK_DATA: 879 /* 880 * NB: page 240 of ICH5 datasheet shows that the R/#W 881 * bit should be cleared here, even when reading. 882 * However if SPD Write Disable is set (Lynx Point and later), 883 * the read will fail if we don't set the R/#W bit. 884 */ 885 outb_p(((addr & 0x7f) << 1) | 886 ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ? 887 (read_write & 0x01) : 0), 888 SMBHSTADD(priv)); 889 if (read_write == I2C_SMBUS_READ) { 890 /* NB: page 240 of ICH5 datasheet also shows 891 * that DATA1 is the cmd field when reading */ 892 outb_p(command, SMBHSTDAT1(priv)); 893 } else 894 outb_p(command, SMBHSTCMD(priv)); 895 block = 1; 896 break; 897 case I2C_SMBUS_BLOCK_PROC_CALL: 898 /* 899 * Bit 0 of the slave address register always indicate a write 900 * command. 901 */ 902 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv)); 903 outb_p(command, SMBHSTCMD(priv)); 904 block = 1; 905 break; 906 default: 907 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n", 908 size); 909 ret = -EOPNOTSUPP; 910 goto out; 911 } 912 913 if (hwpec) /* enable/disable hardware PEC */ 914 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv)); 915 else 916 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC), 917 SMBAUXCTL(priv)); 918 919 if (block) 920 ret = i801_block_transaction(priv, data, read_write, size, 921 hwpec); 922 else 923 ret = i801_transaction(priv, xact); 924 925 /* Some BIOSes don't like it when PEC is enabled at reboot or resume 926 time, so we forcibly disable it after every transaction. Turn off 927 E32B for the same reason. */ 928 if (hwpec || block) 929 outb_p(inb_p(SMBAUXCTL(priv)) & 930 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 931 932 if (block) 933 goto out; 934 if (ret) 935 goto out; 936 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK)) 937 goto out; 938 939 switch (xact & 0x7f) { 940 case I801_BYTE: /* Result put in SMBHSTDAT0 */ 941 case I801_BYTE_DATA: 942 data->byte = inb_p(SMBHSTDAT0(priv)); 943 break; 944 case I801_WORD_DATA: 945 data->word = inb_p(SMBHSTDAT0(priv)) + 946 (inb_p(SMBHSTDAT1(priv)) << 8); 947 break; 948 } 949 950 out: 951 /* Unlock the SMBus device for use by BIOS/ACPI */ 952 outb_p(SMBHSTSTS_INUSE_STS, SMBHSTSTS(priv)); 953 954 pm_runtime_mark_last_busy(&priv->pci_dev->dev); 955 pm_runtime_put_autosuspend(&priv->pci_dev->dev); 956 mutex_unlock(&priv->acpi_lock); 957 return ret; 958 } 959 960 961 static u32 i801_func(struct i2c_adapter *adapter) 962 { 963 struct i801_priv *priv = i2c_get_adapdata(adapter); 964 965 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 966 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 967 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | 968 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | 969 ((priv->features & FEATURE_BLOCK_PROC) ? 970 I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) | 971 ((priv->features & FEATURE_I2C_BLOCK_READ) ? 972 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) | 973 ((priv->features & FEATURE_HOST_NOTIFY) ? 974 I2C_FUNC_SMBUS_HOST_NOTIFY : 0); 975 } 976 977 static void i801_enable_host_notify(struct i2c_adapter *adapter) 978 { 979 struct i801_priv *priv = i2c_get_adapdata(adapter); 980 981 if (!(priv->features & FEATURE_HOST_NOTIFY)) 982 return; 983 984 if (!(SMBSLVCMD_HST_NTFY_INTREN & priv->original_slvcmd)) 985 outb_p(SMBSLVCMD_HST_NTFY_INTREN | priv->original_slvcmd, 986 SMBSLVCMD(priv)); 987 988 /* clear Host Notify bit to allow a new notification */ 989 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 990 } 991 992 static void i801_disable_host_notify(struct i801_priv *priv) 993 { 994 if (!(priv->features & FEATURE_HOST_NOTIFY)) 995 return; 996 997 outb_p(priv->original_slvcmd, SMBSLVCMD(priv)); 998 } 999 1000 static const struct i2c_algorithm smbus_algorithm = { 1001 .smbus_xfer = i801_access, 1002 .functionality = i801_func, 1003 }; 1004 1005 static const struct pci_device_id i801_ids[] = { 1006 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) }, 1007 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) }, 1008 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) }, 1009 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) }, 1010 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) }, 1011 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) }, 1012 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) }, 1013 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) }, 1014 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) }, 1015 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) }, 1016 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) }, 1017 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) }, 1018 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) }, 1019 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) }, 1020 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) }, 1021 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) }, 1022 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) }, 1023 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) }, 1024 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) }, 1025 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) }, 1026 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) }, 1027 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) }, 1028 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) }, 1029 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) }, 1030 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) }, 1031 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) }, 1032 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) }, 1033 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) }, 1034 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) }, 1035 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) }, 1036 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) }, 1037 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS) }, 1038 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) }, 1039 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) }, 1040 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) }, 1041 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) }, 1042 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) }, 1043 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) }, 1044 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMBUS) }, 1045 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) }, 1046 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EBG_SMBUS) }, 1047 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) }, 1048 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) }, 1049 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) }, 1050 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) }, 1051 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS) }, 1052 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS) }, 1053 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS) }, 1054 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS) }, 1055 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS) }, 1056 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS) }, 1057 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS) }, 1058 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS) }, 1059 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS) }, 1060 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS) }, 1061 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS) }, 1062 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS) }, 1063 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS) }, 1064 { 0, } 1065 }; 1066 1067 MODULE_DEVICE_TABLE(pci, i801_ids); 1068 1069 #if defined CONFIG_X86 && defined CONFIG_DMI 1070 static unsigned char apanel_addr; 1071 1072 /* Scan the system ROM for the signature "FJKEYINF" */ 1073 static __init const void __iomem *bios_signature(const void __iomem *bios) 1074 { 1075 ssize_t offset; 1076 const unsigned char signature[] = "FJKEYINF"; 1077 1078 for (offset = 0; offset < 0x10000; offset += 0x10) { 1079 if (check_signature(bios + offset, signature, 1080 sizeof(signature)-1)) 1081 return bios + offset; 1082 } 1083 return NULL; 1084 } 1085 1086 static void __init input_apanel_init(void) 1087 { 1088 void __iomem *bios; 1089 const void __iomem *p; 1090 1091 bios = ioremap(0xF0000, 0x10000); /* Can't fail */ 1092 p = bios_signature(bios); 1093 if (p) { 1094 /* just use the first address */ 1095 apanel_addr = readb(p + 8 + 3) >> 1; 1096 } 1097 iounmap(bios); 1098 } 1099 1100 struct dmi_onboard_device_info { 1101 const char *name; 1102 u8 type; 1103 unsigned short i2c_addr; 1104 const char *i2c_type; 1105 }; 1106 1107 static const struct dmi_onboard_device_info dmi_devices[] = { 1108 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" }, 1109 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" }, 1110 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" }, 1111 }; 1112 1113 static void dmi_check_onboard_device(u8 type, const char *name, 1114 struct i2c_adapter *adap) 1115 { 1116 int i; 1117 struct i2c_board_info info; 1118 1119 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) { 1120 /* & ~0x80, ignore enabled/disabled bit */ 1121 if ((type & ~0x80) != dmi_devices[i].type) 1122 continue; 1123 if (strcasecmp(name, dmi_devices[i].name)) 1124 continue; 1125 1126 memset(&info, 0, sizeof(struct i2c_board_info)); 1127 info.addr = dmi_devices[i].i2c_addr; 1128 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); 1129 i2c_new_client_device(adap, &info); 1130 break; 1131 } 1132 } 1133 1134 /* We use our own function to check for onboard devices instead of 1135 dmi_find_device() as some buggy BIOS's have the devices we are interested 1136 in marked as disabled */ 1137 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap) 1138 { 1139 int i, count; 1140 1141 if (dm->type != 10) 1142 return; 1143 1144 count = (dm->length - sizeof(struct dmi_header)) / 2; 1145 for (i = 0; i < count; i++) { 1146 const u8 *d = (char *)(dm + 1) + (i * 2); 1147 const char *name = ((char *) dm) + dm->length; 1148 u8 type = d[0]; 1149 u8 s = d[1]; 1150 1151 if (!s) 1152 continue; 1153 s--; 1154 while (s > 0 && name[0]) { 1155 name += strlen(name) + 1; 1156 s--; 1157 } 1158 if (name[0] == 0) /* Bogus string reference */ 1159 continue; 1160 1161 dmi_check_onboard_device(type, name, adap); 1162 } 1163 } 1164 1165 /* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */ 1166 static const char *const acpi_smo8800_ids[] = { 1167 "SMO8800", 1168 "SMO8801", 1169 "SMO8810", 1170 "SMO8811", 1171 "SMO8820", 1172 "SMO8821", 1173 "SMO8830", 1174 "SMO8831", 1175 }; 1176 1177 static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle, 1178 u32 nesting_level, 1179 void *context, 1180 void **return_value) 1181 { 1182 struct acpi_device_info *info; 1183 acpi_status status; 1184 char *hid; 1185 int i; 1186 1187 status = acpi_get_object_info(obj_handle, &info); 1188 if (ACPI_FAILURE(status)) 1189 return AE_OK; 1190 1191 if (!(info->valid & ACPI_VALID_HID)) 1192 goto smo88xx_not_found; 1193 1194 hid = info->hardware_id.string; 1195 if (!hid) 1196 goto smo88xx_not_found; 1197 1198 i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid); 1199 if (i < 0) 1200 goto smo88xx_not_found; 1201 1202 kfree(info); 1203 1204 *((bool *)return_value) = true; 1205 return AE_CTRL_TERMINATE; 1206 1207 smo88xx_not_found: 1208 kfree(info); 1209 return AE_OK; 1210 } 1211 1212 static bool is_dell_system_with_lis3lv02d(void) 1213 { 1214 bool found; 1215 const char *vendor; 1216 1217 vendor = dmi_get_system_info(DMI_SYS_VENDOR); 1218 if (!vendor || strcmp(vendor, "Dell Inc.")) 1219 return false; 1220 1221 /* 1222 * Check that ACPI device SMO88xx is present and is functioning. 1223 * Function acpi_get_devices() already filters all ACPI devices 1224 * which are not present or are not functioning. 1225 * ACPI device SMO88xx represents our ST microelectronics lis3lv02d 1226 * accelerometer but unfortunately ACPI does not provide any other 1227 * information (like I2C address). 1228 */ 1229 found = false; 1230 acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL, 1231 (void **)&found); 1232 1233 return found; 1234 } 1235 1236 /* 1237 * Accelerometer's I2C address is not specified in DMI nor ACPI, 1238 * so it is needed to define mapping table based on DMI product names. 1239 */ 1240 static const struct { 1241 const char *dmi_product_name; 1242 unsigned short i2c_addr; 1243 } dell_lis3lv02d_devices[] = { 1244 /* 1245 * Dell platform team told us that these Latitude devices have 1246 * ST microelectronics accelerometer at I2C address 0x29. 1247 */ 1248 { "Latitude E5250", 0x29 }, 1249 { "Latitude E5450", 0x29 }, 1250 { "Latitude E5550", 0x29 }, 1251 { "Latitude E6440", 0x29 }, 1252 { "Latitude E6440 ATG", 0x29 }, 1253 { "Latitude E6540", 0x29 }, 1254 /* 1255 * Additional individual entries were added after verification. 1256 */ 1257 { "Latitude 5480", 0x29 }, 1258 { "Vostro V131", 0x1d }, 1259 }; 1260 1261 static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv) 1262 { 1263 struct i2c_board_info info; 1264 const char *dmi_product_name; 1265 int i; 1266 1267 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME); 1268 for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) { 1269 if (strcmp(dmi_product_name, 1270 dell_lis3lv02d_devices[i].dmi_product_name) == 0) 1271 break; 1272 } 1273 1274 if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) { 1275 dev_warn(&priv->pci_dev->dev, 1276 "Accelerometer lis3lv02d is present on SMBus but its" 1277 " address is unknown, skipping registration\n"); 1278 return; 1279 } 1280 1281 memset(&info, 0, sizeof(struct i2c_board_info)); 1282 info.addr = dell_lis3lv02d_devices[i].i2c_addr; 1283 strlcpy(info.type, "lis3lv02d", I2C_NAME_SIZE); 1284 i2c_new_client_device(&priv->adapter, &info); 1285 } 1286 1287 /* Register optional slaves */ 1288 static void i801_probe_optional_slaves(struct i801_priv *priv) 1289 { 1290 /* Only register slaves on main SMBus channel */ 1291 if (priv->features & FEATURE_IDF) 1292 return; 1293 1294 if (apanel_addr) { 1295 struct i2c_board_info info = { 1296 .addr = apanel_addr, 1297 .type = "fujitsu_apanel", 1298 }; 1299 1300 i2c_new_client_device(&priv->adapter, &info); 1301 } 1302 1303 if (dmi_name_in_vendors("FUJITSU")) 1304 dmi_walk(dmi_check_onboard_devices, &priv->adapter); 1305 1306 if (is_dell_system_with_lis3lv02d()) 1307 register_dell_lis3lv02d_i2c_device(priv); 1308 1309 /* Instantiate SPD EEPROMs unless the SMBus is multiplexed */ 1310 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) 1311 if (!priv->mux_drvdata) 1312 #endif 1313 i2c_register_spd(&priv->adapter); 1314 } 1315 #else 1316 static void __init input_apanel_init(void) {} 1317 static void i801_probe_optional_slaves(struct i801_priv *priv) {} 1318 #endif /* CONFIG_X86 && CONFIG_DMI */ 1319 1320 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 1321 static struct i801_mux_config i801_mux_config_asus_z8_d12 = { 1322 .gpio_chip = "gpio_ich", 1323 .values = { 0x02, 0x03 }, 1324 .n_values = 2, 1325 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD }, 1326 .gpios = { 52, 53 }, 1327 .n_gpios = 2, 1328 }; 1329 1330 static struct i801_mux_config i801_mux_config_asus_z8_d18 = { 1331 .gpio_chip = "gpio_ich", 1332 .values = { 0x02, 0x03, 0x01 }, 1333 .n_values = 3, 1334 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD }, 1335 .gpios = { 52, 53 }, 1336 .n_gpios = 2, 1337 }; 1338 1339 static const struct dmi_system_id mux_dmi_table[] = { 1340 { 1341 .matches = { 1342 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1343 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"), 1344 }, 1345 .driver_data = &i801_mux_config_asus_z8_d12, 1346 }, 1347 { 1348 .matches = { 1349 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1350 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"), 1351 }, 1352 .driver_data = &i801_mux_config_asus_z8_d12, 1353 }, 1354 { 1355 .matches = { 1356 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1357 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"), 1358 }, 1359 .driver_data = &i801_mux_config_asus_z8_d12, 1360 }, 1361 { 1362 .matches = { 1363 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1364 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"), 1365 }, 1366 .driver_data = &i801_mux_config_asus_z8_d12, 1367 }, 1368 { 1369 .matches = { 1370 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1371 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"), 1372 }, 1373 .driver_data = &i801_mux_config_asus_z8_d12, 1374 }, 1375 { 1376 .matches = { 1377 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1378 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"), 1379 }, 1380 .driver_data = &i801_mux_config_asus_z8_d12, 1381 }, 1382 { 1383 .matches = { 1384 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1385 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"), 1386 }, 1387 .driver_data = &i801_mux_config_asus_z8_d18, 1388 }, 1389 { 1390 .matches = { 1391 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1392 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"), 1393 }, 1394 .driver_data = &i801_mux_config_asus_z8_d18, 1395 }, 1396 { 1397 .matches = { 1398 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1399 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"), 1400 }, 1401 .driver_data = &i801_mux_config_asus_z8_d12, 1402 }, 1403 { } 1404 }; 1405 1406 /* Setup multiplexing if needed */ 1407 static int i801_add_mux(struct i801_priv *priv) 1408 { 1409 struct device *dev = &priv->adapter.dev; 1410 const struct i801_mux_config *mux_config; 1411 struct i2c_mux_gpio_platform_data gpio_data; 1412 struct gpiod_lookup_table *lookup; 1413 int i; 1414 1415 if (!priv->mux_drvdata) 1416 return 0; 1417 mux_config = priv->mux_drvdata; 1418 1419 /* Prepare the platform data */ 1420 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data)); 1421 gpio_data.parent = priv->adapter.nr; 1422 gpio_data.values = mux_config->values; 1423 gpio_data.n_values = mux_config->n_values; 1424 gpio_data.classes = mux_config->classes; 1425 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE; 1426 1427 /* Register GPIO descriptor lookup table */ 1428 lookup = devm_kzalloc(dev, 1429 struct_size(lookup, table, mux_config->n_gpios + 1), 1430 GFP_KERNEL); 1431 if (!lookup) 1432 return -ENOMEM; 1433 lookup->dev_id = "i2c-mux-gpio"; 1434 for (i = 0; i < mux_config->n_gpios; i++) { 1435 lookup->table[i] = (struct gpiod_lookup) 1436 GPIO_LOOKUP(mux_config->gpio_chip, 1437 mux_config->gpios[i], "mux", 0); 1438 } 1439 gpiod_add_lookup_table(lookup); 1440 priv->lookup = lookup; 1441 1442 /* 1443 * Register the mux device, we use PLATFORM_DEVID_NONE here 1444 * because since we are referring to the GPIO chip by name we are 1445 * anyways in deep trouble if there is more than one of these 1446 * devices, and there should likely only be one platform controller 1447 * hub. 1448 */ 1449 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio", 1450 PLATFORM_DEVID_NONE, &gpio_data, 1451 sizeof(struct i2c_mux_gpio_platform_data)); 1452 if (IS_ERR(priv->mux_pdev)) { 1453 gpiod_remove_lookup_table(lookup); 1454 dev_err(dev, "Failed to register i2c-mux-gpio device\n"); 1455 } 1456 1457 return PTR_ERR_OR_ZERO(priv->mux_pdev); 1458 } 1459 1460 static void i801_del_mux(struct i801_priv *priv) 1461 { 1462 platform_device_unregister(priv->mux_pdev); 1463 gpiod_remove_lookup_table(priv->lookup); 1464 } 1465 1466 static unsigned int i801_get_adapter_class(struct i801_priv *priv) 1467 { 1468 const struct dmi_system_id *id; 1469 const struct i801_mux_config *mux_config; 1470 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 1471 int i; 1472 1473 id = dmi_first_match(mux_dmi_table); 1474 if (id) { 1475 /* Remove branch classes from trunk */ 1476 mux_config = id->driver_data; 1477 for (i = 0; i < mux_config->n_values; i++) 1478 class &= ~mux_config->classes[i]; 1479 1480 /* Remember for later */ 1481 priv->mux_drvdata = mux_config; 1482 } 1483 1484 return class; 1485 } 1486 #else 1487 static inline int i801_add_mux(struct i801_priv *priv) { return 0; } 1488 static inline void i801_del_mux(struct i801_priv *priv) { } 1489 1490 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv) 1491 { 1492 return I2C_CLASS_HWMON | I2C_CLASS_SPD; 1493 } 1494 #endif 1495 1496 static const struct itco_wdt_platform_data spt_tco_platform_data = { 1497 .name = "Intel PCH", 1498 .version = 4, 1499 }; 1500 1501 static DEFINE_SPINLOCK(p2sb_spinlock); 1502 1503 static struct platform_device * 1504 i801_add_tco_spt(struct i801_priv *priv, struct pci_dev *pci_dev, 1505 struct resource *tco_res) 1506 { 1507 struct resource *res; 1508 unsigned int devfn; 1509 u64 base64_addr; 1510 u32 base_addr; 1511 u8 hidden; 1512 1513 /* 1514 * We must access the NO_REBOOT bit over the Primary to Sideband 1515 * bridge (P2SB). The BIOS prevents the P2SB device from being 1516 * enumerated by the PCI subsystem, so we need to unhide/hide it 1517 * to lookup the P2SB BAR. 1518 */ 1519 spin_lock(&p2sb_spinlock); 1520 1521 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1); 1522 1523 /* Unhide the P2SB device, if it is hidden */ 1524 pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden); 1525 if (hidden) 1526 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0); 1527 1528 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr); 1529 base64_addr = base_addr & 0xfffffff0; 1530 1531 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr); 1532 base64_addr |= (u64)base_addr << 32; 1533 1534 /* Hide the P2SB device, if it was hidden before */ 1535 if (hidden) 1536 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden); 1537 spin_unlock(&p2sb_spinlock); 1538 1539 res = &tco_res[1]; 1540 if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS) 1541 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV; 1542 else 1543 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL; 1544 1545 res->end = res->start + 3; 1546 res->flags = IORESOURCE_MEM; 1547 1548 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1, 1549 tco_res, 2, &spt_tco_platform_data, 1550 sizeof(spt_tco_platform_data)); 1551 } 1552 1553 static const struct itco_wdt_platform_data cnl_tco_platform_data = { 1554 .name = "Intel PCH", 1555 .version = 6, 1556 }; 1557 1558 static struct platform_device * 1559 i801_add_tco_cnl(struct i801_priv *priv, struct pci_dev *pci_dev, 1560 struct resource *tco_res) 1561 { 1562 return platform_device_register_resndata(&pci_dev->dev, 1563 "iTCO_wdt", -1, tco_res, 1, &cnl_tco_platform_data, 1564 sizeof(cnl_tco_platform_data)); 1565 } 1566 1567 static void i801_add_tco(struct i801_priv *priv) 1568 { 1569 struct pci_dev *pci_dev = priv->pci_dev; 1570 struct resource tco_res[2], *res; 1571 u32 tco_base, tco_ctl; 1572 1573 /* If we have ACPI based watchdog use that instead */ 1574 if (acpi_has_watchdog()) 1575 return; 1576 1577 if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL))) 1578 return; 1579 1580 pci_read_config_dword(pci_dev, TCOBASE, &tco_base); 1581 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl); 1582 if (!(tco_ctl & TCOCTL_EN)) 1583 return; 1584 1585 memset(tco_res, 0, sizeof(tco_res)); 1586 /* 1587 * Always populate the main iTCO IO resource here. The second entry 1588 * for NO_REBOOT MMIO is filled by the SPT specific function. 1589 */ 1590 res = &tco_res[0]; 1591 res->start = tco_base & ~1; 1592 res->end = res->start + 32 - 1; 1593 res->flags = IORESOURCE_IO; 1594 1595 if (priv->features & FEATURE_TCO_CNL) 1596 priv->tco_pdev = i801_add_tco_cnl(priv, pci_dev, tco_res); 1597 else 1598 priv->tco_pdev = i801_add_tco_spt(priv, pci_dev, tco_res); 1599 1600 if (IS_ERR(priv->tco_pdev)) 1601 dev_warn(&pci_dev->dev, "failed to create iTCO device\n"); 1602 } 1603 1604 #ifdef CONFIG_ACPI 1605 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv, 1606 acpi_physical_address address) 1607 { 1608 return address >= priv->smba && 1609 address <= pci_resource_end(priv->pci_dev, SMBBAR); 1610 } 1611 1612 static acpi_status 1613 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits, 1614 u64 *value, void *handler_context, void *region_context) 1615 { 1616 struct i801_priv *priv = handler_context; 1617 struct pci_dev *pdev = priv->pci_dev; 1618 acpi_status status; 1619 1620 /* 1621 * Once BIOS AML code touches the OpRegion we warn and inhibit any 1622 * further access from the driver itself. This device is now owned 1623 * by the system firmware. 1624 */ 1625 mutex_lock(&priv->acpi_lock); 1626 1627 if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) { 1628 priv->acpi_reserved = true; 1629 1630 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n"); 1631 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n"); 1632 1633 /* 1634 * BIOS is accessing the host controller so prevent it from 1635 * suspending automatically from now on. 1636 */ 1637 pm_runtime_get_sync(&pdev->dev); 1638 } 1639 1640 if ((function & ACPI_IO_MASK) == ACPI_READ) 1641 status = acpi_os_read_port(address, (u32 *)value, bits); 1642 else 1643 status = acpi_os_write_port(address, (u32)*value, bits); 1644 1645 mutex_unlock(&priv->acpi_lock); 1646 1647 return status; 1648 } 1649 1650 static int i801_acpi_probe(struct i801_priv *priv) 1651 { 1652 struct acpi_device *adev; 1653 acpi_status status; 1654 1655 adev = ACPI_COMPANION(&priv->pci_dev->dev); 1656 if (adev) { 1657 status = acpi_install_address_space_handler(adev->handle, 1658 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler, 1659 NULL, priv); 1660 if (ACPI_SUCCESS(status)) 1661 return 0; 1662 } 1663 1664 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]); 1665 } 1666 1667 static void i801_acpi_remove(struct i801_priv *priv) 1668 { 1669 struct acpi_device *adev; 1670 1671 adev = ACPI_COMPANION(&priv->pci_dev->dev); 1672 if (!adev) 1673 return; 1674 1675 acpi_remove_address_space_handler(adev->handle, 1676 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler); 1677 1678 mutex_lock(&priv->acpi_lock); 1679 if (priv->acpi_reserved) 1680 pm_runtime_put(&priv->pci_dev->dev); 1681 mutex_unlock(&priv->acpi_lock); 1682 } 1683 #else 1684 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; } 1685 static inline void i801_acpi_remove(struct i801_priv *priv) { } 1686 #endif 1687 1688 static void i801_setup_hstcfg(struct i801_priv *priv) 1689 { 1690 unsigned char hstcfg = priv->original_hstcfg; 1691 1692 hstcfg &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ 1693 hstcfg |= SMBHSTCFG_HST_EN; 1694 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hstcfg); 1695 } 1696 1697 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id) 1698 { 1699 int err, i; 1700 struct i801_priv *priv; 1701 1702 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL); 1703 if (!priv) 1704 return -ENOMEM; 1705 1706 i2c_set_adapdata(&priv->adapter, priv); 1707 priv->adapter.owner = THIS_MODULE; 1708 priv->adapter.class = i801_get_adapter_class(priv); 1709 priv->adapter.algo = &smbus_algorithm; 1710 priv->adapter.dev.parent = &dev->dev; 1711 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev)); 1712 priv->adapter.retries = 3; 1713 mutex_init(&priv->acpi_lock); 1714 1715 priv->pci_dev = dev; 1716 switch (dev->device) { 1717 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS: 1718 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS: 1719 case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS: 1720 case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS: 1721 case PCI_DEVICE_ID_INTEL_DNV_SMBUS: 1722 case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS: 1723 case PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS: 1724 priv->features |= FEATURE_BLOCK_PROC; 1725 priv->features |= FEATURE_I2C_BLOCK_READ; 1726 priv->features |= FEATURE_IRQ; 1727 priv->features |= FEATURE_SMBUS_PEC; 1728 priv->features |= FEATURE_BLOCK_BUFFER; 1729 priv->features |= FEATURE_TCO_SPT; 1730 priv->features |= FEATURE_HOST_NOTIFY; 1731 break; 1732 1733 case PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS: 1734 case PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS: 1735 case PCI_DEVICE_ID_INTEL_CDF_SMBUS: 1736 case PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS: 1737 case PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS: 1738 case PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS: 1739 case PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS: 1740 case PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS: 1741 case PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS: 1742 case PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS: 1743 case PCI_DEVICE_ID_INTEL_EBG_SMBUS: 1744 case PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS: 1745 case PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS: 1746 case PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS: 1747 priv->features |= FEATURE_BLOCK_PROC; 1748 priv->features |= FEATURE_I2C_BLOCK_READ; 1749 priv->features |= FEATURE_IRQ; 1750 priv->features |= FEATURE_SMBUS_PEC; 1751 priv->features |= FEATURE_BLOCK_BUFFER; 1752 priv->features |= FEATURE_TCO_CNL; 1753 priv->features |= FEATURE_HOST_NOTIFY; 1754 break; 1755 1756 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0: 1757 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1: 1758 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2: 1759 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0: 1760 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1: 1761 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2: 1762 priv->features |= FEATURE_IDF; 1763 fallthrough; 1764 default: 1765 priv->features |= FEATURE_BLOCK_PROC; 1766 priv->features |= FEATURE_I2C_BLOCK_READ; 1767 priv->features |= FEATURE_IRQ; 1768 fallthrough; 1769 case PCI_DEVICE_ID_INTEL_82801DB_3: 1770 priv->features |= FEATURE_SMBUS_PEC; 1771 priv->features |= FEATURE_BLOCK_BUFFER; 1772 fallthrough; 1773 case PCI_DEVICE_ID_INTEL_82801CA_3: 1774 priv->features |= FEATURE_HOST_NOTIFY; 1775 fallthrough; 1776 case PCI_DEVICE_ID_INTEL_82801BA_2: 1777 case PCI_DEVICE_ID_INTEL_82801AB_3: 1778 case PCI_DEVICE_ID_INTEL_82801AA_3: 1779 break; 1780 } 1781 1782 /* Disable features on user request */ 1783 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) { 1784 if (priv->features & disable_features & (1 << i)) 1785 dev_notice(&dev->dev, "%s disabled by user\n", 1786 i801_feature_names[i]); 1787 } 1788 priv->features &= ~disable_features; 1789 1790 err = pcim_enable_device(dev); 1791 if (err) { 1792 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", 1793 err); 1794 return err; 1795 } 1796 pcim_pin_device(dev); 1797 1798 /* Determine the address of the SMBus area */ 1799 priv->smba = pci_resource_start(dev, SMBBAR); 1800 if (!priv->smba) { 1801 dev_err(&dev->dev, 1802 "SMBus base address uninitialized, upgrade BIOS\n"); 1803 return -ENODEV; 1804 } 1805 1806 if (i801_acpi_probe(priv)) 1807 return -ENODEV; 1808 1809 err = pcim_iomap_regions(dev, 1 << SMBBAR, DRV_NAME); 1810 if (err) { 1811 dev_err(&dev->dev, 1812 "Failed to request SMBus region 0x%lx-0x%Lx\n", 1813 priv->smba, 1814 (unsigned long long)pci_resource_end(dev, SMBBAR)); 1815 i801_acpi_remove(priv); 1816 return err; 1817 } 1818 1819 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &priv->original_hstcfg); 1820 i801_setup_hstcfg(priv); 1821 if (!(priv->original_hstcfg & SMBHSTCFG_HST_EN)) 1822 dev_info(&dev->dev, "Enabling SMBus device\n"); 1823 1824 if (priv->original_hstcfg & SMBHSTCFG_SMB_SMI_EN) { 1825 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); 1826 /* Disable SMBus interrupt feature if SMBus using SMI# */ 1827 priv->features &= ~FEATURE_IRQ; 1828 } 1829 if (priv->original_hstcfg & SMBHSTCFG_SPD_WD) 1830 dev_info(&dev->dev, "SPD Write Disable is set\n"); 1831 1832 /* Clear special mode bits */ 1833 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) 1834 outb_p(inb_p(SMBAUXCTL(priv)) & 1835 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 1836 1837 /* Remember original Host Notify setting */ 1838 if (priv->features & FEATURE_HOST_NOTIFY) 1839 priv->original_slvcmd = inb_p(SMBSLVCMD(priv)); 1840 1841 /* Default timeout in interrupt mode: 200 ms */ 1842 priv->adapter.timeout = HZ / 5; 1843 1844 if (dev->irq == IRQ_NOTCONNECTED) 1845 priv->features &= ~FEATURE_IRQ; 1846 1847 if (priv->features & FEATURE_IRQ) { 1848 u16 pcictl, pcists; 1849 1850 /* Complain if an interrupt is already pending */ 1851 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists); 1852 if (pcists & PCI_STATUS_INTERRUPT) 1853 dev_warn(&dev->dev, "An interrupt is pending!\n"); 1854 1855 /* Check if interrupts have been disabled */ 1856 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pcictl); 1857 if (pcictl & PCI_COMMAND_INTX_DISABLE) { 1858 dev_info(&dev->dev, "Interrupts are disabled\n"); 1859 priv->features &= ~FEATURE_IRQ; 1860 } 1861 } 1862 1863 if (priv->features & FEATURE_IRQ) { 1864 init_completion(&priv->done); 1865 1866 err = devm_request_irq(&dev->dev, dev->irq, i801_isr, 1867 IRQF_SHARED, DRV_NAME, priv); 1868 if (err) { 1869 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n", 1870 dev->irq, err); 1871 priv->features &= ~FEATURE_IRQ; 1872 } 1873 } 1874 dev_info(&dev->dev, "SMBus using %s\n", 1875 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling"); 1876 1877 i801_add_tco(priv); 1878 1879 snprintf(priv->adapter.name, sizeof(priv->adapter.name), 1880 "SMBus I801 adapter at %04lx", priv->smba); 1881 err = i2c_add_adapter(&priv->adapter); 1882 if (err) { 1883 i801_acpi_remove(priv); 1884 return err; 1885 } 1886 1887 i801_enable_host_notify(&priv->adapter); 1888 1889 i801_probe_optional_slaves(priv); 1890 /* We ignore errors - multiplexing is optional */ 1891 i801_add_mux(priv); 1892 1893 pci_set_drvdata(dev, priv); 1894 1895 dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 1896 pm_runtime_set_autosuspend_delay(&dev->dev, 1000); 1897 pm_runtime_use_autosuspend(&dev->dev); 1898 pm_runtime_put_autosuspend(&dev->dev); 1899 pm_runtime_allow(&dev->dev); 1900 1901 return 0; 1902 } 1903 1904 static void i801_remove(struct pci_dev *dev) 1905 { 1906 struct i801_priv *priv = pci_get_drvdata(dev); 1907 1908 pm_runtime_forbid(&dev->dev); 1909 pm_runtime_get_noresume(&dev->dev); 1910 1911 i801_disable_host_notify(priv); 1912 i801_del_mux(priv); 1913 i2c_del_adapter(&priv->adapter); 1914 i801_acpi_remove(priv); 1915 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); 1916 1917 platform_device_unregister(priv->tco_pdev); 1918 1919 /* 1920 * do not call pci_disable_device(dev) since it can cause hard hangs on 1921 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) 1922 */ 1923 } 1924 1925 static void i801_shutdown(struct pci_dev *dev) 1926 { 1927 struct i801_priv *priv = pci_get_drvdata(dev); 1928 1929 /* Restore config registers to avoid hard hang on some systems */ 1930 i801_disable_host_notify(priv); 1931 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); 1932 } 1933 1934 #ifdef CONFIG_PM_SLEEP 1935 static int i801_suspend(struct device *dev) 1936 { 1937 struct i801_priv *priv = dev_get_drvdata(dev); 1938 1939 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, priv->original_hstcfg); 1940 return 0; 1941 } 1942 1943 static int i801_resume(struct device *dev) 1944 { 1945 struct i801_priv *priv = dev_get_drvdata(dev); 1946 1947 i801_setup_hstcfg(priv); 1948 i801_enable_host_notify(&priv->adapter); 1949 1950 return 0; 1951 } 1952 #endif 1953 1954 static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume); 1955 1956 static struct pci_driver i801_driver = { 1957 .name = DRV_NAME, 1958 .id_table = i801_ids, 1959 .probe = i801_probe, 1960 .remove = i801_remove, 1961 .shutdown = i801_shutdown, 1962 .driver = { 1963 .pm = &i801_pm_ops, 1964 }, 1965 }; 1966 1967 static int __init i2c_i801_init(void) 1968 { 1969 if (dmi_name_in_vendors("FUJITSU")) 1970 input_apanel_init(); 1971 return pci_register_driver(&i801_driver); 1972 } 1973 1974 static void __exit i2c_i801_exit(void) 1975 { 1976 pci_unregister_driver(&i801_driver); 1977 } 1978 1979 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>"); 1980 MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>"); 1981 MODULE_DESCRIPTION("I801 SMBus driver"); 1982 MODULE_LICENSE("GPL"); 1983 1984 module_init(i2c_i801_init); 1985 module_exit(i2c_i801_exit); 1986