1 /* 2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, 3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker 4 <mdsxyz123@yahoo.com> 5 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de> 6 Copyright (C) 2010 Intel Corporation, 7 David Woodhouse <dwmw2@infradead.org> 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 2 of the License, or 12 (at your option) any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 */ 19 20 /* 21 * Supports the following Intel I/O Controller Hubs (ICH): 22 * 23 * I/O Block I2C 24 * region SMBus Block proc. block 25 * Chip name PCI ID size PEC buffer call read 26 * --------------------------------------------------------------------------- 27 * 82801AA (ICH) 0x2413 16 no no no no 28 * 82801AB (ICH0) 0x2423 16 no no no no 29 * 82801BA (ICH2) 0x2443 16 no no no no 30 * 82801CA (ICH3) 0x2483 32 soft no no no 31 * 82801DB (ICH4) 0x24c3 32 hard yes no no 32 * 82801E (ICH5) 0x24d3 32 hard yes yes yes 33 * 6300ESB 0x25a4 32 hard yes yes yes 34 * 82801F (ICH6) 0x266a 32 hard yes yes yes 35 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes 36 * 82801G (ICH7) 0x27da 32 hard yes yes yes 37 * 82801H (ICH8) 0x283e 32 hard yes yes yes 38 * 82801I (ICH9) 0x2930 32 hard yes yes yes 39 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes 40 * ICH10 0x3a30 32 hard yes yes yes 41 * ICH10 0x3a60 32 hard yes yes yes 42 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes 43 * 6 Series (PCH) 0x1c22 32 hard yes yes yes 44 * Patsburg (PCH) 0x1d22 32 hard yes yes yes 45 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes 46 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes 47 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes 48 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes 49 * Panther Point (PCH) 0x1e22 32 hard yes yes yes 50 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes 51 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes 52 * Avoton (SOC) 0x1f3c 32 hard yes yes yes 53 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes 54 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes 55 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes 56 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes 57 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes 58 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes 59 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes 60 * BayTrail (SOC) 0x0f12 32 hard yes yes yes 61 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes 62 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes 63 * DNV (SOC) 0x19df 32 hard yes yes yes 64 * Broxton (SOC) 0x5ad4 32 hard yes yes yes 65 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes 66 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes 67 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes 68 * 69 * Features supported by this driver: 70 * Software PEC no 71 * Hardware PEC yes 72 * Block buffer yes 73 * Block process call transaction no 74 * I2C block read transaction yes (doesn't use the block buffer) 75 * Slave mode no 76 * SMBus Host Notify yes 77 * Interrupt processing yes 78 * 79 * See the file Documentation/i2c/busses/i2c-i801 for details. 80 */ 81 82 #include <linux/interrupt.h> 83 #include <linux/module.h> 84 #include <linux/pci.h> 85 #include <linux/kernel.h> 86 #include <linux/stddef.h> 87 #include <linux/delay.h> 88 #include <linux/ioport.h> 89 #include <linux/init.h> 90 #include <linux/i2c.h> 91 #include <linux/i2c-smbus.h> 92 #include <linux/acpi.h> 93 #include <linux/io.h> 94 #include <linux/dmi.h> 95 #include <linux/slab.h> 96 #include <linux/wait.h> 97 #include <linux/err.h> 98 #include <linux/platform_device.h> 99 #include <linux/platform_data/itco_wdt.h> 100 #include <linux/pm_runtime.h> 101 102 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 103 #include <linux/gpio.h> 104 #include <linux/i2c-mux-gpio.h> 105 #endif 106 107 /* I801 SMBus address offsets */ 108 #define SMBHSTSTS(p) (0 + (p)->smba) 109 #define SMBHSTCNT(p) (2 + (p)->smba) 110 #define SMBHSTCMD(p) (3 + (p)->smba) 111 #define SMBHSTADD(p) (4 + (p)->smba) 112 #define SMBHSTDAT0(p) (5 + (p)->smba) 113 #define SMBHSTDAT1(p) (6 + (p)->smba) 114 #define SMBBLKDAT(p) (7 + (p)->smba) 115 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */ 116 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */ 117 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */ 118 #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */ 119 #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */ 120 #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */ 121 122 /* PCI Address Constants */ 123 #define SMBBAR 4 124 #define SMBPCICTL 0x004 125 #define SMBPCISTS 0x006 126 #define SMBHSTCFG 0x040 127 #define TCOBASE 0x050 128 #define TCOCTL 0x054 129 130 #define ACPIBASE 0x040 131 #define ACPIBASE_SMI_OFF 0x030 132 #define ACPICTRL 0x044 133 #define ACPICTRL_EN 0x080 134 135 #define SBREG_BAR 0x10 136 #define SBREG_SMBCTRL 0xc6000c 137 138 /* Host status bits for SMBPCISTS */ 139 #define SMBPCISTS_INTS BIT(3) 140 141 /* Control bits for SMBPCICTL */ 142 #define SMBPCICTL_INTDIS BIT(10) 143 144 /* Host configuration bits for SMBHSTCFG */ 145 #define SMBHSTCFG_HST_EN BIT(0) 146 #define SMBHSTCFG_SMB_SMI_EN BIT(1) 147 #define SMBHSTCFG_I2C_EN BIT(2) 148 #define SMBHSTCFG_SPD_WD BIT(4) 149 150 /* TCO configuration bits for TCOCTL */ 151 #define TCOCTL_EN BIT(8) 152 153 /* Auxiliary status register bits, ICH4+ only */ 154 #define SMBAUXSTS_CRCE BIT(0) 155 #define SMBAUXSTS_STCO BIT(1) 156 157 /* Auxiliary control register bits, ICH4+ only */ 158 #define SMBAUXCTL_CRC BIT(0) 159 #define SMBAUXCTL_E32B BIT(1) 160 161 /* Other settings */ 162 #define MAX_RETRIES 400 163 164 /* I801 command constants */ 165 #define I801_QUICK 0x00 166 #define I801_BYTE 0x04 167 #define I801_BYTE_DATA 0x08 168 #define I801_WORD_DATA 0x0C 169 #define I801_PROC_CALL 0x10 /* unimplemented */ 170 #define I801_BLOCK_DATA 0x14 171 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ 172 173 /* I801 Host Control register bits */ 174 #define SMBHSTCNT_INTREN BIT(0) 175 #define SMBHSTCNT_KILL BIT(1) 176 #define SMBHSTCNT_LAST_BYTE BIT(5) 177 #define SMBHSTCNT_START BIT(6) 178 #define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */ 179 180 /* I801 Hosts Status register bits */ 181 #define SMBHSTSTS_BYTE_DONE BIT(7) 182 #define SMBHSTSTS_INUSE_STS BIT(6) 183 #define SMBHSTSTS_SMBALERT_STS BIT(5) 184 #define SMBHSTSTS_FAILED BIT(4) 185 #define SMBHSTSTS_BUS_ERR BIT(3) 186 #define SMBHSTSTS_DEV_ERR BIT(2) 187 #define SMBHSTSTS_INTR BIT(1) 188 #define SMBHSTSTS_HOST_BUSY BIT(0) 189 190 /* Host Notify Status register bits */ 191 #define SMBSLVSTS_HST_NTFY_STS BIT(0) 192 193 /* Host Notify Command register bits */ 194 #define SMBSLVCMD_HST_NTFY_INTREN BIT(0) 195 196 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \ 197 SMBHSTSTS_DEV_ERR) 198 199 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \ 200 STATUS_ERROR_FLAGS) 201 202 /* Older devices have their ID defined in <linux/pci_ids.h> */ 203 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12 204 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df 205 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 206 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 207 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */ 208 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70 209 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71 210 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72 211 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 212 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c 213 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292 214 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 215 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0 216 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 217 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4 218 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 219 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2 220 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22 221 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d 222 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e 223 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f 224 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22 225 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2 226 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23 227 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123 228 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3 229 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223 230 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3 231 232 struct i801_mux_config { 233 char *gpio_chip; 234 unsigned values[3]; 235 int n_values; 236 unsigned classes[3]; 237 unsigned gpios[2]; /* Relative to gpio_chip->base */ 238 int n_gpios; 239 }; 240 241 struct i801_priv { 242 struct i2c_adapter adapter; 243 unsigned long smba; 244 unsigned char original_hstcfg; 245 unsigned char original_slvcmd; 246 struct pci_dev *pci_dev; 247 unsigned int features; 248 249 /* isr processing */ 250 wait_queue_head_t waitq; 251 u8 status; 252 253 /* Command state used by isr for byte-by-byte block transactions */ 254 u8 cmd; 255 bool is_read; 256 int count; 257 int len; 258 u8 *data; 259 260 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 261 const struct i801_mux_config *mux_drvdata; 262 struct platform_device *mux_pdev; 263 #endif 264 struct platform_device *tco_pdev; 265 266 /* 267 * If set to true the host controller registers are reserved for 268 * ACPI AML use. Protected by acpi_lock. 269 */ 270 bool acpi_reserved; 271 struct mutex acpi_lock; 272 }; 273 274 #define FEATURE_SMBUS_PEC BIT(0) 275 #define FEATURE_BLOCK_BUFFER BIT(1) 276 #define FEATURE_BLOCK_PROC BIT(2) 277 #define FEATURE_I2C_BLOCK_READ BIT(3) 278 #define FEATURE_IRQ BIT(4) 279 #define FEATURE_HOST_NOTIFY BIT(5) 280 /* Not really a feature, but it's convenient to handle it as such */ 281 #define FEATURE_IDF BIT(15) 282 #define FEATURE_TCO BIT(16) 283 284 static const char *i801_feature_names[] = { 285 "SMBus PEC", 286 "Block buffer", 287 "Block process call", 288 "I2C block read", 289 "Interrupt", 290 "SMBus Host Notify", 291 }; 292 293 static unsigned int disable_features; 294 module_param(disable_features, uint, S_IRUGO | S_IWUSR); 295 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n" 296 "\t\t 0x01 disable SMBus PEC\n" 297 "\t\t 0x02 disable the block buffer\n" 298 "\t\t 0x08 disable the I2C block read functionality\n" 299 "\t\t 0x10 don't use interrupts\n" 300 "\t\t 0x20 disable SMBus Host Notify "); 301 302 /* Make sure the SMBus host is ready to start transmitting. 303 Return 0 if it is, -EBUSY if it is not. */ 304 static int i801_check_pre(struct i801_priv *priv) 305 { 306 int status; 307 308 status = inb_p(SMBHSTSTS(priv)); 309 if (status & SMBHSTSTS_HOST_BUSY) { 310 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n"); 311 return -EBUSY; 312 } 313 314 status &= STATUS_FLAGS; 315 if (status) { 316 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n", 317 status); 318 outb_p(status, SMBHSTSTS(priv)); 319 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS; 320 if (status) { 321 dev_err(&priv->pci_dev->dev, 322 "Failed clearing status flags (%02x)\n", 323 status); 324 return -EBUSY; 325 } 326 } 327 328 /* 329 * Clear CRC status if needed. 330 * During normal operation, i801_check_post() takes care 331 * of it after every operation. We do it here only in case 332 * the hardware was already in this state when the driver 333 * started. 334 */ 335 if (priv->features & FEATURE_SMBUS_PEC) { 336 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE; 337 if (status) { 338 dev_dbg(&priv->pci_dev->dev, 339 "Clearing aux status flags (%02x)\n", status); 340 outb_p(status, SMBAUXSTS(priv)); 341 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE; 342 if (status) { 343 dev_err(&priv->pci_dev->dev, 344 "Failed clearing aux status flags (%02x)\n", 345 status); 346 return -EBUSY; 347 } 348 } 349 } 350 351 return 0; 352 } 353 354 /* 355 * Convert the status register to an error code, and clear it. 356 * Note that status only contains the bits we want to clear, not the 357 * actual register value. 358 */ 359 static int i801_check_post(struct i801_priv *priv, int status) 360 { 361 int result = 0; 362 363 /* 364 * If the SMBus is still busy, we give up 365 * Note: This timeout condition only happens when using polling 366 * transactions. For interrupt operation, NAK/timeout is indicated by 367 * DEV_ERR. 368 */ 369 if (unlikely(status < 0)) { 370 dev_err(&priv->pci_dev->dev, "Transaction timeout\n"); 371 /* try to stop the current command */ 372 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n"); 373 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL, 374 SMBHSTCNT(priv)); 375 usleep_range(1000, 2000); 376 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL), 377 SMBHSTCNT(priv)); 378 379 /* Check if it worked */ 380 status = inb_p(SMBHSTSTS(priv)); 381 if ((status & SMBHSTSTS_HOST_BUSY) || 382 !(status & SMBHSTSTS_FAILED)) 383 dev_err(&priv->pci_dev->dev, 384 "Failed terminating the transaction\n"); 385 outb_p(STATUS_FLAGS, SMBHSTSTS(priv)); 386 return -ETIMEDOUT; 387 } 388 389 if (status & SMBHSTSTS_FAILED) { 390 result = -EIO; 391 dev_err(&priv->pci_dev->dev, "Transaction failed\n"); 392 } 393 if (status & SMBHSTSTS_DEV_ERR) { 394 /* 395 * This may be a PEC error, check and clear it. 396 * 397 * AUXSTS is handled differently from HSTSTS. 398 * For HSTSTS, i801_isr() or i801_wait_intr() 399 * has already cleared the error bits in hardware, 400 * and we are passed a copy of the original value 401 * in "status". 402 * For AUXSTS, the hardware register is left 403 * for us to handle here. 404 * This is asymmetric, slightly iffy, but safe, 405 * since all this code is serialized and the CRCE 406 * bit is harmless as long as it's cleared before 407 * the next operation. 408 */ 409 if ((priv->features & FEATURE_SMBUS_PEC) && 410 (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) { 411 outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv)); 412 result = -EBADMSG; 413 dev_dbg(&priv->pci_dev->dev, "PEC error\n"); 414 } else { 415 result = -ENXIO; 416 dev_dbg(&priv->pci_dev->dev, "No response\n"); 417 } 418 } 419 if (status & SMBHSTSTS_BUS_ERR) { 420 result = -EAGAIN; 421 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n"); 422 } 423 424 /* Clear status flags except BYTE_DONE, to be cleared by caller */ 425 outb_p(status, SMBHSTSTS(priv)); 426 427 return result; 428 } 429 430 /* Wait for BUSY being cleared and either INTR or an error flag being set */ 431 static int i801_wait_intr(struct i801_priv *priv) 432 { 433 int timeout = 0; 434 int status; 435 436 /* We will always wait for a fraction of a second! */ 437 do { 438 usleep_range(250, 500); 439 status = inb_p(SMBHSTSTS(priv)); 440 } while (((status & SMBHSTSTS_HOST_BUSY) || 441 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) && 442 (timeout++ < MAX_RETRIES)); 443 444 if (timeout > MAX_RETRIES) { 445 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n"); 446 return -ETIMEDOUT; 447 } 448 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR); 449 } 450 451 /* Wait for either BYTE_DONE or an error flag being set */ 452 static int i801_wait_byte_done(struct i801_priv *priv) 453 { 454 int timeout = 0; 455 int status; 456 457 /* We will always wait for a fraction of a second! */ 458 do { 459 usleep_range(250, 500); 460 status = inb_p(SMBHSTSTS(priv)); 461 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) && 462 (timeout++ < MAX_RETRIES)); 463 464 if (timeout > MAX_RETRIES) { 465 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n"); 466 return -ETIMEDOUT; 467 } 468 return status & STATUS_ERROR_FLAGS; 469 } 470 471 static int i801_transaction(struct i801_priv *priv, int xact) 472 { 473 int status; 474 int result; 475 const struct i2c_adapter *adap = &priv->adapter; 476 477 result = i801_check_pre(priv); 478 if (result < 0) 479 return result; 480 481 if (priv->features & FEATURE_IRQ) { 482 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START, 483 SMBHSTCNT(priv)); 484 result = wait_event_timeout(priv->waitq, 485 (status = priv->status), 486 adap->timeout); 487 if (!result) { 488 status = -ETIMEDOUT; 489 dev_warn(&priv->pci_dev->dev, 490 "Timeout waiting for interrupt!\n"); 491 } 492 priv->status = 0; 493 return i801_check_post(priv, status); 494 } 495 496 /* the current contents of SMBHSTCNT can be overwritten, since PEC, 497 * SMBSCMD are passed in xact */ 498 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv)); 499 500 status = i801_wait_intr(priv); 501 return i801_check_post(priv, status); 502 } 503 504 static int i801_block_transaction_by_block(struct i801_priv *priv, 505 union i2c_smbus_data *data, 506 char read_write, int hwpec) 507 { 508 int i, len; 509 int status; 510 511 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ 512 513 /* Use 32-byte buffer to process this transaction */ 514 if (read_write == I2C_SMBUS_WRITE) { 515 len = data->block[0]; 516 outb_p(len, SMBHSTDAT0(priv)); 517 for (i = 0; i < len; i++) 518 outb_p(data->block[i+1], SMBBLKDAT(priv)); 519 } 520 521 status = i801_transaction(priv, I801_BLOCK_DATA | 522 (hwpec ? SMBHSTCNT_PEC_EN : 0)); 523 if (status) 524 return status; 525 526 if (read_write == I2C_SMBUS_READ) { 527 len = inb_p(SMBHSTDAT0(priv)); 528 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) 529 return -EPROTO; 530 531 data->block[0] = len; 532 for (i = 0; i < len; i++) 533 data->block[i + 1] = inb_p(SMBBLKDAT(priv)); 534 } 535 return 0; 536 } 537 538 static void i801_isr_byte_done(struct i801_priv *priv) 539 { 540 if (priv->is_read) { 541 /* For SMBus block reads, length is received with first byte */ 542 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) && 543 (priv->count == 0)) { 544 priv->len = inb_p(SMBHSTDAT0(priv)); 545 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) { 546 dev_err(&priv->pci_dev->dev, 547 "Illegal SMBus block read size %d\n", 548 priv->len); 549 /* FIXME: Recover */ 550 priv->len = I2C_SMBUS_BLOCK_MAX; 551 } else { 552 dev_dbg(&priv->pci_dev->dev, 553 "SMBus block read size is %d\n", 554 priv->len); 555 } 556 priv->data[-1] = priv->len; 557 } 558 559 /* Read next byte */ 560 if (priv->count < priv->len) 561 priv->data[priv->count++] = inb(SMBBLKDAT(priv)); 562 else 563 dev_dbg(&priv->pci_dev->dev, 564 "Discarding extra byte on block read\n"); 565 566 /* Set LAST_BYTE for last byte of read transaction */ 567 if (priv->count == priv->len - 1) 568 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE, 569 SMBHSTCNT(priv)); 570 } else if (priv->count < priv->len - 1) { 571 /* Write next byte, except for IRQ after last byte */ 572 outb_p(priv->data[++priv->count], SMBBLKDAT(priv)); 573 } 574 575 /* Clear BYTE_DONE to continue with next byte */ 576 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 577 } 578 579 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv) 580 { 581 unsigned short addr; 582 583 addr = inb_p(SMBNTFDADD(priv)) >> 1; 584 585 /* 586 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba) 587 * always returns 0. Our current implementation doesn't provide 588 * data, so we just ignore it. 589 */ 590 i2c_handle_smbus_host_notify(&priv->adapter, addr); 591 592 /* clear Host Notify bit and return */ 593 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 594 return IRQ_HANDLED; 595 } 596 597 /* 598 * There are three kinds of interrupts: 599 * 600 * 1) i801 signals transaction completion with one of these interrupts: 601 * INTR - Success 602 * DEV_ERR - Invalid command, NAK or communication timeout 603 * BUS_ERR - SMI# transaction collision 604 * FAILED - transaction was canceled due to a KILL request 605 * When any of these occur, update ->status and wake up the waitq. 606 * ->status must be cleared before kicking off the next transaction. 607 * 608 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt 609 * occurs for each byte of a byte-by-byte to prepare the next byte. 610 * 611 * 3) Host Notify interrupts 612 */ 613 static irqreturn_t i801_isr(int irq, void *dev_id) 614 { 615 struct i801_priv *priv = dev_id; 616 u16 pcists; 617 u8 status; 618 619 /* Confirm this is our interrupt */ 620 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); 621 if (!(pcists & SMBPCISTS_INTS)) 622 return IRQ_NONE; 623 624 if (priv->features & FEATURE_HOST_NOTIFY) { 625 status = inb_p(SMBSLVSTS(priv)); 626 if (status & SMBSLVSTS_HST_NTFY_STS) 627 return i801_host_notify_isr(priv); 628 } 629 630 status = inb_p(SMBHSTSTS(priv)); 631 if (status & SMBHSTSTS_BYTE_DONE) 632 i801_isr_byte_done(priv); 633 634 /* 635 * Clear irq sources and report transaction result. 636 * ->status must be cleared before the next transaction is started. 637 */ 638 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS; 639 if (status) { 640 outb_p(status, SMBHSTSTS(priv)); 641 priv->status = status; 642 wake_up(&priv->waitq); 643 } 644 645 return IRQ_HANDLED; 646 } 647 648 /* 649 * For "byte-by-byte" block transactions: 650 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1 651 * I2C read uses cmd=I801_I2C_BLOCK_DATA 652 */ 653 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, 654 union i2c_smbus_data *data, 655 char read_write, int command, 656 int hwpec) 657 { 658 int i, len; 659 int smbcmd; 660 int status; 661 int result; 662 const struct i2c_adapter *adap = &priv->adapter; 663 664 result = i801_check_pre(priv); 665 if (result < 0) 666 return result; 667 668 len = data->block[0]; 669 670 if (read_write == I2C_SMBUS_WRITE) { 671 outb_p(len, SMBHSTDAT0(priv)); 672 outb_p(data->block[1], SMBBLKDAT(priv)); 673 } 674 675 if (command == I2C_SMBUS_I2C_BLOCK_DATA && 676 read_write == I2C_SMBUS_READ) 677 smbcmd = I801_I2C_BLOCK_DATA; 678 else 679 smbcmd = I801_BLOCK_DATA; 680 681 if (priv->features & FEATURE_IRQ) { 682 priv->is_read = (read_write == I2C_SMBUS_READ); 683 if (len == 1 && priv->is_read) 684 smbcmd |= SMBHSTCNT_LAST_BYTE; 685 priv->cmd = smbcmd | SMBHSTCNT_INTREN; 686 priv->len = len; 687 priv->count = 0; 688 priv->data = &data->block[1]; 689 690 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv)); 691 result = wait_event_timeout(priv->waitq, 692 (status = priv->status), 693 adap->timeout); 694 if (!result) { 695 status = -ETIMEDOUT; 696 dev_warn(&priv->pci_dev->dev, 697 "Timeout waiting for interrupt!\n"); 698 } 699 priv->status = 0; 700 return i801_check_post(priv, status); 701 } 702 703 for (i = 1; i <= len; i++) { 704 if (i == len && read_write == I2C_SMBUS_READ) 705 smbcmd |= SMBHSTCNT_LAST_BYTE; 706 outb_p(smbcmd, SMBHSTCNT(priv)); 707 708 if (i == 1) 709 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START, 710 SMBHSTCNT(priv)); 711 712 status = i801_wait_byte_done(priv); 713 if (status) 714 goto exit; 715 716 if (i == 1 && read_write == I2C_SMBUS_READ 717 && command != I2C_SMBUS_I2C_BLOCK_DATA) { 718 len = inb_p(SMBHSTDAT0(priv)); 719 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { 720 dev_err(&priv->pci_dev->dev, 721 "Illegal SMBus block read size %d\n", 722 len); 723 /* Recover */ 724 while (inb_p(SMBHSTSTS(priv)) & 725 SMBHSTSTS_HOST_BUSY) 726 outb_p(SMBHSTSTS_BYTE_DONE, 727 SMBHSTSTS(priv)); 728 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); 729 return -EPROTO; 730 } 731 data->block[0] = len; 732 } 733 734 /* Retrieve/store value in SMBBLKDAT */ 735 if (read_write == I2C_SMBUS_READ) 736 data->block[i] = inb_p(SMBBLKDAT(priv)); 737 if (read_write == I2C_SMBUS_WRITE && i+1 <= len) 738 outb_p(data->block[i+1], SMBBLKDAT(priv)); 739 740 /* signals SMBBLKDAT ready */ 741 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 742 } 743 744 status = i801_wait_intr(priv); 745 exit: 746 return i801_check_post(priv, status); 747 } 748 749 static int i801_set_block_buffer_mode(struct i801_priv *priv) 750 { 751 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv)); 752 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0) 753 return -EIO; 754 return 0; 755 } 756 757 /* Block transaction function */ 758 static int i801_block_transaction(struct i801_priv *priv, 759 union i2c_smbus_data *data, char read_write, 760 int command, int hwpec) 761 { 762 int result = 0; 763 unsigned char hostc; 764 765 if (command == I2C_SMBUS_I2C_BLOCK_DATA) { 766 if (read_write == I2C_SMBUS_WRITE) { 767 /* set I2C_EN bit in configuration register */ 768 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc); 769 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, 770 hostc | SMBHSTCFG_I2C_EN); 771 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) { 772 dev_err(&priv->pci_dev->dev, 773 "I2C block read is unsupported!\n"); 774 return -EOPNOTSUPP; 775 } 776 } 777 778 if (read_write == I2C_SMBUS_WRITE 779 || command == I2C_SMBUS_I2C_BLOCK_DATA) { 780 if (data->block[0] < 1) 781 data->block[0] = 1; 782 if (data->block[0] > I2C_SMBUS_BLOCK_MAX) 783 data->block[0] = I2C_SMBUS_BLOCK_MAX; 784 } else { 785 data->block[0] = 32; /* max for SMBus block reads */ 786 } 787 788 /* Experience has shown that the block buffer can only be used for 789 SMBus (not I2C) block transactions, even though the datasheet 790 doesn't mention this limitation. */ 791 if ((priv->features & FEATURE_BLOCK_BUFFER) 792 && command != I2C_SMBUS_I2C_BLOCK_DATA 793 && i801_set_block_buffer_mode(priv) == 0) 794 result = i801_block_transaction_by_block(priv, data, 795 read_write, hwpec); 796 else 797 result = i801_block_transaction_byte_by_byte(priv, data, 798 read_write, 799 command, hwpec); 800 801 if (command == I2C_SMBUS_I2C_BLOCK_DATA 802 && read_write == I2C_SMBUS_WRITE) { 803 /* restore saved configuration register value */ 804 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc); 805 } 806 return result; 807 } 808 809 /* Return negative errno on error. */ 810 static s32 i801_access(struct i2c_adapter *adap, u16 addr, 811 unsigned short flags, char read_write, u8 command, 812 int size, union i2c_smbus_data *data) 813 { 814 int hwpec; 815 int block = 0; 816 int ret = 0, xact = 0; 817 struct i801_priv *priv = i2c_get_adapdata(adap); 818 819 mutex_lock(&priv->acpi_lock); 820 if (priv->acpi_reserved) { 821 mutex_unlock(&priv->acpi_lock); 822 return -EBUSY; 823 } 824 825 pm_runtime_get_sync(&priv->pci_dev->dev); 826 827 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) 828 && size != I2C_SMBUS_QUICK 829 && size != I2C_SMBUS_I2C_BLOCK_DATA; 830 831 switch (size) { 832 case I2C_SMBUS_QUICK: 833 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 834 SMBHSTADD(priv)); 835 xact = I801_QUICK; 836 break; 837 case I2C_SMBUS_BYTE: 838 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 839 SMBHSTADD(priv)); 840 if (read_write == I2C_SMBUS_WRITE) 841 outb_p(command, SMBHSTCMD(priv)); 842 xact = I801_BYTE; 843 break; 844 case I2C_SMBUS_BYTE_DATA: 845 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 846 SMBHSTADD(priv)); 847 outb_p(command, SMBHSTCMD(priv)); 848 if (read_write == I2C_SMBUS_WRITE) 849 outb_p(data->byte, SMBHSTDAT0(priv)); 850 xact = I801_BYTE_DATA; 851 break; 852 case I2C_SMBUS_WORD_DATA: 853 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 854 SMBHSTADD(priv)); 855 outb_p(command, SMBHSTCMD(priv)); 856 if (read_write == I2C_SMBUS_WRITE) { 857 outb_p(data->word & 0xff, SMBHSTDAT0(priv)); 858 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); 859 } 860 xact = I801_WORD_DATA; 861 break; 862 case I2C_SMBUS_BLOCK_DATA: 863 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 864 SMBHSTADD(priv)); 865 outb_p(command, SMBHSTCMD(priv)); 866 block = 1; 867 break; 868 case I2C_SMBUS_I2C_BLOCK_DATA: 869 /* 870 * NB: page 240 of ICH5 datasheet shows that the R/#W 871 * bit should be cleared here, even when reading. 872 * However if SPD Write Disable is set (Lynx Point and later), 873 * the read will fail if we don't set the R/#W bit. 874 */ 875 outb_p(((addr & 0x7f) << 1) | 876 ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ? 877 (read_write & 0x01) : 0), 878 SMBHSTADD(priv)); 879 if (read_write == I2C_SMBUS_READ) { 880 /* NB: page 240 of ICH5 datasheet also shows 881 * that DATA1 is the cmd field when reading */ 882 outb_p(command, SMBHSTDAT1(priv)); 883 } else 884 outb_p(command, SMBHSTCMD(priv)); 885 block = 1; 886 break; 887 default: 888 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n", 889 size); 890 ret = -EOPNOTSUPP; 891 goto out; 892 } 893 894 if (hwpec) /* enable/disable hardware PEC */ 895 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv)); 896 else 897 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC), 898 SMBAUXCTL(priv)); 899 900 if (block) 901 ret = i801_block_transaction(priv, data, read_write, size, 902 hwpec); 903 else 904 ret = i801_transaction(priv, xact); 905 906 /* Some BIOSes don't like it when PEC is enabled at reboot or resume 907 time, so we forcibly disable it after every transaction. Turn off 908 E32B for the same reason. */ 909 if (hwpec || block) 910 outb_p(inb_p(SMBAUXCTL(priv)) & 911 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 912 913 if (block) 914 goto out; 915 if (ret) 916 goto out; 917 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK)) 918 goto out; 919 920 switch (xact & 0x7f) { 921 case I801_BYTE: /* Result put in SMBHSTDAT0 */ 922 case I801_BYTE_DATA: 923 data->byte = inb_p(SMBHSTDAT0(priv)); 924 break; 925 case I801_WORD_DATA: 926 data->word = inb_p(SMBHSTDAT0(priv)) + 927 (inb_p(SMBHSTDAT1(priv)) << 8); 928 break; 929 } 930 931 out: 932 pm_runtime_mark_last_busy(&priv->pci_dev->dev); 933 pm_runtime_put_autosuspend(&priv->pci_dev->dev); 934 mutex_unlock(&priv->acpi_lock); 935 return ret; 936 } 937 938 939 static u32 i801_func(struct i2c_adapter *adapter) 940 { 941 struct i801_priv *priv = i2c_get_adapdata(adapter); 942 943 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 944 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 945 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | 946 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | 947 ((priv->features & FEATURE_I2C_BLOCK_READ) ? 948 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) | 949 ((priv->features & FEATURE_HOST_NOTIFY) ? 950 I2C_FUNC_SMBUS_HOST_NOTIFY : 0); 951 } 952 953 static void i801_enable_host_notify(struct i2c_adapter *adapter) 954 { 955 struct i801_priv *priv = i2c_get_adapdata(adapter); 956 957 if (!(priv->features & FEATURE_HOST_NOTIFY)) 958 return; 959 960 priv->original_slvcmd = inb_p(SMBSLVCMD(priv)); 961 962 if (!(SMBSLVCMD_HST_NTFY_INTREN & priv->original_slvcmd)) 963 outb_p(SMBSLVCMD_HST_NTFY_INTREN | priv->original_slvcmd, 964 SMBSLVCMD(priv)); 965 966 /* clear Host Notify bit to allow a new notification */ 967 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 968 } 969 970 static void i801_disable_host_notify(struct i801_priv *priv) 971 { 972 if (!(priv->features & FEATURE_HOST_NOTIFY)) 973 return; 974 975 outb_p(priv->original_slvcmd, SMBSLVCMD(priv)); 976 } 977 978 static const struct i2c_algorithm smbus_algorithm = { 979 .smbus_xfer = i801_access, 980 .functionality = i801_func, 981 }; 982 983 static const struct pci_device_id i801_ids[] = { 984 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) }, 985 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) }, 986 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) }, 987 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) }, 988 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) }, 989 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) }, 990 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) }, 991 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) }, 992 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) }, 993 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) }, 994 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) }, 995 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) }, 996 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) }, 997 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) }, 998 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) }, 999 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) }, 1000 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) }, 1001 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) }, 1002 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) }, 1003 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) }, 1004 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) }, 1005 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) }, 1006 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) }, 1007 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) }, 1008 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) }, 1009 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) }, 1010 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) }, 1011 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) }, 1012 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) }, 1013 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) }, 1014 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) }, 1015 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) }, 1016 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) }, 1017 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) }, 1018 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) }, 1019 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) }, 1020 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) }, 1021 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) }, 1022 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) }, 1023 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) }, 1024 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) }, 1025 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) }, 1026 { 0, } 1027 }; 1028 1029 MODULE_DEVICE_TABLE(pci, i801_ids); 1030 1031 #if defined CONFIG_X86 && defined CONFIG_DMI 1032 static unsigned char apanel_addr; 1033 1034 /* Scan the system ROM for the signature "FJKEYINF" */ 1035 static __init const void __iomem *bios_signature(const void __iomem *bios) 1036 { 1037 ssize_t offset; 1038 const unsigned char signature[] = "FJKEYINF"; 1039 1040 for (offset = 0; offset < 0x10000; offset += 0x10) { 1041 if (check_signature(bios + offset, signature, 1042 sizeof(signature)-1)) 1043 return bios + offset; 1044 } 1045 return NULL; 1046 } 1047 1048 static void __init input_apanel_init(void) 1049 { 1050 void __iomem *bios; 1051 const void __iomem *p; 1052 1053 bios = ioremap(0xF0000, 0x10000); /* Can't fail */ 1054 p = bios_signature(bios); 1055 if (p) { 1056 /* just use the first address */ 1057 apanel_addr = readb(p + 8 + 3) >> 1; 1058 } 1059 iounmap(bios); 1060 } 1061 1062 struct dmi_onboard_device_info { 1063 const char *name; 1064 u8 type; 1065 unsigned short i2c_addr; 1066 const char *i2c_type; 1067 }; 1068 1069 static const struct dmi_onboard_device_info dmi_devices[] = { 1070 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" }, 1071 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" }, 1072 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" }, 1073 }; 1074 1075 static void dmi_check_onboard_device(u8 type, const char *name, 1076 struct i2c_adapter *adap) 1077 { 1078 int i; 1079 struct i2c_board_info info; 1080 1081 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) { 1082 /* & ~0x80, ignore enabled/disabled bit */ 1083 if ((type & ~0x80) != dmi_devices[i].type) 1084 continue; 1085 if (strcasecmp(name, dmi_devices[i].name)) 1086 continue; 1087 1088 memset(&info, 0, sizeof(struct i2c_board_info)); 1089 info.addr = dmi_devices[i].i2c_addr; 1090 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); 1091 i2c_new_device(adap, &info); 1092 break; 1093 } 1094 } 1095 1096 /* We use our own function to check for onboard devices instead of 1097 dmi_find_device() as some buggy BIOS's have the devices we are interested 1098 in marked as disabled */ 1099 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap) 1100 { 1101 int i, count; 1102 1103 if (dm->type != 10) 1104 return; 1105 1106 count = (dm->length - sizeof(struct dmi_header)) / 2; 1107 for (i = 0; i < count; i++) { 1108 const u8 *d = (char *)(dm + 1) + (i * 2); 1109 const char *name = ((char *) dm) + dm->length; 1110 u8 type = d[0]; 1111 u8 s = d[1]; 1112 1113 if (!s) 1114 continue; 1115 s--; 1116 while (s > 0 && name[0]) { 1117 name += strlen(name) + 1; 1118 s--; 1119 } 1120 if (name[0] == 0) /* Bogus string reference */ 1121 continue; 1122 1123 dmi_check_onboard_device(type, name, adap); 1124 } 1125 } 1126 1127 /* Register optional slaves */ 1128 static void i801_probe_optional_slaves(struct i801_priv *priv) 1129 { 1130 /* Only register slaves on main SMBus channel */ 1131 if (priv->features & FEATURE_IDF) 1132 return; 1133 1134 if (apanel_addr) { 1135 struct i2c_board_info info; 1136 1137 memset(&info, 0, sizeof(struct i2c_board_info)); 1138 info.addr = apanel_addr; 1139 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE); 1140 i2c_new_device(&priv->adapter, &info); 1141 } 1142 1143 if (dmi_name_in_vendors("FUJITSU")) 1144 dmi_walk(dmi_check_onboard_devices, &priv->adapter); 1145 } 1146 #else 1147 static void __init input_apanel_init(void) {} 1148 static void i801_probe_optional_slaves(struct i801_priv *priv) {} 1149 #endif /* CONFIG_X86 && CONFIG_DMI */ 1150 1151 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 1152 static struct i801_mux_config i801_mux_config_asus_z8_d12 = { 1153 .gpio_chip = "gpio_ich", 1154 .values = { 0x02, 0x03 }, 1155 .n_values = 2, 1156 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD }, 1157 .gpios = { 52, 53 }, 1158 .n_gpios = 2, 1159 }; 1160 1161 static struct i801_mux_config i801_mux_config_asus_z8_d18 = { 1162 .gpio_chip = "gpio_ich", 1163 .values = { 0x02, 0x03, 0x01 }, 1164 .n_values = 3, 1165 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD }, 1166 .gpios = { 52, 53 }, 1167 .n_gpios = 2, 1168 }; 1169 1170 static const struct dmi_system_id mux_dmi_table[] = { 1171 { 1172 .matches = { 1173 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1174 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"), 1175 }, 1176 .driver_data = &i801_mux_config_asus_z8_d12, 1177 }, 1178 { 1179 .matches = { 1180 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1181 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"), 1182 }, 1183 .driver_data = &i801_mux_config_asus_z8_d12, 1184 }, 1185 { 1186 .matches = { 1187 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1188 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"), 1189 }, 1190 .driver_data = &i801_mux_config_asus_z8_d12, 1191 }, 1192 { 1193 .matches = { 1194 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1195 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"), 1196 }, 1197 .driver_data = &i801_mux_config_asus_z8_d12, 1198 }, 1199 { 1200 .matches = { 1201 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1202 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"), 1203 }, 1204 .driver_data = &i801_mux_config_asus_z8_d12, 1205 }, 1206 { 1207 .matches = { 1208 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1209 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"), 1210 }, 1211 .driver_data = &i801_mux_config_asus_z8_d12, 1212 }, 1213 { 1214 .matches = { 1215 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1216 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"), 1217 }, 1218 .driver_data = &i801_mux_config_asus_z8_d18, 1219 }, 1220 { 1221 .matches = { 1222 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1223 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"), 1224 }, 1225 .driver_data = &i801_mux_config_asus_z8_d18, 1226 }, 1227 { 1228 .matches = { 1229 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1230 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"), 1231 }, 1232 .driver_data = &i801_mux_config_asus_z8_d12, 1233 }, 1234 { } 1235 }; 1236 1237 /* Setup multiplexing if needed */ 1238 static int i801_add_mux(struct i801_priv *priv) 1239 { 1240 struct device *dev = &priv->adapter.dev; 1241 const struct i801_mux_config *mux_config; 1242 struct i2c_mux_gpio_platform_data gpio_data; 1243 int err; 1244 1245 if (!priv->mux_drvdata) 1246 return 0; 1247 mux_config = priv->mux_drvdata; 1248 1249 /* Prepare the platform data */ 1250 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data)); 1251 gpio_data.parent = priv->adapter.nr; 1252 gpio_data.values = mux_config->values; 1253 gpio_data.n_values = mux_config->n_values; 1254 gpio_data.classes = mux_config->classes; 1255 gpio_data.gpio_chip = mux_config->gpio_chip; 1256 gpio_data.gpios = mux_config->gpios; 1257 gpio_data.n_gpios = mux_config->n_gpios; 1258 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE; 1259 1260 /* Register the mux device */ 1261 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio", 1262 PLATFORM_DEVID_AUTO, &gpio_data, 1263 sizeof(struct i2c_mux_gpio_platform_data)); 1264 if (IS_ERR(priv->mux_pdev)) { 1265 err = PTR_ERR(priv->mux_pdev); 1266 priv->mux_pdev = NULL; 1267 dev_err(dev, "Failed to register i2c-mux-gpio device\n"); 1268 return err; 1269 } 1270 1271 return 0; 1272 } 1273 1274 static void i801_del_mux(struct i801_priv *priv) 1275 { 1276 if (priv->mux_pdev) 1277 platform_device_unregister(priv->mux_pdev); 1278 } 1279 1280 static unsigned int i801_get_adapter_class(struct i801_priv *priv) 1281 { 1282 const struct dmi_system_id *id; 1283 const struct i801_mux_config *mux_config; 1284 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 1285 int i; 1286 1287 id = dmi_first_match(mux_dmi_table); 1288 if (id) { 1289 /* Remove branch classes from trunk */ 1290 mux_config = id->driver_data; 1291 for (i = 0; i < mux_config->n_values; i++) 1292 class &= ~mux_config->classes[i]; 1293 1294 /* Remember for later */ 1295 priv->mux_drvdata = mux_config; 1296 } 1297 1298 return class; 1299 } 1300 #else 1301 static inline int i801_add_mux(struct i801_priv *priv) { return 0; } 1302 static inline void i801_del_mux(struct i801_priv *priv) { } 1303 1304 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv) 1305 { 1306 return I2C_CLASS_HWMON | I2C_CLASS_SPD; 1307 } 1308 #endif 1309 1310 static const struct itco_wdt_platform_data tco_platform_data = { 1311 .name = "Intel PCH", 1312 .version = 4, 1313 }; 1314 1315 static DEFINE_SPINLOCK(p2sb_spinlock); 1316 1317 static void i801_add_tco(struct i801_priv *priv) 1318 { 1319 struct pci_dev *pci_dev = priv->pci_dev; 1320 struct resource tco_res[3], *res; 1321 struct platform_device *pdev; 1322 unsigned int devfn; 1323 u32 tco_base, tco_ctl; 1324 u32 base_addr, ctrl_val; 1325 u64 base64_addr; 1326 1327 if (!(priv->features & FEATURE_TCO)) 1328 return; 1329 1330 pci_read_config_dword(pci_dev, TCOBASE, &tco_base); 1331 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl); 1332 if (!(tco_ctl & TCOCTL_EN)) 1333 return; 1334 1335 memset(tco_res, 0, sizeof(tco_res)); 1336 1337 res = &tco_res[ICH_RES_IO_TCO]; 1338 res->start = tco_base & ~1; 1339 res->end = res->start + 32 - 1; 1340 res->flags = IORESOURCE_IO; 1341 1342 /* 1343 * Power Management registers. 1344 */ 1345 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 2); 1346 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPIBASE, &base_addr); 1347 1348 res = &tco_res[ICH_RES_IO_SMI]; 1349 res->start = (base_addr & ~1) + ACPIBASE_SMI_OFF; 1350 res->end = res->start + 3; 1351 res->flags = IORESOURCE_IO; 1352 1353 /* 1354 * Enable the ACPI I/O space. 1355 */ 1356 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPICTRL, &ctrl_val); 1357 ctrl_val |= ACPICTRL_EN; 1358 pci_bus_write_config_dword(pci_dev->bus, devfn, ACPICTRL, ctrl_val); 1359 1360 /* 1361 * We must access the NO_REBOOT bit over the Primary to Sideband 1362 * bridge (P2SB). The BIOS prevents the P2SB device from being 1363 * enumerated by the PCI subsystem, so we need to unhide/hide it 1364 * to lookup the P2SB BAR. 1365 */ 1366 spin_lock(&p2sb_spinlock); 1367 1368 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1); 1369 1370 /* Unhide the P2SB device */ 1371 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0); 1372 1373 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr); 1374 base64_addr = base_addr & 0xfffffff0; 1375 1376 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr); 1377 base64_addr |= (u64)base_addr << 32; 1378 1379 /* Hide the P2SB device */ 1380 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x1); 1381 spin_unlock(&p2sb_spinlock); 1382 1383 res = &tco_res[ICH_RES_MEM_OFF]; 1384 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL; 1385 res->end = res->start + 3; 1386 res->flags = IORESOURCE_MEM; 1387 1388 pdev = platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1, 1389 tco_res, 3, &tco_platform_data, 1390 sizeof(tco_platform_data)); 1391 if (IS_ERR(pdev)) { 1392 dev_warn(&pci_dev->dev, "failed to create iTCO device\n"); 1393 return; 1394 } 1395 1396 priv->tco_pdev = pdev; 1397 } 1398 1399 #ifdef CONFIG_ACPI 1400 static acpi_status 1401 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits, 1402 u64 *value, void *handler_context, void *region_context) 1403 { 1404 struct i801_priv *priv = handler_context; 1405 struct pci_dev *pdev = priv->pci_dev; 1406 acpi_status status; 1407 1408 /* 1409 * Once BIOS AML code touches the OpRegion we warn and inhibit any 1410 * further access from the driver itself. This device is now owned 1411 * by the system firmware. 1412 */ 1413 mutex_lock(&priv->acpi_lock); 1414 1415 if (!priv->acpi_reserved) { 1416 priv->acpi_reserved = true; 1417 1418 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n"); 1419 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n"); 1420 1421 /* 1422 * BIOS is accessing the host controller so prevent it from 1423 * suspending automatically from now on. 1424 */ 1425 pm_runtime_get_sync(&pdev->dev); 1426 } 1427 1428 if ((function & ACPI_IO_MASK) == ACPI_READ) 1429 status = acpi_os_read_port(address, (u32 *)value, bits); 1430 else 1431 status = acpi_os_write_port(address, (u32)*value, bits); 1432 1433 mutex_unlock(&priv->acpi_lock); 1434 1435 return status; 1436 } 1437 1438 static int i801_acpi_probe(struct i801_priv *priv) 1439 { 1440 struct acpi_device *adev; 1441 acpi_status status; 1442 1443 adev = ACPI_COMPANION(&priv->pci_dev->dev); 1444 if (adev) { 1445 status = acpi_install_address_space_handler(adev->handle, 1446 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler, 1447 NULL, priv); 1448 if (ACPI_SUCCESS(status)) 1449 return 0; 1450 } 1451 1452 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]); 1453 } 1454 1455 static void i801_acpi_remove(struct i801_priv *priv) 1456 { 1457 struct acpi_device *adev; 1458 1459 adev = ACPI_COMPANION(&priv->pci_dev->dev); 1460 if (!adev) 1461 return; 1462 1463 acpi_remove_address_space_handler(adev->handle, 1464 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler); 1465 1466 mutex_lock(&priv->acpi_lock); 1467 if (priv->acpi_reserved) 1468 pm_runtime_put(&priv->pci_dev->dev); 1469 mutex_unlock(&priv->acpi_lock); 1470 } 1471 #else 1472 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; } 1473 static inline void i801_acpi_remove(struct i801_priv *priv) { } 1474 #endif 1475 1476 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id) 1477 { 1478 unsigned char temp; 1479 int err, i; 1480 struct i801_priv *priv; 1481 1482 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL); 1483 if (!priv) 1484 return -ENOMEM; 1485 1486 i2c_set_adapdata(&priv->adapter, priv); 1487 priv->adapter.owner = THIS_MODULE; 1488 priv->adapter.class = i801_get_adapter_class(priv); 1489 priv->adapter.algo = &smbus_algorithm; 1490 priv->adapter.dev.parent = &dev->dev; 1491 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev)); 1492 priv->adapter.retries = 3; 1493 mutex_init(&priv->acpi_lock); 1494 1495 priv->pci_dev = dev; 1496 switch (dev->device) { 1497 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS: 1498 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS: 1499 case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS: 1500 case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS: 1501 case PCI_DEVICE_ID_INTEL_DNV_SMBUS: 1502 case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS: 1503 priv->features |= FEATURE_I2C_BLOCK_READ; 1504 priv->features |= FEATURE_IRQ; 1505 priv->features |= FEATURE_SMBUS_PEC; 1506 priv->features |= FEATURE_BLOCK_BUFFER; 1507 /* If we have ACPI based watchdog use that instead */ 1508 if (!acpi_has_watchdog()) 1509 priv->features |= FEATURE_TCO; 1510 priv->features |= FEATURE_HOST_NOTIFY; 1511 break; 1512 1513 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0: 1514 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1: 1515 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2: 1516 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0: 1517 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1: 1518 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2: 1519 priv->features |= FEATURE_IDF; 1520 /* fall through */ 1521 default: 1522 priv->features |= FEATURE_I2C_BLOCK_READ; 1523 priv->features |= FEATURE_IRQ; 1524 /* fall through */ 1525 case PCI_DEVICE_ID_INTEL_82801DB_3: 1526 priv->features |= FEATURE_SMBUS_PEC; 1527 priv->features |= FEATURE_BLOCK_BUFFER; 1528 /* fall through */ 1529 case PCI_DEVICE_ID_INTEL_82801CA_3: 1530 priv->features |= FEATURE_HOST_NOTIFY; 1531 /* fall through */ 1532 case PCI_DEVICE_ID_INTEL_82801BA_2: 1533 case PCI_DEVICE_ID_INTEL_82801AB_3: 1534 case PCI_DEVICE_ID_INTEL_82801AA_3: 1535 break; 1536 } 1537 1538 /* Disable features on user request */ 1539 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) { 1540 if (priv->features & disable_features & (1 << i)) 1541 dev_notice(&dev->dev, "%s disabled by user\n", 1542 i801_feature_names[i]); 1543 } 1544 priv->features &= ~disable_features; 1545 1546 err = pcim_enable_device(dev); 1547 if (err) { 1548 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", 1549 err); 1550 return err; 1551 } 1552 pcim_pin_device(dev); 1553 1554 /* Determine the address of the SMBus area */ 1555 priv->smba = pci_resource_start(dev, SMBBAR); 1556 if (!priv->smba) { 1557 dev_err(&dev->dev, 1558 "SMBus base address uninitialized, upgrade BIOS\n"); 1559 return -ENODEV; 1560 } 1561 1562 if (i801_acpi_probe(priv)) 1563 return -ENODEV; 1564 1565 err = pcim_iomap_regions(dev, 1 << SMBBAR, 1566 dev_driver_string(&dev->dev)); 1567 if (err) { 1568 dev_err(&dev->dev, 1569 "Failed to request SMBus region 0x%lx-0x%Lx\n", 1570 priv->smba, 1571 (unsigned long long)pci_resource_end(dev, SMBBAR)); 1572 i801_acpi_remove(priv); 1573 return err; 1574 } 1575 1576 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp); 1577 priv->original_hstcfg = temp; 1578 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ 1579 if (!(temp & SMBHSTCFG_HST_EN)) { 1580 dev_info(&dev->dev, "Enabling SMBus device\n"); 1581 temp |= SMBHSTCFG_HST_EN; 1582 } 1583 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp); 1584 1585 if (temp & SMBHSTCFG_SMB_SMI_EN) { 1586 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); 1587 /* Disable SMBus interrupt feature if SMBus using SMI# */ 1588 priv->features &= ~FEATURE_IRQ; 1589 } 1590 if (temp & SMBHSTCFG_SPD_WD) 1591 dev_info(&dev->dev, "SPD Write Disable is set\n"); 1592 1593 /* Clear special mode bits */ 1594 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) 1595 outb_p(inb_p(SMBAUXCTL(priv)) & 1596 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 1597 1598 /* Default timeout in interrupt mode: 200 ms */ 1599 priv->adapter.timeout = HZ / 5; 1600 1601 if (priv->features & FEATURE_IRQ) { 1602 u16 pcictl, pcists; 1603 1604 /* Complain if an interrupt is already pending */ 1605 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); 1606 if (pcists & SMBPCISTS_INTS) 1607 dev_warn(&dev->dev, "An interrupt is pending!\n"); 1608 1609 /* Check if interrupts have been disabled */ 1610 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl); 1611 if (pcictl & SMBPCICTL_INTDIS) { 1612 dev_info(&dev->dev, "Interrupts are disabled\n"); 1613 priv->features &= ~FEATURE_IRQ; 1614 } 1615 } 1616 1617 if (priv->features & FEATURE_IRQ) { 1618 init_waitqueue_head(&priv->waitq); 1619 1620 err = devm_request_irq(&dev->dev, dev->irq, i801_isr, 1621 IRQF_SHARED, 1622 dev_driver_string(&dev->dev), priv); 1623 if (err) { 1624 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n", 1625 dev->irq, err); 1626 priv->features &= ~FEATURE_IRQ; 1627 } 1628 } 1629 dev_info(&dev->dev, "SMBus using %s\n", 1630 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling"); 1631 1632 i801_add_tco(priv); 1633 1634 snprintf(priv->adapter.name, sizeof(priv->adapter.name), 1635 "SMBus I801 adapter at %04lx", priv->smba); 1636 err = i2c_add_adapter(&priv->adapter); 1637 if (err) { 1638 i801_acpi_remove(priv); 1639 return err; 1640 } 1641 1642 i801_enable_host_notify(&priv->adapter); 1643 1644 i801_probe_optional_slaves(priv); 1645 /* We ignore errors - multiplexing is optional */ 1646 i801_add_mux(priv); 1647 1648 pci_set_drvdata(dev, priv); 1649 1650 pm_runtime_set_autosuspend_delay(&dev->dev, 1000); 1651 pm_runtime_use_autosuspend(&dev->dev); 1652 pm_runtime_put_autosuspend(&dev->dev); 1653 pm_runtime_allow(&dev->dev); 1654 1655 return 0; 1656 } 1657 1658 static void i801_remove(struct pci_dev *dev) 1659 { 1660 struct i801_priv *priv = pci_get_drvdata(dev); 1661 1662 pm_runtime_forbid(&dev->dev); 1663 pm_runtime_get_noresume(&dev->dev); 1664 1665 i801_disable_host_notify(priv); 1666 i801_del_mux(priv); 1667 i2c_del_adapter(&priv->adapter); 1668 i801_acpi_remove(priv); 1669 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); 1670 1671 platform_device_unregister(priv->tco_pdev); 1672 1673 /* 1674 * do not call pci_disable_device(dev) since it can cause hard hangs on 1675 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) 1676 */ 1677 } 1678 1679 #ifdef CONFIG_PM 1680 static int i801_suspend(struct device *dev) 1681 { 1682 struct pci_dev *pci_dev = to_pci_dev(dev); 1683 struct i801_priv *priv = pci_get_drvdata(pci_dev); 1684 1685 pci_write_config_byte(pci_dev, SMBHSTCFG, priv->original_hstcfg); 1686 return 0; 1687 } 1688 1689 static int i801_resume(struct device *dev) 1690 { 1691 struct pci_dev *pci_dev = to_pci_dev(dev); 1692 struct i801_priv *priv = pci_get_drvdata(pci_dev); 1693 1694 i801_enable_host_notify(&priv->adapter); 1695 1696 return 0; 1697 } 1698 #endif 1699 1700 static UNIVERSAL_DEV_PM_OPS(i801_pm_ops, i801_suspend, 1701 i801_resume, NULL); 1702 1703 static struct pci_driver i801_driver = { 1704 .name = "i801_smbus", 1705 .id_table = i801_ids, 1706 .probe = i801_probe, 1707 .remove = i801_remove, 1708 .driver = { 1709 .pm = &i801_pm_ops, 1710 }, 1711 }; 1712 1713 static int __init i2c_i801_init(void) 1714 { 1715 if (dmi_name_in_vendors("FUJITSU")) 1716 input_apanel_init(); 1717 return pci_register_driver(&i801_driver); 1718 } 1719 1720 static void __exit i2c_i801_exit(void) 1721 { 1722 pci_unregister_driver(&i801_driver); 1723 } 1724 1725 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>"); 1726 MODULE_DESCRIPTION("I801 SMBus driver"); 1727 MODULE_LICENSE("GPL"); 1728 1729 module_init(i2c_i801_init); 1730 module_exit(i2c_i801_exit); 1731