1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, 4 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker 5 <mdsxyz123@yahoo.com> 6 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de> 7 Copyright (C) 2010 Intel Corporation, 8 David Woodhouse <dwmw2@infradead.org> 9 10 */ 11 12 /* 13 * Supports the following Intel I/O Controller Hubs (ICH): 14 * 15 * I/O Block I2C 16 * region SMBus Block proc. block 17 * Chip name PCI ID size PEC buffer call read 18 * --------------------------------------------------------------------------- 19 * 82801AA (ICH) 0x2413 16 no no no no 20 * 82801AB (ICH0) 0x2423 16 no no no no 21 * 82801BA (ICH2) 0x2443 16 no no no no 22 * 82801CA (ICH3) 0x2483 32 soft no no no 23 * 82801DB (ICH4) 0x24c3 32 hard yes no no 24 * 82801E (ICH5) 0x24d3 32 hard yes yes yes 25 * 6300ESB 0x25a4 32 hard yes yes yes 26 * 82801F (ICH6) 0x266a 32 hard yes yes yes 27 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes 28 * 82801G (ICH7) 0x27da 32 hard yes yes yes 29 * 82801H (ICH8) 0x283e 32 hard yes yes yes 30 * 82801I (ICH9) 0x2930 32 hard yes yes yes 31 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes 32 * ICH10 0x3a30 32 hard yes yes yes 33 * ICH10 0x3a60 32 hard yes yes yes 34 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes 35 * 6 Series (PCH) 0x1c22 32 hard yes yes yes 36 * Patsburg (PCH) 0x1d22 32 hard yes yes yes 37 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes 38 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes 39 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes 40 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes 41 * Panther Point (PCH) 0x1e22 32 hard yes yes yes 42 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes 43 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes 44 * Avoton (SOC) 0x1f3c 32 hard yes yes yes 45 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes 46 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes 47 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes 48 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes 49 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes 50 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes 51 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes 52 * BayTrail (SOC) 0x0f12 32 hard yes yes yes 53 * Braswell (SOC) 0x2292 32 hard yes yes yes 54 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes 55 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes 56 * DNV (SOC) 0x19df 32 hard yes yes yes 57 * Emmitsburg (PCH) 0x1bc9 32 hard yes yes yes 58 * Broxton (SOC) 0x5ad4 32 hard yes yes yes 59 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes 60 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes 61 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes 62 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes 63 * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes 64 * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes 65 * Cedar Fork (PCH) 0x18df 32 hard yes yes yes 66 * Ice Lake-LP (PCH) 0x34a3 32 hard yes yes yes 67 * Ice Lake-N (PCH) 0x38a3 32 hard yes yes yes 68 * Comet Lake (PCH) 0x02a3 32 hard yes yes yes 69 * Comet Lake-H (PCH) 0x06a3 32 hard yes yes yes 70 * Elkhart Lake (PCH) 0x4b23 32 hard yes yes yes 71 * Tiger Lake-LP (PCH) 0xa0a3 32 hard yes yes yes 72 * Tiger Lake-H (PCH) 0x43a3 32 hard yes yes yes 73 * Jasper Lake (SOC) 0x4da3 32 hard yes yes yes 74 * Comet Lake-V (PCH) 0xa3a3 32 hard yes yes yes 75 * Alder Lake-S (PCH) 0x7aa3 32 hard yes yes yes 76 * Alder Lake-P (PCH) 0x51a3 32 hard yes yes yes 77 * Alder Lake-M (PCH) 0x54a3 32 hard yes yes yes 78 * 79 * Features supported by this driver: 80 * Software PEC no 81 * Hardware PEC yes 82 * Block buffer yes 83 * Block process call transaction yes 84 * I2C block read transaction yes (doesn't use the block buffer) 85 * Slave mode no 86 * SMBus Host Notify yes 87 * Interrupt processing yes 88 * 89 * See the file Documentation/i2c/busses/i2c-i801.rst for details. 90 */ 91 92 #define DRV_NAME "i801_smbus" 93 94 #include <linux/interrupt.h> 95 #include <linux/module.h> 96 #include <linux/pci.h> 97 #include <linux/kernel.h> 98 #include <linux/stddef.h> 99 #include <linux/delay.h> 100 #include <linux/ioport.h> 101 #include <linux/init.h> 102 #include <linux/i2c.h> 103 #include <linux/i2c-smbus.h> 104 #include <linux/acpi.h> 105 #include <linux/io.h> 106 #include <linux/dmi.h> 107 #include <linux/slab.h> 108 #include <linux/string.h> 109 #include <linux/completion.h> 110 #include <linux/err.h> 111 #include <linux/platform_device.h> 112 #include <linux/platform_data/itco_wdt.h> 113 #include <linux/pm_runtime.h> 114 #include <linux/mutex.h> 115 116 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 117 #include <linux/gpio/machine.h> 118 #include <linux/platform_data/i2c-mux-gpio.h> 119 #endif 120 121 /* I801 SMBus address offsets */ 122 #define SMBHSTSTS(p) (0 + (p)->smba) 123 #define SMBHSTCNT(p) (2 + (p)->smba) 124 #define SMBHSTCMD(p) (3 + (p)->smba) 125 #define SMBHSTADD(p) (4 + (p)->smba) 126 #define SMBHSTDAT0(p) (5 + (p)->smba) 127 #define SMBHSTDAT1(p) (6 + (p)->smba) 128 #define SMBBLKDAT(p) (7 + (p)->smba) 129 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */ 130 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */ 131 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */ 132 #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */ 133 #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */ 134 #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */ 135 136 /* PCI Address Constants */ 137 #define SMBBAR 4 138 #define SMBHSTCFG 0x040 139 #define TCOBASE 0x050 140 #define TCOCTL 0x054 141 142 #define SBREG_BAR 0x10 143 #define SBREG_SMBCTRL 0xc6000c 144 #define SBREG_SMBCTRL_DNV 0xcf000c 145 146 /* Host configuration bits for SMBHSTCFG */ 147 #define SMBHSTCFG_HST_EN BIT(0) 148 #define SMBHSTCFG_SMB_SMI_EN BIT(1) 149 #define SMBHSTCFG_I2C_EN BIT(2) 150 #define SMBHSTCFG_SPD_WD BIT(4) 151 152 /* TCO configuration bits for TCOCTL */ 153 #define TCOCTL_EN BIT(8) 154 155 /* Auxiliary status register bits, ICH4+ only */ 156 #define SMBAUXSTS_CRCE BIT(0) 157 #define SMBAUXSTS_STCO BIT(1) 158 159 /* Auxiliary control register bits, ICH4+ only */ 160 #define SMBAUXCTL_CRC BIT(0) 161 #define SMBAUXCTL_E32B BIT(1) 162 163 /* I801 command constants */ 164 #define I801_QUICK 0x00 165 #define I801_BYTE 0x04 166 #define I801_BYTE_DATA 0x08 167 #define I801_WORD_DATA 0x0C 168 #define I801_PROC_CALL 0x10 /* unimplemented */ 169 #define I801_BLOCK_DATA 0x14 170 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ 171 #define I801_BLOCK_PROC_CALL 0x1C 172 173 /* I801 Host Control register bits */ 174 #define SMBHSTCNT_INTREN BIT(0) 175 #define SMBHSTCNT_KILL BIT(1) 176 #define SMBHSTCNT_LAST_BYTE BIT(5) 177 #define SMBHSTCNT_START BIT(6) 178 #define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */ 179 180 /* I801 Hosts Status register bits */ 181 #define SMBHSTSTS_BYTE_DONE BIT(7) 182 #define SMBHSTSTS_INUSE_STS BIT(6) 183 #define SMBHSTSTS_SMBALERT_STS BIT(5) 184 #define SMBHSTSTS_FAILED BIT(4) 185 #define SMBHSTSTS_BUS_ERR BIT(3) 186 #define SMBHSTSTS_DEV_ERR BIT(2) 187 #define SMBHSTSTS_INTR BIT(1) 188 #define SMBHSTSTS_HOST_BUSY BIT(0) 189 190 /* Host Notify Status register bits */ 191 #define SMBSLVSTS_HST_NTFY_STS BIT(0) 192 193 /* Host Notify Command register bits */ 194 #define SMBSLVCMD_HST_NTFY_INTREN BIT(0) 195 196 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \ 197 SMBHSTSTS_DEV_ERR) 198 199 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \ 200 STATUS_ERROR_FLAGS) 201 202 /* Older devices have their ID defined in <linux/pci_ids.h> */ 203 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS 0x02a3 204 #define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS 0x06a3 205 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12 206 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df 207 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df 208 #define PCI_DEVICE_ID_INTEL_EBG_SMBUS 0x1bc9 209 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 210 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 211 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */ 212 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70 213 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71 214 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72 215 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 216 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c 217 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292 218 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 219 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0 220 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4 221 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS 0x34a3 222 #define PCI_DEVICE_ID_INTEL_ICELAKE_N_SMBUS 0x38a3 223 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 224 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS 0x43a3 225 #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS 0x4b23 226 #define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS 0x4da3 227 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS 0x51a3 228 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS 0x54a3 229 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4 230 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS 0x7aa3 231 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 232 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2 233 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22 234 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d 235 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e 236 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f 237 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22 238 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2 239 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23 240 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3 241 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS 0xa0a3 242 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123 243 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3 244 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223 245 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3 246 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323 247 #define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS 0xa3a3 248 249 struct i801_mux_config { 250 char *gpio_chip; 251 unsigned values[3]; 252 int n_values; 253 unsigned classes[3]; 254 unsigned gpios[2]; /* Relative to gpio_chip->base */ 255 int n_gpios; 256 }; 257 258 struct i801_priv { 259 struct i2c_adapter adapter; 260 unsigned long smba; 261 unsigned char original_hstcfg; 262 unsigned char original_slvcmd; 263 struct pci_dev *pci_dev; 264 unsigned int features; 265 266 /* isr processing */ 267 struct completion done; 268 u8 status; 269 270 /* Command state used by isr for byte-by-byte block transactions */ 271 u8 cmd; 272 bool is_read; 273 int count; 274 int len; 275 u8 *data; 276 277 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 278 const struct i801_mux_config *mux_drvdata; 279 struct platform_device *mux_pdev; 280 struct gpiod_lookup_table *lookup; 281 #endif 282 struct platform_device *tco_pdev; 283 284 /* 285 * If set to true the host controller registers are reserved for 286 * ACPI AML use. Protected by acpi_lock. 287 */ 288 bool acpi_reserved; 289 struct mutex acpi_lock; 290 }; 291 292 #define FEATURE_SMBUS_PEC BIT(0) 293 #define FEATURE_BLOCK_BUFFER BIT(1) 294 #define FEATURE_BLOCK_PROC BIT(2) 295 #define FEATURE_I2C_BLOCK_READ BIT(3) 296 #define FEATURE_IRQ BIT(4) 297 #define FEATURE_HOST_NOTIFY BIT(5) 298 /* Not really a feature, but it's convenient to handle it as such */ 299 #define FEATURE_IDF BIT(15) 300 #define FEATURE_TCO_SPT BIT(16) 301 #define FEATURE_TCO_CNL BIT(17) 302 303 static const char *i801_feature_names[] = { 304 "SMBus PEC", 305 "Block buffer", 306 "Block process call", 307 "I2C block read", 308 "Interrupt", 309 "SMBus Host Notify", 310 }; 311 312 static unsigned int disable_features; 313 module_param(disable_features, uint, S_IRUGO | S_IWUSR); 314 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n" 315 "\t\t 0x01 disable SMBus PEC\n" 316 "\t\t 0x02 disable the block buffer\n" 317 "\t\t 0x08 disable the I2C block read functionality\n" 318 "\t\t 0x10 don't use interrupts\n" 319 "\t\t 0x20 disable SMBus Host Notify "); 320 321 /* Make sure the SMBus host is ready to start transmitting. 322 Return 0 if it is, -EBUSY if it is not. */ 323 static int i801_check_pre(struct i801_priv *priv) 324 { 325 int status; 326 327 status = inb_p(SMBHSTSTS(priv)); 328 if (status & SMBHSTSTS_HOST_BUSY) { 329 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n"); 330 return -EBUSY; 331 } 332 333 status &= STATUS_FLAGS; 334 if (status) { 335 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n", 336 status); 337 outb_p(status, SMBHSTSTS(priv)); 338 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS; 339 if (status) { 340 dev_err(&priv->pci_dev->dev, 341 "Failed clearing status flags (%02x)\n", 342 status); 343 return -EBUSY; 344 } 345 } 346 347 /* 348 * Clear CRC status if needed. 349 * During normal operation, i801_check_post() takes care 350 * of it after every operation. We do it here only in case 351 * the hardware was already in this state when the driver 352 * started. 353 */ 354 if (priv->features & FEATURE_SMBUS_PEC) { 355 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE; 356 if (status) { 357 dev_dbg(&priv->pci_dev->dev, 358 "Clearing aux status flags (%02x)\n", status); 359 outb_p(status, SMBAUXSTS(priv)); 360 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE; 361 if (status) { 362 dev_err(&priv->pci_dev->dev, 363 "Failed clearing aux status flags (%02x)\n", 364 status); 365 return -EBUSY; 366 } 367 } 368 } 369 370 return 0; 371 } 372 373 /* 374 * Convert the status register to an error code, and clear it. 375 * Note that status only contains the bits we want to clear, not the 376 * actual register value. 377 */ 378 static int i801_check_post(struct i801_priv *priv, int status) 379 { 380 int result = 0; 381 382 /* 383 * If the SMBus is still busy, we give up 384 * Note: This timeout condition only happens when using polling 385 * transactions. For interrupt operation, NAK/timeout is indicated by 386 * DEV_ERR. 387 */ 388 if (unlikely(status < 0)) { 389 dev_err(&priv->pci_dev->dev, "Transaction timeout\n"); 390 /* try to stop the current command */ 391 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n"); 392 outb_p(SMBHSTCNT_KILL, SMBHSTCNT(priv)); 393 usleep_range(1000, 2000); 394 outb_p(0, SMBHSTCNT(priv)); 395 396 /* Check if it worked */ 397 status = inb_p(SMBHSTSTS(priv)); 398 if ((status & SMBHSTSTS_HOST_BUSY) || 399 !(status & SMBHSTSTS_FAILED)) 400 dev_err(&priv->pci_dev->dev, 401 "Failed terminating the transaction\n"); 402 outb_p(STATUS_FLAGS, SMBHSTSTS(priv)); 403 return -ETIMEDOUT; 404 } 405 406 if (status & SMBHSTSTS_FAILED) { 407 result = -EIO; 408 dev_err(&priv->pci_dev->dev, "Transaction failed\n"); 409 } 410 if (status & SMBHSTSTS_DEV_ERR) { 411 /* 412 * This may be a PEC error, check and clear it. 413 * 414 * AUXSTS is handled differently from HSTSTS. 415 * For HSTSTS, i801_isr() or i801_wait_intr() 416 * has already cleared the error bits in hardware, 417 * and we are passed a copy of the original value 418 * in "status". 419 * For AUXSTS, the hardware register is left 420 * for us to handle here. 421 * This is asymmetric, slightly iffy, but safe, 422 * since all this code is serialized and the CRCE 423 * bit is harmless as long as it's cleared before 424 * the next operation. 425 */ 426 if ((priv->features & FEATURE_SMBUS_PEC) && 427 (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) { 428 outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv)); 429 result = -EBADMSG; 430 dev_dbg(&priv->pci_dev->dev, "PEC error\n"); 431 } else { 432 result = -ENXIO; 433 dev_dbg(&priv->pci_dev->dev, "No response\n"); 434 } 435 } 436 if (status & SMBHSTSTS_BUS_ERR) { 437 result = -EAGAIN; 438 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n"); 439 } 440 441 /* Clear status flags except BYTE_DONE, to be cleared by caller */ 442 outb_p(status, SMBHSTSTS(priv)); 443 444 return result; 445 } 446 447 /* Wait for BUSY being cleared and either INTR or an error flag being set */ 448 static int i801_wait_intr(struct i801_priv *priv) 449 { 450 unsigned long timeout = jiffies + priv->adapter.timeout; 451 int status, busy; 452 453 do { 454 usleep_range(250, 500); 455 status = inb_p(SMBHSTSTS(priv)); 456 busy = status & SMBHSTSTS_HOST_BUSY; 457 status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR; 458 if (!busy && status) 459 return status; 460 } while (time_is_after_eq_jiffies(timeout)); 461 462 return -ETIMEDOUT; 463 } 464 465 /* Wait for either BYTE_DONE or an error flag being set */ 466 static int i801_wait_byte_done(struct i801_priv *priv) 467 { 468 unsigned long timeout = jiffies + priv->adapter.timeout; 469 int status; 470 471 do { 472 usleep_range(250, 500); 473 status = inb_p(SMBHSTSTS(priv)); 474 if (status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) 475 return status & STATUS_ERROR_FLAGS; 476 } while (time_is_after_eq_jiffies(timeout)); 477 478 return -ETIMEDOUT; 479 } 480 481 static int i801_transaction(struct i801_priv *priv, int xact) 482 { 483 int status; 484 unsigned long result; 485 const struct i2c_adapter *adap = &priv->adapter; 486 487 status = i801_check_pre(priv); 488 if (status < 0) 489 return status; 490 491 if (priv->features & FEATURE_IRQ) { 492 reinit_completion(&priv->done); 493 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START, 494 SMBHSTCNT(priv)); 495 result = wait_for_completion_timeout(&priv->done, adap->timeout); 496 return i801_check_post(priv, result ? priv->status : -ETIMEDOUT); 497 } 498 499 /* the current contents of SMBHSTCNT can be overwritten, since PEC, 500 * SMBSCMD are passed in xact */ 501 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv)); 502 503 status = i801_wait_intr(priv); 504 return i801_check_post(priv, status); 505 } 506 507 static int i801_block_transaction_by_block(struct i801_priv *priv, 508 union i2c_smbus_data *data, 509 char read_write, int command) 510 { 511 int i, len, status, xact; 512 513 switch (command) { 514 case I2C_SMBUS_BLOCK_PROC_CALL: 515 xact = I801_BLOCK_PROC_CALL; 516 break; 517 case I2C_SMBUS_BLOCK_DATA: 518 xact = I801_BLOCK_DATA; 519 break; 520 default: 521 return -EOPNOTSUPP; 522 } 523 524 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ 525 526 /* Use 32-byte buffer to process this transaction */ 527 if (read_write == I2C_SMBUS_WRITE) { 528 len = data->block[0]; 529 outb_p(len, SMBHSTDAT0(priv)); 530 for (i = 0; i < len; i++) 531 outb_p(data->block[i+1], SMBBLKDAT(priv)); 532 } 533 534 status = i801_transaction(priv, xact); 535 if (status) 536 return status; 537 538 if (read_write == I2C_SMBUS_READ || 539 command == I2C_SMBUS_BLOCK_PROC_CALL) { 540 len = inb_p(SMBHSTDAT0(priv)); 541 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) 542 return -EPROTO; 543 544 data->block[0] = len; 545 for (i = 0; i < len; i++) 546 data->block[i + 1] = inb_p(SMBBLKDAT(priv)); 547 } 548 return 0; 549 } 550 551 static void i801_isr_byte_done(struct i801_priv *priv) 552 { 553 if (priv->is_read) { 554 /* For SMBus block reads, length is received with first byte */ 555 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) && 556 (priv->count == 0)) { 557 priv->len = inb_p(SMBHSTDAT0(priv)); 558 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) { 559 dev_err(&priv->pci_dev->dev, 560 "Illegal SMBus block read size %d\n", 561 priv->len); 562 /* FIXME: Recover */ 563 priv->len = I2C_SMBUS_BLOCK_MAX; 564 } 565 priv->data[-1] = priv->len; 566 } 567 568 /* Read next byte */ 569 if (priv->count < priv->len) 570 priv->data[priv->count++] = inb(SMBBLKDAT(priv)); 571 else 572 dev_dbg(&priv->pci_dev->dev, 573 "Discarding extra byte on block read\n"); 574 575 /* Set LAST_BYTE for last byte of read transaction */ 576 if (priv->count == priv->len - 1) 577 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE, 578 SMBHSTCNT(priv)); 579 } else if (priv->count < priv->len - 1) { 580 /* Write next byte, except for IRQ after last byte */ 581 outb_p(priv->data[++priv->count], SMBBLKDAT(priv)); 582 } 583 584 /* Clear BYTE_DONE to continue with next byte */ 585 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 586 } 587 588 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv) 589 { 590 unsigned short addr; 591 592 addr = inb_p(SMBNTFDADD(priv)) >> 1; 593 594 /* 595 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba) 596 * always returns 0. Our current implementation doesn't provide 597 * data, so we just ignore it. 598 */ 599 i2c_handle_smbus_host_notify(&priv->adapter, addr); 600 601 /* clear Host Notify bit and return */ 602 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 603 return IRQ_HANDLED; 604 } 605 606 /* 607 * There are three kinds of interrupts: 608 * 609 * 1) i801 signals transaction completion with one of these interrupts: 610 * INTR - Success 611 * DEV_ERR - Invalid command, NAK or communication timeout 612 * BUS_ERR - SMI# transaction collision 613 * FAILED - transaction was canceled due to a KILL request 614 * When any of these occur, update ->status and signal completion. 615 * ->status must be cleared before kicking off the next transaction. 616 * 617 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt 618 * occurs for each byte of a byte-by-byte to prepare the next byte. 619 * 620 * 3) Host Notify interrupts 621 */ 622 static irqreturn_t i801_isr(int irq, void *dev_id) 623 { 624 struct i801_priv *priv = dev_id; 625 u16 pcists; 626 u8 status; 627 628 /* Confirm this is our interrupt */ 629 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists); 630 if (!(pcists & PCI_STATUS_INTERRUPT)) 631 return IRQ_NONE; 632 633 if (priv->features & FEATURE_HOST_NOTIFY) { 634 status = inb_p(SMBSLVSTS(priv)); 635 if (status & SMBSLVSTS_HST_NTFY_STS) 636 return i801_host_notify_isr(priv); 637 } 638 639 status = inb_p(SMBHSTSTS(priv)); 640 if (status & SMBHSTSTS_BYTE_DONE) 641 i801_isr_byte_done(priv); 642 643 /* 644 * Clear irq sources and report transaction result. 645 * ->status must be cleared before the next transaction is started. 646 */ 647 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS; 648 if (status) { 649 outb_p(status, SMBHSTSTS(priv)); 650 priv->status = status; 651 complete(&priv->done); 652 } 653 654 return IRQ_HANDLED; 655 } 656 657 /* 658 * For "byte-by-byte" block transactions: 659 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1 660 * I2C read uses cmd=I801_I2C_BLOCK_DATA 661 */ 662 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, 663 union i2c_smbus_data *data, 664 char read_write, int command) 665 { 666 int i, len; 667 int smbcmd; 668 int status; 669 unsigned long result; 670 const struct i2c_adapter *adap = &priv->adapter; 671 672 if (command == I2C_SMBUS_BLOCK_PROC_CALL) 673 return -EOPNOTSUPP; 674 675 status = i801_check_pre(priv); 676 if (status < 0) 677 return status; 678 679 len = data->block[0]; 680 681 if (read_write == I2C_SMBUS_WRITE) { 682 outb_p(len, SMBHSTDAT0(priv)); 683 outb_p(data->block[1], SMBBLKDAT(priv)); 684 } 685 686 if (command == I2C_SMBUS_I2C_BLOCK_DATA && 687 read_write == I2C_SMBUS_READ) 688 smbcmd = I801_I2C_BLOCK_DATA; 689 else 690 smbcmd = I801_BLOCK_DATA; 691 692 if (priv->features & FEATURE_IRQ) { 693 priv->is_read = (read_write == I2C_SMBUS_READ); 694 if (len == 1 && priv->is_read) 695 smbcmd |= SMBHSTCNT_LAST_BYTE; 696 priv->cmd = smbcmd | SMBHSTCNT_INTREN; 697 priv->len = len; 698 priv->count = 0; 699 priv->data = &data->block[1]; 700 701 reinit_completion(&priv->done); 702 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv)); 703 result = wait_for_completion_timeout(&priv->done, adap->timeout); 704 return i801_check_post(priv, result ? priv->status : -ETIMEDOUT); 705 } 706 707 for (i = 1; i <= len; i++) { 708 if (i == len && read_write == I2C_SMBUS_READ) 709 smbcmd |= SMBHSTCNT_LAST_BYTE; 710 outb_p(smbcmd, SMBHSTCNT(priv)); 711 712 if (i == 1) 713 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START, 714 SMBHSTCNT(priv)); 715 716 status = i801_wait_byte_done(priv); 717 if (status) 718 goto exit; 719 720 if (i == 1 && read_write == I2C_SMBUS_READ 721 && command != I2C_SMBUS_I2C_BLOCK_DATA) { 722 len = inb_p(SMBHSTDAT0(priv)); 723 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { 724 dev_err(&priv->pci_dev->dev, 725 "Illegal SMBus block read size %d\n", 726 len); 727 /* Recover */ 728 while (inb_p(SMBHSTSTS(priv)) & 729 SMBHSTSTS_HOST_BUSY) 730 outb_p(SMBHSTSTS_BYTE_DONE, 731 SMBHSTSTS(priv)); 732 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); 733 return -EPROTO; 734 } 735 data->block[0] = len; 736 } 737 738 /* Retrieve/store value in SMBBLKDAT */ 739 if (read_write == I2C_SMBUS_READ) 740 data->block[i] = inb_p(SMBBLKDAT(priv)); 741 if (read_write == I2C_SMBUS_WRITE && i+1 <= len) 742 outb_p(data->block[i+1], SMBBLKDAT(priv)); 743 744 /* signals SMBBLKDAT ready */ 745 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 746 } 747 748 status = i801_wait_intr(priv); 749 exit: 750 return i801_check_post(priv, status); 751 } 752 753 static int i801_set_block_buffer_mode(struct i801_priv *priv) 754 { 755 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv)); 756 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0) 757 return -EIO; 758 return 0; 759 } 760 761 /* Block transaction function */ 762 static int i801_block_transaction(struct i801_priv *priv, union i2c_smbus_data *data, 763 char read_write, int command) 764 { 765 int result = 0; 766 unsigned char hostc; 767 768 if (command == I2C_SMBUS_I2C_BLOCK_DATA) { 769 if (read_write == I2C_SMBUS_WRITE) { 770 /* set I2C_EN bit in configuration register */ 771 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc); 772 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, 773 hostc | SMBHSTCFG_I2C_EN); 774 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) { 775 dev_err(&priv->pci_dev->dev, 776 "I2C block read is unsupported!\n"); 777 return -EOPNOTSUPP; 778 } 779 } 780 781 if (read_write == I2C_SMBUS_WRITE 782 || command == I2C_SMBUS_I2C_BLOCK_DATA) { 783 if (data->block[0] < 1) 784 data->block[0] = 1; 785 if (data->block[0] > I2C_SMBUS_BLOCK_MAX) 786 data->block[0] = I2C_SMBUS_BLOCK_MAX; 787 } else { 788 data->block[0] = 32; /* max for SMBus block reads */ 789 } 790 791 /* Experience has shown that the block buffer can only be used for 792 SMBus (not I2C) block transactions, even though the datasheet 793 doesn't mention this limitation. */ 794 if ((priv->features & FEATURE_BLOCK_BUFFER) 795 && command != I2C_SMBUS_I2C_BLOCK_DATA 796 && i801_set_block_buffer_mode(priv) == 0) 797 result = i801_block_transaction_by_block(priv, data, 798 read_write, 799 command); 800 else 801 result = i801_block_transaction_byte_by_byte(priv, data, 802 read_write, 803 command); 804 805 if (command == I2C_SMBUS_I2C_BLOCK_DATA 806 && read_write == I2C_SMBUS_WRITE) { 807 /* restore saved configuration register value */ 808 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc); 809 } 810 return result; 811 } 812 813 /* Return negative errno on error. */ 814 static s32 i801_access(struct i2c_adapter *adap, u16 addr, 815 unsigned short flags, char read_write, u8 command, 816 int size, union i2c_smbus_data *data) 817 { 818 int hwpec; 819 int block = 0; 820 int ret = 0, xact = 0; 821 struct i801_priv *priv = i2c_get_adapdata(adap); 822 823 mutex_lock(&priv->acpi_lock); 824 if (priv->acpi_reserved) { 825 mutex_unlock(&priv->acpi_lock); 826 return -EBUSY; 827 } 828 829 pm_runtime_get_sync(&priv->pci_dev->dev); 830 831 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) 832 && size != I2C_SMBUS_QUICK 833 && size != I2C_SMBUS_I2C_BLOCK_DATA; 834 835 switch (size) { 836 case I2C_SMBUS_QUICK: 837 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 838 SMBHSTADD(priv)); 839 xact = I801_QUICK; 840 break; 841 case I2C_SMBUS_BYTE: 842 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 843 SMBHSTADD(priv)); 844 if (read_write == I2C_SMBUS_WRITE) 845 outb_p(command, SMBHSTCMD(priv)); 846 xact = I801_BYTE; 847 break; 848 case I2C_SMBUS_BYTE_DATA: 849 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 850 SMBHSTADD(priv)); 851 outb_p(command, SMBHSTCMD(priv)); 852 if (read_write == I2C_SMBUS_WRITE) 853 outb_p(data->byte, SMBHSTDAT0(priv)); 854 xact = I801_BYTE_DATA; 855 break; 856 case I2C_SMBUS_WORD_DATA: 857 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 858 SMBHSTADD(priv)); 859 outb_p(command, SMBHSTCMD(priv)); 860 if (read_write == I2C_SMBUS_WRITE) { 861 outb_p(data->word & 0xff, SMBHSTDAT0(priv)); 862 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); 863 } 864 xact = I801_WORD_DATA; 865 break; 866 case I2C_SMBUS_BLOCK_DATA: 867 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 868 SMBHSTADD(priv)); 869 outb_p(command, SMBHSTCMD(priv)); 870 block = 1; 871 break; 872 case I2C_SMBUS_I2C_BLOCK_DATA: 873 /* 874 * NB: page 240 of ICH5 datasheet shows that the R/#W 875 * bit should be cleared here, even when reading. 876 * However if SPD Write Disable is set (Lynx Point and later), 877 * the read will fail if we don't set the R/#W bit. 878 */ 879 outb_p(((addr & 0x7f) << 1) | 880 ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ? 881 (read_write & 0x01) : 0), 882 SMBHSTADD(priv)); 883 if (read_write == I2C_SMBUS_READ) { 884 /* NB: page 240 of ICH5 datasheet also shows 885 * that DATA1 is the cmd field when reading */ 886 outb_p(command, SMBHSTDAT1(priv)); 887 } else 888 outb_p(command, SMBHSTCMD(priv)); 889 block = 1; 890 break; 891 case I2C_SMBUS_BLOCK_PROC_CALL: 892 /* 893 * Bit 0 of the slave address register always indicate a write 894 * command. 895 */ 896 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv)); 897 outb_p(command, SMBHSTCMD(priv)); 898 block = 1; 899 break; 900 default: 901 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n", 902 size); 903 ret = -EOPNOTSUPP; 904 goto out; 905 } 906 907 if (hwpec) /* enable/disable hardware PEC */ 908 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv)); 909 else 910 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC), 911 SMBAUXCTL(priv)); 912 913 if (block) 914 ret = i801_block_transaction(priv, data, read_write, size); 915 else 916 ret = i801_transaction(priv, xact); 917 918 /* Some BIOSes don't like it when PEC is enabled at reboot or resume 919 time, so we forcibly disable it after every transaction. Turn off 920 E32B for the same reason. */ 921 if (hwpec || block) 922 outb_p(inb_p(SMBAUXCTL(priv)) & 923 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 924 925 if (block) 926 goto out; 927 if (ret) 928 goto out; 929 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK)) 930 goto out; 931 932 switch (xact & 0x7f) { 933 case I801_BYTE: /* Result put in SMBHSTDAT0 */ 934 case I801_BYTE_DATA: 935 data->byte = inb_p(SMBHSTDAT0(priv)); 936 break; 937 case I801_WORD_DATA: 938 data->word = inb_p(SMBHSTDAT0(priv)) + 939 (inb_p(SMBHSTDAT1(priv)) << 8); 940 break; 941 } 942 943 out: 944 /* Unlock the SMBus device for use by BIOS/ACPI */ 945 outb_p(SMBHSTSTS_INUSE_STS, SMBHSTSTS(priv)); 946 947 pm_runtime_mark_last_busy(&priv->pci_dev->dev); 948 pm_runtime_put_autosuspend(&priv->pci_dev->dev); 949 mutex_unlock(&priv->acpi_lock); 950 return ret; 951 } 952 953 954 static u32 i801_func(struct i2c_adapter *adapter) 955 { 956 struct i801_priv *priv = i2c_get_adapdata(adapter); 957 958 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 959 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 960 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | 961 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | 962 ((priv->features & FEATURE_BLOCK_PROC) ? 963 I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) | 964 ((priv->features & FEATURE_I2C_BLOCK_READ) ? 965 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) | 966 ((priv->features & FEATURE_HOST_NOTIFY) ? 967 I2C_FUNC_SMBUS_HOST_NOTIFY : 0); 968 } 969 970 static void i801_enable_host_notify(struct i2c_adapter *adapter) 971 { 972 struct i801_priv *priv = i2c_get_adapdata(adapter); 973 974 if (!(priv->features & FEATURE_HOST_NOTIFY)) 975 return; 976 977 if (!(SMBSLVCMD_HST_NTFY_INTREN & priv->original_slvcmd)) 978 outb_p(SMBSLVCMD_HST_NTFY_INTREN | priv->original_slvcmd, 979 SMBSLVCMD(priv)); 980 981 /* clear Host Notify bit to allow a new notification */ 982 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 983 } 984 985 static void i801_disable_host_notify(struct i801_priv *priv) 986 { 987 if (!(priv->features & FEATURE_HOST_NOTIFY)) 988 return; 989 990 outb_p(priv->original_slvcmd, SMBSLVCMD(priv)); 991 } 992 993 static const struct i2c_algorithm smbus_algorithm = { 994 .smbus_xfer = i801_access, 995 .functionality = i801_func, 996 }; 997 998 static const struct pci_device_id i801_ids[] = { 999 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) }, 1000 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) }, 1001 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) }, 1002 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) }, 1003 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) }, 1004 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) }, 1005 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) }, 1006 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) }, 1007 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) }, 1008 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) }, 1009 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) }, 1010 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) }, 1011 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) }, 1012 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) }, 1013 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) }, 1014 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) }, 1015 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) }, 1016 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) }, 1017 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) }, 1018 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) }, 1019 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) }, 1020 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) }, 1021 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) }, 1022 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) }, 1023 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) }, 1024 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) }, 1025 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) }, 1026 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) }, 1027 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) }, 1028 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) }, 1029 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) }, 1030 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS) }, 1031 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) }, 1032 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) }, 1033 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) }, 1034 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) }, 1035 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) }, 1036 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) }, 1037 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMBUS) }, 1038 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) }, 1039 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EBG_SMBUS) }, 1040 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) }, 1041 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) }, 1042 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) }, 1043 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) }, 1044 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS) }, 1045 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS) }, 1046 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS) }, 1047 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICELAKE_N_SMBUS) }, 1048 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS) }, 1049 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS) }, 1050 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS) }, 1051 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS) }, 1052 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS) }, 1053 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS) }, 1054 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS) }, 1055 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS) }, 1056 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS) }, 1057 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS) }, 1058 { 0, } 1059 }; 1060 1061 MODULE_DEVICE_TABLE(pci, i801_ids); 1062 1063 #if defined CONFIG_X86 && defined CONFIG_DMI 1064 static unsigned char apanel_addr; 1065 1066 /* Scan the system ROM for the signature "FJKEYINF" */ 1067 static __init const void __iomem *bios_signature(const void __iomem *bios) 1068 { 1069 ssize_t offset; 1070 const unsigned char signature[] = "FJKEYINF"; 1071 1072 for (offset = 0; offset < 0x10000; offset += 0x10) { 1073 if (check_signature(bios + offset, signature, 1074 sizeof(signature)-1)) 1075 return bios + offset; 1076 } 1077 return NULL; 1078 } 1079 1080 static void __init input_apanel_init(void) 1081 { 1082 void __iomem *bios; 1083 const void __iomem *p; 1084 1085 bios = ioremap(0xF0000, 0x10000); /* Can't fail */ 1086 p = bios_signature(bios); 1087 if (p) { 1088 /* just use the first address */ 1089 apanel_addr = readb(p + 8 + 3) >> 1; 1090 } 1091 iounmap(bios); 1092 } 1093 1094 struct dmi_onboard_device_info { 1095 const char *name; 1096 u8 type; 1097 unsigned short i2c_addr; 1098 const char *i2c_type; 1099 }; 1100 1101 static const struct dmi_onboard_device_info dmi_devices[] = { 1102 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" }, 1103 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" }, 1104 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" }, 1105 }; 1106 1107 static void dmi_check_onboard_device(u8 type, const char *name, 1108 struct i2c_adapter *adap) 1109 { 1110 int i; 1111 struct i2c_board_info info; 1112 1113 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) { 1114 /* & ~0x80, ignore enabled/disabled bit */ 1115 if ((type & ~0x80) != dmi_devices[i].type) 1116 continue; 1117 if (strcasecmp(name, dmi_devices[i].name)) 1118 continue; 1119 1120 memset(&info, 0, sizeof(struct i2c_board_info)); 1121 info.addr = dmi_devices[i].i2c_addr; 1122 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); 1123 i2c_new_client_device(adap, &info); 1124 break; 1125 } 1126 } 1127 1128 /* We use our own function to check for onboard devices instead of 1129 dmi_find_device() as some buggy BIOS's have the devices we are interested 1130 in marked as disabled */ 1131 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap) 1132 { 1133 int i, count; 1134 1135 if (dm->type != 10) 1136 return; 1137 1138 count = (dm->length - sizeof(struct dmi_header)) / 2; 1139 for (i = 0; i < count; i++) { 1140 const u8 *d = (char *)(dm + 1) + (i * 2); 1141 const char *name = ((char *) dm) + dm->length; 1142 u8 type = d[0]; 1143 u8 s = d[1]; 1144 1145 if (!s) 1146 continue; 1147 s--; 1148 while (s > 0 && name[0]) { 1149 name += strlen(name) + 1; 1150 s--; 1151 } 1152 if (name[0] == 0) /* Bogus string reference */ 1153 continue; 1154 1155 dmi_check_onboard_device(type, name, adap); 1156 } 1157 } 1158 1159 /* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */ 1160 static const char *const acpi_smo8800_ids[] = { 1161 "SMO8800", 1162 "SMO8801", 1163 "SMO8810", 1164 "SMO8811", 1165 "SMO8820", 1166 "SMO8821", 1167 "SMO8830", 1168 "SMO8831", 1169 }; 1170 1171 static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle, 1172 u32 nesting_level, 1173 void *context, 1174 void **return_value) 1175 { 1176 struct acpi_device_info *info; 1177 acpi_status status; 1178 char *hid; 1179 int i; 1180 1181 status = acpi_get_object_info(obj_handle, &info); 1182 if (ACPI_FAILURE(status)) 1183 return AE_OK; 1184 1185 if (!(info->valid & ACPI_VALID_HID)) 1186 goto smo88xx_not_found; 1187 1188 hid = info->hardware_id.string; 1189 if (!hid) 1190 goto smo88xx_not_found; 1191 1192 i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid); 1193 if (i < 0) 1194 goto smo88xx_not_found; 1195 1196 kfree(info); 1197 1198 *return_value = NULL; 1199 return AE_CTRL_TERMINATE; 1200 1201 smo88xx_not_found: 1202 kfree(info); 1203 return AE_OK; 1204 } 1205 1206 static bool is_dell_system_with_lis3lv02d(void) 1207 { 1208 void *err = ERR_PTR(-ENOENT); 1209 1210 if (!dmi_match(DMI_SYS_VENDOR, "Dell Inc.")) 1211 return false; 1212 1213 /* 1214 * Check that ACPI device SMO88xx is present and is functioning. 1215 * Function acpi_get_devices() already filters all ACPI devices 1216 * which are not present or are not functioning. 1217 * ACPI device SMO88xx represents our ST microelectronics lis3lv02d 1218 * accelerometer but unfortunately ACPI does not provide any other 1219 * information (like I2C address). 1220 */ 1221 acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL, &err); 1222 1223 return !IS_ERR(err); 1224 } 1225 1226 /* 1227 * Accelerometer's I2C address is not specified in DMI nor ACPI, 1228 * so it is needed to define mapping table based on DMI product names. 1229 */ 1230 static const struct { 1231 const char *dmi_product_name; 1232 unsigned short i2c_addr; 1233 } dell_lis3lv02d_devices[] = { 1234 /* 1235 * Dell platform team told us that these Latitude devices have 1236 * ST microelectronics accelerometer at I2C address 0x29. 1237 */ 1238 { "Latitude E5250", 0x29 }, 1239 { "Latitude E5450", 0x29 }, 1240 { "Latitude E5550", 0x29 }, 1241 { "Latitude E6440", 0x29 }, 1242 { "Latitude E6440 ATG", 0x29 }, 1243 { "Latitude E6540", 0x29 }, 1244 /* 1245 * Additional individual entries were added after verification. 1246 */ 1247 { "Latitude 5480", 0x29 }, 1248 { "Vostro V131", 0x1d }, 1249 }; 1250 1251 static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv) 1252 { 1253 struct i2c_board_info info; 1254 const char *dmi_product_name; 1255 int i; 1256 1257 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME); 1258 for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) { 1259 if (strcmp(dmi_product_name, 1260 dell_lis3lv02d_devices[i].dmi_product_name) == 0) 1261 break; 1262 } 1263 1264 if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) { 1265 dev_warn(&priv->pci_dev->dev, 1266 "Accelerometer lis3lv02d is present on SMBus but its" 1267 " address is unknown, skipping registration\n"); 1268 return; 1269 } 1270 1271 memset(&info, 0, sizeof(struct i2c_board_info)); 1272 info.addr = dell_lis3lv02d_devices[i].i2c_addr; 1273 strlcpy(info.type, "lis3lv02d", I2C_NAME_SIZE); 1274 i2c_new_client_device(&priv->adapter, &info); 1275 } 1276 1277 /* Register optional slaves */ 1278 static void i801_probe_optional_slaves(struct i801_priv *priv) 1279 { 1280 /* Only register slaves on main SMBus channel */ 1281 if (priv->features & FEATURE_IDF) 1282 return; 1283 1284 if (apanel_addr) { 1285 struct i2c_board_info info = { 1286 .addr = apanel_addr, 1287 .type = "fujitsu_apanel", 1288 }; 1289 1290 i2c_new_client_device(&priv->adapter, &info); 1291 } 1292 1293 if (dmi_name_in_vendors("FUJITSU")) 1294 dmi_walk(dmi_check_onboard_devices, &priv->adapter); 1295 1296 if (is_dell_system_with_lis3lv02d()) 1297 register_dell_lis3lv02d_i2c_device(priv); 1298 1299 /* Instantiate SPD EEPROMs unless the SMBus is multiplexed */ 1300 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) 1301 if (!priv->mux_drvdata) 1302 #endif 1303 i2c_register_spd(&priv->adapter); 1304 } 1305 #else 1306 static void __init input_apanel_init(void) {} 1307 static void i801_probe_optional_slaves(struct i801_priv *priv) {} 1308 #endif /* CONFIG_X86 && CONFIG_DMI */ 1309 1310 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 1311 static struct i801_mux_config i801_mux_config_asus_z8_d12 = { 1312 .gpio_chip = "gpio_ich", 1313 .values = { 0x02, 0x03 }, 1314 .n_values = 2, 1315 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD }, 1316 .gpios = { 52, 53 }, 1317 .n_gpios = 2, 1318 }; 1319 1320 static struct i801_mux_config i801_mux_config_asus_z8_d18 = { 1321 .gpio_chip = "gpio_ich", 1322 .values = { 0x02, 0x03, 0x01 }, 1323 .n_values = 3, 1324 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD }, 1325 .gpios = { 52, 53 }, 1326 .n_gpios = 2, 1327 }; 1328 1329 static const struct dmi_system_id mux_dmi_table[] = { 1330 { 1331 .matches = { 1332 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1333 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"), 1334 }, 1335 .driver_data = &i801_mux_config_asus_z8_d12, 1336 }, 1337 { 1338 .matches = { 1339 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1340 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"), 1341 }, 1342 .driver_data = &i801_mux_config_asus_z8_d12, 1343 }, 1344 { 1345 .matches = { 1346 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1347 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"), 1348 }, 1349 .driver_data = &i801_mux_config_asus_z8_d12, 1350 }, 1351 { 1352 .matches = { 1353 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1354 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"), 1355 }, 1356 .driver_data = &i801_mux_config_asus_z8_d12, 1357 }, 1358 { 1359 .matches = { 1360 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1361 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"), 1362 }, 1363 .driver_data = &i801_mux_config_asus_z8_d12, 1364 }, 1365 { 1366 .matches = { 1367 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1368 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"), 1369 }, 1370 .driver_data = &i801_mux_config_asus_z8_d12, 1371 }, 1372 { 1373 .matches = { 1374 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1375 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"), 1376 }, 1377 .driver_data = &i801_mux_config_asus_z8_d18, 1378 }, 1379 { 1380 .matches = { 1381 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1382 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"), 1383 }, 1384 .driver_data = &i801_mux_config_asus_z8_d18, 1385 }, 1386 { 1387 .matches = { 1388 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1389 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"), 1390 }, 1391 .driver_data = &i801_mux_config_asus_z8_d12, 1392 }, 1393 { } 1394 }; 1395 1396 /* Setup multiplexing if needed */ 1397 static void i801_add_mux(struct i801_priv *priv) 1398 { 1399 struct device *dev = &priv->adapter.dev; 1400 const struct i801_mux_config *mux_config; 1401 struct i2c_mux_gpio_platform_data gpio_data; 1402 struct gpiod_lookup_table *lookup; 1403 int i; 1404 1405 if (!priv->mux_drvdata) 1406 return; 1407 mux_config = priv->mux_drvdata; 1408 1409 /* Prepare the platform data */ 1410 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data)); 1411 gpio_data.parent = priv->adapter.nr; 1412 gpio_data.values = mux_config->values; 1413 gpio_data.n_values = mux_config->n_values; 1414 gpio_data.classes = mux_config->classes; 1415 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE; 1416 1417 /* Register GPIO descriptor lookup table */ 1418 lookup = devm_kzalloc(dev, 1419 struct_size(lookup, table, mux_config->n_gpios + 1), 1420 GFP_KERNEL); 1421 if (!lookup) 1422 return; 1423 lookup->dev_id = "i2c-mux-gpio"; 1424 for (i = 0; i < mux_config->n_gpios; i++) 1425 lookup->table[i] = GPIO_LOOKUP(mux_config->gpio_chip, 1426 mux_config->gpios[i], "mux", 0); 1427 gpiod_add_lookup_table(lookup); 1428 priv->lookup = lookup; 1429 1430 /* 1431 * Register the mux device, we use PLATFORM_DEVID_NONE here 1432 * because since we are referring to the GPIO chip by name we are 1433 * anyways in deep trouble if there is more than one of these 1434 * devices, and there should likely only be one platform controller 1435 * hub. 1436 */ 1437 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio", 1438 PLATFORM_DEVID_NONE, &gpio_data, 1439 sizeof(struct i2c_mux_gpio_platform_data)); 1440 if (IS_ERR(priv->mux_pdev)) { 1441 gpiod_remove_lookup_table(lookup); 1442 dev_err(dev, "Failed to register i2c-mux-gpio device\n"); 1443 } 1444 } 1445 1446 static void i801_del_mux(struct i801_priv *priv) 1447 { 1448 platform_device_unregister(priv->mux_pdev); 1449 gpiod_remove_lookup_table(priv->lookup); 1450 } 1451 1452 static unsigned int i801_get_adapter_class(struct i801_priv *priv) 1453 { 1454 const struct dmi_system_id *id; 1455 const struct i801_mux_config *mux_config; 1456 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 1457 int i; 1458 1459 id = dmi_first_match(mux_dmi_table); 1460 if (id) { 1461 /* Remove branch classes from trunk */ 1462 mux_config = id->driver_data; 1463 for (i = 0; i < mux_config->n_values; i++) 1464 class &= ~mux_config->classes[i]; 1465 1466 /* Remember for later */ 1467 priv->mux_drvdata = mux_config; 1468 } 1469 1470 return class; 1471 } 1472 #else 1473 static inline void i801_add_mux(struct i801_priv *priv) { } 1474 static inline void i801_del_mux(struct i801_priv *priv) { } 1475 1476 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv) 1477 { 1478 return I2C_CLASS_HWMON | I2C_CLASS_SPD; 1479 } 1480 #endif 1481 1482 static const struct itco_wdt_platform_data spt_tco_platform_data = { 1483 .name = "Intel PCH", 1484 .version = 4, 1485 }; 1486 1487 static struct platform_device * 1488 i801_add_tco_spt(struct i801_priv *priv, struct pci_dev *pci_dev, 1489 struct resource *tco_res) 1490 { 1491 struct resource *res; 1492 unsigned int devfn; 1493 u64 base64_addr; 1494 u32 base_addr; 1495 u8 hidden; 1496 1497 /* 1498 * We must access the NO_REBOOT bit over the Primary to Sideband 1499 * bridge (P2SB). The BIOS prevents the P2SB device from being 1500 * enumerated by the PCI subsystem, so we need to unhide/hide it 1501 * to lookup the P2SB BAR. 1502 */ 1503 pci_lock_rescan_remove(); 1504 1505 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1); 1506 1507 /* Unhide the P2SB device, if it is hidden */ 1508 pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden); 1509 if (hidden) 1510 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0); 1511 1512 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr); 1513 base64_addr = base_addr & 0xfffffff0; 1514 1515 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr); 1516 base64_addr |= (u64)base_addr << 32; 1517 1518 /* Hide the P2SB device, if it was hidden before */ 1519 if (hidden) 1520 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden); 1521 pci_unlock_rescan_remove(); 1522 1523 res = &tco_res[1]; 1524 if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS) 1525 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV; 1526 else 1527 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL; 1528 1529 res->end = res->start + 3; 1530 res->flags = IORESOURCE_MEM; 1531 1532 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1, 1533 tco_res, 2, &spt_tco_platform_data, 1534 sizeof(spt_tco_platform_data)); 1535 } 1536 1537 static const struct itco_wdt_platform_data cnl_tco_platform_data = { 1538 .name = "Intel PCH", 1539 .version = 6, 1540 }; 1541 1542 static struct platform_device * 1543 i801_add_tco_cnl(struct i801_priv *priv, struct pci_dev *pci_dev, 1544 struct resource *tco_res) 1545 { 1546 return platform_device_register_resndata(&pci_dev->dev, 1547 "iTCO_wdt", -1, tco_res, 1, &cnl_tco_platform_data, 1548 sizeof(cnl_tco_platform_data)); 1549 } 1550 1551 static void i801_add_tco(struct i801_priv *priv) 1552 { 1553 struct pci_dev *pci_dev = priv->pci_dev; 1554 struct resource tco_res[2], *res; 1555 u32 tco_base, tco_ctl; 1556 1557 /* If we have ACPI based watchdog use that instead */ 1558 if (acpi_has_watchdog()) 1559 return; 1560 1561 if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL))) 1562 return; 1563 1564 pci_read_config_dword(pci_dev, TCOBASE, &tco_base); 1565 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl); 1566 if (!(tco_ctl & TCOCTL_EN)) 1567 return; 1568 1569 memset(tco_res, 0, sizeof(tco_res)); 1570 /* 1571 * Always populate the main iTCO IO resource here. The second entry 1572 * for NO_REBOOT MMIO is filled by the SPT specific function. 1573 */ 1574 res = &tco_res[0]; 1575 res->start = tco_base & ~1; 1576 res->end = res->start + 32 - 1; 1577 res->flags = IORESOURCE_IO; 1578 1579 if (priv->features & FEATURE_TCO_CNL) 1580 priv->tco_pdev = i801_add_tco_cnl(priv, pci_dev, tco_res); 1581 else 1582 priv->tco_pdev = i801_add_tco_spt(priv, pci_dev, tco_res); 1583 1584 if (IS_ERR(priv->tco_pdev)) 1585 dev_warn(&pci_dev->dev, "failed to create iTCO device\n"); 1586 } 1587 1588 #ifdef CONFIG_ACPI 1589 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv, 1590 acpi_physical_address address) 1591 { 1592 return address >= priv->smba && 1593 address <= pci_resource_end(priv->pci_dev, SMBBAR); 1594 } 1595 1596 static acpi_status 1597 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits, 1598 u64 *value, void *handler_context, void *region_context) 1599 { 1600 struct i801_priv *priv = handler_context; 1601 struct pci_dev *pdev = priv->pci_dev; 1602 acpi_status status; 1603 1604 /* 1605 * Once BIOS AML code touches the OpRegion we warn and inhibit any 1606 * further access from the driver itself. This device is now owned 1607 * by the system firmware. 1608 */ 1609 mutex_lock(&priv->acpi_lock); 1610 1611 if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) { 1612 priv->acpi_reserved = true; 1613 1614 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n"); 1615 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n"); 1616 1617 /* 1618 * BIOS is accessing the host controller so prevent it from 1619 * suspending automatically from now on. 1620 */ 1621 pm_runtime_get_sync(&pdev->dev); 1622 } 1623 1624 if ((function & ACPI_IO_MASK) == ACPI_READ) 1625 status = acpi_os_read_port(address, (u32 *)value, bits); 1626 else 1627 status = acpi_os_write_port(address, (u32)*value, bits); 1628 1629 mutex_unlock(&priv->acpi_lock); 1630 1631 return status; 1632 } 1633 1634 static int i801_acpi_probe(struct i801_priv *priv) 1635 { 1636 acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev); 1637 acpi_status status; 1638 1639 status = acpi_install_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO, 1640 i801_acpi_io_handler, NULL, priv); 1641 if (ACPI_SUCCESS(status)) 1642 return 0; 1643 1644 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]); 1645 } 1646 1647 static void i801_acpi_remove(struct i801_priv *priv) 1648 { 1649 acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev); 1650 1651 acpi_remove_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler); 1652 } 1653 #else 1654 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; } 1655 static inline void i801_acpi_remove(struct i801_priv *priv) { } 1656 #endif 1657 1658 static void i801_setup_hstcfg(struct i801_priv *priv) 1659 { 1660 unsigned char hstcfg = priv->original_hstcfg; 1661 1662 hstcfg &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ 1663 hstcfg |= SMBHSTCFG_HST_EN; 1664 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hstcfg); 1665 } 1666 1667 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id) 1668 { 1669 int err, i; 1670 struct i801_priv *priv; 1671 1672 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL); 1673 if (!priv) 1674 return -ENOMEM; 1675 1676 i2c_set_adapdata(&priv->adapter, priv); 1677 priv->adapter.owner = THIS_MODULE; 1678 priv->adapter.class = i801_get_adapter_class(priv); 1679 priv->adapter.algo = &smbus_algorithm; 1680 priv->adapter.dev.parent = &dev->dev; 1681 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev)); 1682 priv->adapter.retries = 3; 1683 mutex_init(&priv->acpi_lock); 1684 1685 priv->pci_dev = dev; 1686 switch (dev->device) { 1687 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS: 1688 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS: 1689 case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS: 1690 case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS: 1691 case PCI_DEVICE_ID_INTEL_DNV_SMBUS: 1692 case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS: 1693 case PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS: 1694 priv->features |= FEATURE_BLOCK_PROC; 1695 priv->features |= FEATURE_I2C_BLOCK_READ; 1696 priv->features |= FEATURE_IRQ; 1697 priv->features |= FEATURE_SMBUS_PEC; 1698 priv->features |= FEATURE_BLOCK_BUFFER; 1699 priv->features |= FEATURE_TCO_SPT; 1700 priv->features |= FEATURE_HOST_NOTIFY; 1701 break; 1702 1703 case PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS: 1704 case PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS: 1705 case PCI_DEVICE_ID_INTEL_CDF_SMBUS: 1706 case PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS: 1707 case PCI_DEVICE_ID_INTEL_ICELAKE_N_SMBUS: 1708 case PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS: 1709 case PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS: 1710 case PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS: 1711 case PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS: 1712 case PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS: 1713 case PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS: 1714 case PCI_DEVICE_ID_INTEL_EBG_SMBUS: 1715 case PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS: 1716 case PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS: 1717 case PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS: 1718 priv->features |= FEATURE_BLOCK_PROC; 1719 priv->features |= FEATURE_I2C_BLOCK_READ; 1720 priv->features |= FEATURE_IRQ; 1721 priv->features |= FEATURE_SMBUS_PEC; 1722 priv->features |= FEATURE_BLOCK_BUFFER; 1723 priv->features |= FEATURE_TCO_CNL; 1724 priv->features |= FEATURE_HOST_NOTIFY; 1725 break; 1726 1727 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0: 1728 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1: 1729 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2: 1730 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0: 1731 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1: 1732 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2: 1733 priv->features |= FEATURE_IDF; 1734 fallthrough; 1735 default: 1736 priv->features |= FEATURE_BLOCK_PROC; 1737 priv->features |= FEATURE_I2C_BLOCK_READ; 1738 priv->features |= FEATURE_IRQ; 1739 fallthrough; 1740 case PCI_DEVICE_ID_INTEL_82801DB_3: 1741 priv->features |= FEATURE_SMBUS_PEC; 1742 priv->features |= FEATURE_BLOCK_BUFFER; 1743 fallthrough; 1744 case PCI_DEVICE_ID_INTEL_82801CA_3: 1745 priv->features |= FEATURE_HOST_NOTIFY; 1746 fallthrough; 1747 case PCI_DEVICE_ID_INTEL_82801BA_2: 1748 case PCI_DEVICE_ID_INTEL_82801AB_3: 1749 case PCI_DEVICE_ID_INTEL_82801AA_3: 1750 break; 1751 } 1752 1753 /* Disable features on user request */ 1754 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) { 1755 if (priv->features & disable_features & (1 << i)) 1756 dev_notice(&dev->dev, "%s disabled by user\n", 1757 i801_feature_names[i]); 1758 } 1759 priv->features &= ~disable_features; 1760 1761 err = pcim_enable_device(dev); 1762 if (err) { 1763 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", 1764 err); 1765 return err; 1766 } 1767 pcim_pin_device(dev); 1768 1769 /* Determine the address of the SMBus area */ 1770 priv->smba = pci_resource_start(dev, SMBBAR); 1771 if (!priv->smba) { 1772 dev_err(&dev->dev, 1773 "SMBus base address uninitialized, upgrade BIOS\n"); 1774 return -ENODEV; 1775 } 1776 1777 if (i801_acpi_probe(priv)) 1778 return -ENODEV; 1779 1780 err = pcim_iomap_regions(dev, 1 << SMBBAR, DRV_NAME); 1781 if (err) { 1782 dev_err(&dev->dev, 1783 "Failed to request SMBus region 0x%lx-0x%Lx\n", 1784 priv->smba, 1785 (unsigned long long)pci_resource_end(dev, SMBBAR)); 1786 i801_acpi_remove(priv); 1787 return err; 1788 } 1789 1790 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &priv->original_hstcfg); 1791 i801_setup_hstcfg(priv); 1792 if (!(priv->original_hstcfg & SMBHSTCFG_HST_EN)) 1793 dev_info(&dev->dev, "Enabling SMBus device\n"); 1794 1795 if (priv->original_hstcfg & SMBHSTCFG_SMB_SMI_EN) { 1796 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); 1797 /* Disable SMBus interrupt feature if SMBus using SMI# */ 1798 priv->features &= ~FEATURE_IRQ; 1799 } 1800 if (priv->original_hstcfg & SMBHSTCFG_SPD_WD) 1801 dev_info(&dev->dev, "SPD Write Disable is set\n"); 1802 1803 /* Clear special mode bits */ 1804 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) 1805 outb_p(inb_p(SMBAUXCTL(priv)) & 1806 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 1807 1808 /* Remember original Host Notify setting */ 1809 if (priv->features & FEATURE_HOST_NOTIFY) 1810 priv->original_slvcmd = inb_p(SMBSLVCMD(priv)); 1811 1812 /* Default timeout in interrupt mode: 200 ms */ 1813 priv->adapter.timeout = HZ / 5; 1814 1815 if (dev->irq == IRQ_NOTCONNECTED) 1816 priv->features &= ~FEATURE_IRQ; 1817 1818 if (priv->features & FEATURE_IRQ) { 1819 u16 pcists; 1820 1821 /* Complain if an interrupt is already pending */ 1822 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists); 1823 if (pcists & PCI_STATUS_INTERRUPT) 1824 dev_warn(&dev->dev, "An interrupt is pending!\n"); 1825 } 1826 1827 if (priv->features & FEATURE_IRQ) { 1828 init_completion(&priv->done); 1829 1830 err = devm_request_irq(&dev->dev, dev->irq, i801_isr, 1831 IRQF_SHARED, DRV_NAME, priv); 1832 if (err) { 1833 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n", 1834 dev->irq, err); 1835 priv->features &= ~FEATURE_IRQ; 1836 } 1837 } 1838 dev_info(&dev->dev, "SMBus using %s\n", 1839 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling"); 1840 1841 i801_add_tco(priv); 1842 1843 snprintf(priv->adapter.name, sizeof(priv->adapter.name), 1844 "SMBus I801 adapter at %04lx", priv->smba); 1845 err = i2c_add_adapter(&priv->adapter); 1846 if (err) { 1847 i801_acpi_remove(priv); 1848 return err; 1849 } 1850 1851 i801_enable_host_notify(&priv->adapter); 1852 1853 i801_probe_optional_slaves(priv); 1854 /* We ignore errors - multiplexing is optional */ 1855 i801_add_mux(priv); 1856 1857 pci_set_drvdata(dev, priv); 1858 1859 dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 1860 pm_runtime_set_autosuspend_delay(&dev->dev, 1000); 1861 pm_runtime_use_autosuspend(&dev->dev); 1862 pm_runtime_put_autosuspend(&dev->dev); 1863 pm_runtime_allow(&dev->dev); 1864 1865 return 0; 1866 } 1867 1868 static void i801_remove(struct pci_dev *dev) 1869 { 1870 struct i801_priv *priv = pci_get_drvdata(dev); 1871 1872 i801_disable_host_notify(priv); 1873 i801_del_mux(priv); 1874 i2c_del_adapter(&priv->adapter); 1875 i801_acpi_remove(priv); 1876 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); 1877 1878 platform_device_unregister(priv->tco_pdev); 1879 1880 /* if acpi_reserved is set then usage_count is incremented already */ 1881 if (!priv->acpi_reserved) 1882 pm_runtime_get_noresume(&dev->dev); 1883 1884 /* 1885 * do not call pci_disable_device(dev) since it can cause hard hangs on 1886 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) 1887 */ 1888 } 1889 1890 static void i801_shutdown(struct pci_dev *dev) 1891 { 1892 struct i801_priv *priv = pci_get_drvdata(dev); 1893 1894 /* Restore config registers to avoid hard hang on some systems */ 1895 i801_disable_host_notify(priv); 1896 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); 1897 } 1898 1899 #ifdef CONFIG_PM_SLEEP 1900 static int i801_suspend(struct device *dev) 1901 { 1902 struct i801_priv *priv = dev_get_drvdata(dev); 1903 1904 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, priv->original_hstcfg); 1905 return 0; 1906 } 1907 1908 static int i801_resume(struct device *dev) 1909 { 1910 struct i801_priv *priv = dev_get_drvdata(dev); 1911 1912 i801_setup_hstcfg(priv); 1913 i801_enable_host_notify(&priv->adapter); 1914 1915 return 0; 1916 } 1917 #endif 1918 1919 static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume); 1920 1921 static struct pci_driver i801_driver = { 1922 .name = DRV_NAME, 1923 .id_table = i801_ids, 1924 .probe = i801_probe, 1925 .remove = i801_remove, 1926 .shutdown = i801_shutdown, 1927 .driver = { 1928 .pm = &i801_pm_ops, 1929 }, 1930 }; 1931 1932 static int __init i2c_i801_init(void) 1933 { 1934 if (dmi_name_in_vendors("FUJITSU")) 1935 input_apanel_init(); 1936 return pci_register_driver(&i801_driver); 1937 } 1938 1939 static void __exit i2c_i801_exit(void) 1940 { 1941 pci_unregister_driver(&i801_driver); 1942 } 1943 1944 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>"); 1945 MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>"); 1946 MODULE_DESCRIPTION("I801 SMBus driver"); 1947 MODULE_LICENSE("GPL"); 1948 1949 module_init(i2c_i801_init); 1950 module_exit(i2c_i801_exit); 1951