1 /* 2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, 3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker 4 <mdsxyz123@yahoo.com> 5 Copyright (C) 2007 - 2012 Jean Delvare <jdelvare@suse.de> 6 Copyright (C) 2010 Intel Corporation, 7 David Woodhouse <dwmw2@infradead.org> 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 2 of the License, or 12 (at your option) any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program; if not, write to the Free Software 21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 22 */ 23 24 /* 25 * Supports the following Intel I/O Controller Hubs (ICH): 26 * 27 * I/O Block I2C 28 * region SMBus Block proc. block 29 * Chip name PCI ID size PEC buffer call read 30 * --------------------------------------------------------------------------- 31 * 82801AA (ICH) 0x2413 16 no no no no 32 * 82801AB (ICH0) 0x2423 16 no no no no 33 * 82801BA (ICH2) 0x2443 16 no no no no 34 * 82801CA (ICH3) 0x2483 32 soft no no no 35 * 82801DB (ICH4) 0x24c3 32 hard yes no no 36 * 82801E (ICH5) 0x24d3 32 hard yes yes yes 37 * 6300ESB 0x25a4 32 hard yes yes yes 38 * 82801F (ICH6) 0x266a 32 hard yes yes yes 39 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes 40 * 82801G (ICH7) 0x27da 32 hard yes yes yes 41 * 82801H (ICH8) 0x283e 32 hard yes yes yes 42 * 82801I (ICH9) 0x2930 32 hard yes yes yes 43 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes 44 * ICH10 0x3a30 32 hard yes yes yes 45 * ICH10 0x3a60 32 hard yes yes yes 46 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes 47 * 6 Series (PCH) 0x1c22 32 hard yes yes yes 48 * Patsburg (PCH) 0x1d22 32 hard yes yes yes 49 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes 50 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes 51 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes 52 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes 53 * Panther Point (PCH) 0x1e22 32 hard yes yes yes 54 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes 55 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes 56 * Avoton (SOC) 0x1f3c 32 hard yes yes yes 57 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes 58 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes 59 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes 60 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes 61 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes 62 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes 63 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes 64 * BayTrail (SOC) 0x0f12 32 hard yes yes yes 65 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes 66 * 67 * Features supported by this driver: 68 * Software PEC no 69 * Hardware PEC yes 70 * Block buffer yes 71 * Block process call transaction no 72 * I2C block read transaction yes (doesn't use the block buffer) 73 * Slave mode no 74 * Interrupt processing yes 75 * 76 * See the file Documentation/i2c/busses/i2c-i801 for details. 77 */ 78 79 #include <linux/interrupt.h> 80 #include <linux/module.h> 81 #include <linux/pci.h> 82 #include <linux/kernel.h> 83 #include <linux/stddef.h> 84 #include <linux/delay.h> 85 #include <linux/ioport.h> 86 #include <linux/init.h> 87 #include <linux/i2c.h> 88 #include <linux/acpi.h> 89 #include <linux/io.h> 90 #include <linux/dmi.h> 91 #include <linux/slab.h> 92 #include <linux/wait.h> 93 #include <linux/err.h> 94 95 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \ 96 defined CONFIG_DMI 97 #include <linux/gpio.h> 98 #include <linux/i2c-mux-gpio.h> 99 #include <linux/platform_device.h> 100 #endif 101 102 /* I801 SMBus address offsets */ 103 #define SMBHSTSTS(p) (0 + (p)->smba) 104 #define SMBHSTCNT(p) (2 + (p)->smba) 105 #define SMBHSTCMD(p) (3 + (p)->smba) 106 #define SMBHSTADD(p) (4 + (p)->smba) 107 #define SMBHSTDAT0(p) (5 + (p)->smba) 108 #define SMBHSTDAT1(p) (6 + (p)->smba) 109 #define SMBBLKDAT(p) (7 + (p)->smba) 110 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */ 111 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */ 112 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */ 113 114 /* PCI Address Constants */ 115 #define SMBBAR 4 116 #define SMBPCISTS 0x006 117 #define SMBHSTCFG 0x040 118 119 /* Host status bits for SMBPCISTS */ 120 #define SMBPCISTS_INTS 0x08 121 122 /* Host configuration bits for SMBHSTCFG */ 123 #define SMBHSTCFG_HST_EN 1 124 #define SMBHSTCFG_SMB_SMI_EN 2 125 #define SMBHSTCFG_I2C_EN 4 126 127 /* Auxiliary control register bits, ICH4+ only */ 128 #define SMBAUXCTL_CRC 1 129 #define SMBAUXCTL_E32B 2 130 131 /* Other settings */ 132 #define MAX_RETRIES 400 133 134 /* I801 command constants */ 135 #define I801_QUICK 0x00 136 #define I801_BYTE 0x04 137 #define I801_BYTE_DATA 0x08 138 #define I801_WORD_DATA 0x0C 139 #define I801_PROC_CALL 0x10 /* unimplemented */ 140 #define I801_BLOCK_DATA 0x14 141 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ 142 143 /* I801 Host Control register bits */ 144 #define SMBHSTCNT_INTREN 0x01 145 #define SMBHSTCNT_KILL 0x02 146 #define SMBHSTCNT_LAST_BYTE 0x20 147 #define SMBHSTCNT_START 0x40 148 #define SMBHSTCNT_PEC_EN 0x80 /* ICH3 and later */ 149 150 /* I801 Hosts Status register bits */ 151 #define SMBHSTSTS_BYTE_DONE 0x80 152 #define SMBHSTSTS_INUSE_STS 0x40 153 #define SMBHSTSTS_SMBALERT_STS 0x20 154 #define SMBHSTSTS_FAILED 0x10 155 #define SMBHSTSTS_BUS_ERR 0x08 156 #define SMBHSTSTS_DEV_ERR 0x04 157 #define SMBHSTSTS_INTR 0x02 158 #define SMBHSTSTS_HOST_BUSY 0x01 159 160 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \ 161 SMBHSTSTS_DEV_ERR) 162 163 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \ 164 STATUS_ERROR_FLAGS) 165 166 /* Older devices have their ID defined in <linux/pci_ids.h> */ 167 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12 168 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292 169 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 170 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 171 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */ 172 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70 173 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71 174 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72 175 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 176 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c 177 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 178 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0 179 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 180 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 181 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2 182 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22 183 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d 184 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e 185 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f 186 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22 187 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2 188 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123 189 190 struct i801_mux_config { 191 char *gpio_chip; 192 unsigned values[3]; 193 int n_values; 194 unsigned classes[3]; 195 unsigned gpios[2]; /* Relative to gpio_chip->base */ 196 int n_gpios; 197 }; 198 199 struct i801_priv { 200 struct i2c_adapter adapter; 201 unsigned long smba; 202 unsigned char original_hstcfg; 203 struct pci_dev *pci_dev; 204 unsigned int features; 205 206 /* isr processing */ 207 wait_queue_head_t waitq; 208 u8 status; 209 210 /* Command state used by isr for byte-by-byte block transactions */ 211 u8 cmd; 212 bool is_read; 213 int count; 214 int len; 215 u8 *data; 216 217 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \ 218 defined CONFIG_DMI 219 const struct i801_mux_config *mux_drvdata; 220 struct platform_device *mux_pdev; 221 #endif 222 }; 223 224 static struct pci_driver i801_driver; 225 226 #define FEATURE_SMBUS_PEC (1 << 0) 227 #define FEATURE_BLOCK_BUFFER (1 << 1) 228 #define FEATURE_BLOCK_PROC (1 << 2) 229 #define FEATURE_I2C_BLOCK_READ (1 << 3) 230 #define FEATURE_IRQ (1 << 4) 231 /* Not really a feature, but it's convenient to handle it as such */ 232 #define FEATURE_IDF (1 << 15) 233 234 static const char *i801_feature_names[] = { 235 "SMBus PEC", 236 "Block buffer", 237 "Block process call", 238 "I2C block read", 239 "Interrupt", 240 }; 241 242 static unsigned int disable_features; 243 module_param(disable_features, uint, S_IRUGO | S_IWUSR); 244 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n" 245 "\t\t 0x01 disable SMBus PEC\n" 246 "\t\t 0x02 disable the block buffer\n" 247 "\t\t 0x08 disable the I2C block read functionality\n" 248 "\t\t 0x10 don't use interrupts "); 249 250 /* Make sure the SMBus host is ready to start transmitting. 251 Return 0 if it is, -EBUSY if it is not. */ 252 static int i801_check_pre(struct i801_priv *priv) 253 { 254 int status; 255 256 status = inb_p(SMBHSTSTS(priv)); 257 if (status & SMBHSTSTS_HOST_BUSY) { 258 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n"); 259 return -EBUSY; 260 } 261 262 status &= STATUS_FLAGS; 263 if (status) { 264 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n", 265 status); 266 outb_p(status, SMBHSTSTS(priv)); 267 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS; 268 if (status) { 269 dev_err(&priv->pci_dev->dev, 270 "Failed clearing status flags (%02x)\n", 271 status); 272 return -EBUSY; 273 } 274 } 275 276 return 0; 277 } 278 279 /* 280 * Convert the status register to an error code, and clear it. 281 * Note that status only contains the bits we want to clear, not the 282 * actual register value. 283 */ 284 static int i801_check_post(struct i801_priv *priv, int status) 285 { 286 int result = 0; 287 288 /* 289 * If the SMBus is still busy, we give up 290 * Note: This timeout condition only happens when using polling 291 * transactions. For interrupt operation, NAK/timeout is indicated by 292 * DEV_ERR. 293 */ 294 if (unlikely(status < 0)) { 295 dev_err(&priv->pci_dev->dev, "Transaction timeout\n"); 296 /* try to stop the current command */ 297 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n"); 298 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL, 299 SMBHSTCNT(priv)); 300 usleep_range(1000, 2000); 301 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL), 302 SMBHSTCNT(priv)); 303 304 /* Check if it worked */ 305 status = inb_p(SMBHSTSTS(priv)); 306 if ((status & SMBHSTSTS_HOST_BUSY) || 307 !(status & SMBHSTSTS_FAILED)) 308 dev_err(&priv->pci_dev->dev, 309 "Failed terminating the transaction\n"); 310 outb_p(STATUS_FLAGS, SMBHSTSTS(priv)); 311 return -ETIMEDOUT; 312 } 313 314 if (status & SMBHSTSTS_FAILED) { 315 result = -EIO; 316 dev_err(&priv->pci_dev->dev, "Transaction failed\n"); 317 } 318 if (status & SMBHSTSTS_DEV_ERR) { 319 result = -ENXIO; 320 dev_dbg(&priv->pci_dev->dev, "No response\n"); 321 } 322 if (status & SMBHSTSTS_BUS_ERR) { 323 result = -EAGAIN; 324 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n"); 325 } 326 327 /* Clear status flags except BYTE_DONE, to be cleared by caller */ 328 outb_p(status, SMBHSTSTS(priv)); 329 330 return result; 331 } 332 333 /* Wait for BUSY being cleared and either INTR or an error flag being set */ 334 static int i801_wait_intr(struct i801_priv *priv) 335 { 336 int timeout = 0; 337 int status; 338 339 /* We will always wait for a fraction of a second! */ 340 do { 341 usleep_range(250, 500); 342 status = inb_p(SMBHSTSTS(priv)); 343 } while (((status & SMBHSTSTS_HOST_BUSY) || 344 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) && 345 (timeout++ < MAX_RETRIES)); 346 347 if (timeout > MAX_RETRIES) { 348 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n"); 349 return -ETIMEDOUT; 350 } 351 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR); 352 } 353 354 /* Wait for either BYTE_DONE or an error flag being set */ 355 static int i801_wait_byte_done(struct i801_priv *priv) 356 { 357 int timeout = 0; 358 int status; 359 360 /* We will always wait for a fraction of a second! */ 361 do { 362 usleep_range(250, 500); 363 status = inb_p(SMBHSTSTS(priv)); 364 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) && 365 (timeout++ < MAX_RETRIES)); 366 367 if (timeout > MAX_RETRIES) { 368 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n"); 369 return -ETIMEDOUT; 370 } 371 return status & STATUS_ERROR_FLAGS; 372 } 373 374 static int i801_transaction(struct i801_priv *priv, int xact) 375 { 376 int status; 377 int result; 378 379 result = i801_check_pre(priv); 380 if (result < 0) 381 return result; 382 383 if (priv->features & FEATURE_IRQ) { 384 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START, 385 SMBHSTCNT(priv)); 386 wait_event(priv->waitq, (status = priv->status)); 387 priv->status = 0; 388 return i801_check_post(priv, status); 389 } 390 391 /* the current contents of SMBHSTCNT can be overwritten, since PEC, 392 * SMBSCMD are passed in xact */ 393 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv)); 394 395 status = i801_wait_intr(priv); 396 return i801_check_post(priv, status); 397 } 398 399 static int i801_block_transaction_by_block(struct i801_priv *priv, 400 union i2c_smbus_data *data, 401 char read_write, int hwpec) 402 { 403 int i, len; 404 int status; 405 406 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ 407 408 /* Use 32-byte buffer to process this transaction */ 409 if (read_write == I2C_SMBUS_WRITE) { 410 len = data->block[0]; 411 outb_p(len, SMBHSTDAT0(priv)); 412 for (i = 0; i < len; i++) 413 outb_p(data->block[i+1], SMBBLKDAT(priv)); 414 } 415 416 status = i801_transaction(priv, I801_BLOCK_DATA | 417 (hwpec ? SMBHSTCNT_PEC_EN : 0)); 418 if (status) 419 return status; 420 421 if (read_write == I2C_SMBUS_READ) { 422 len = inb_p(SMBHSTDAT0(priv)); 423 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) 424 return -EPROTO; 425 426 data->block[0] = len; 427 for (i = 0; i < len; i++) 428 data->block[i + 1] = inb_p(SMBBLKDAT(priv)); 429 } 430 return 0; 431 } 432 433 static void i801_isr_byte_done(struct i801_priv *priv) 434 { 435 if (priv->is_read) { 436 /* For SMBus block reads, length is received with first byte */ 437 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) && 438 (priv->count == 0)) { 439 priv->len = inb_p(SMBHSTDAT0(priv)); 440 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) { 441 dev_err(&priv->pci_dev->dev, 442 "Illegal SMBus block read size %d\n", 443 priv->len); 444 /* FIXME: Recover */ 445 priv->len = I2C_SMBUS_BLOCK_MAX; 446 } else { 447 dev_dbg(&priv->pci_dev->dev, 448 "SMBus block read size is %d\n", 449 priv->len); 450 } 451 priv->data[-1] = priv->len; 452 } 453 454 /* Read next byte */ 455 if (priv->count < priv->len) 456 priv->data[priv->count++] = inb(SMBBLKDAT(priv)); 457 else 458 dev_dbg(&priv->pci_dev->dev, 459 "Discarding extra byte on block read\n"); 460 461 /* Set LAST_BYTE for last byte of read transaction */ 462 if (priv->count == priv->len - 1) 463 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE, 464 SMBHSTCNT(priv)); 465 } else if (priv->count < priv->len - 1) { 466 /* Write next byte, except for IRQ after last byte */ 467 outb_p(priv->data[++priv->count], SMBBLKDAT(priv)); 468 } 469 470 /* Clear BYTE_DONE to continue with next byte */ 471 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 472 } 473 474 /* 475 * There are two kinds of interrupts: 476 * 477 * 1) i801 signals transaction completion with one of these interrupts: 478 * INTR - Success 479 * DEV_ERR - Invalid command, NAK or communication timeout 480 * BUS_ERR - SMI# transaction collision 481 * FAILED - transaction was canceled due to a KILL request 482 * When any of these occur, update ->status and wake up the waitq. 483 * ->status must be cleared before kicking off the next transaction. 484 * 485 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt 486 * occurs for each byte of a byte-by-byte to prepare the next byte. 487 */ 488 static irqreturn_t i801_isr(int irq, void *dev_id) 489 { 490 struct i801_priv *priv = dev_id; 491 u16 pcists; 492 u8 status; 493 494 /* Confirm this is our interrupt */ 495 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); 496 if (!(pcists & SMBPCISTS_INTS)) 497 return IRQ_NONE; 498 499 status = inb_p(SMBHSTSTS(priv)); 500 if (status != 0x42) 501 dev_dbg(&priv->pci_dev->dev, "irq: status = %02x\n", status); 502 503 if (status & SMBHSTSTS_BYTE_DONE) 504 i801_isr_byte_done(priv); 505 506 /* 507 * Clear irq sources and report transaction result. 508 * ->status must be cleared before the next transaction is started. 509 */ 510 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS; 511 if (status) { 512 outb_p(status, SMBHSTSTS(priv)); 513 priv->status |= status; 514 wake_up(&priv->waitq); 515 } 516 517 return IRQ_HANDLED; 518 } 519 520 /* 521 * For "byte-by-byte" block transactions: 522 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1 523 * I2C read uses cmd=I801_I2C_BLOCK_DATA 524 */ 525 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, 526 union i2c_smbus_data *data, 527 char read_write, int command, 528 int hwpec) 529 { 530 int i, len; 531 int smbcmd; 532 int status; 533 int result; 534 535 result = i801_check_pre(priv); 536 if (result < 0) 537 return result; 538 539 len = data->block[0]; 540 541 if (read_write == I2C_SMBUS_WRITE) { 542 outb_p(len, SMBHSTDAT0(priv)); 543 outb_p(data->block[1], SMBBLKDAT(priv)); 544 } 545 546 if (command == I2C_SMBUS_I2C_BLOCK_DATA && 547 read_write == I2C_SMBUS_READ) 548 smbcmd = I801_I2C_BLOCK_DATA; 549 else 550 smbcmd = I801_BLOCK_DATA; 551 552 if (priv->features & FEATURE_IRQ) { 553 priv->is_read = (read_write == I2C_SMBUS_READ); 554 if (len == 1 && priv->is_read) 555 smbcmd |= SMBHSTCNT_LAST_BYTE; 556 priv->cmd = smbcmd | SMBHSTCNT_INTREN; 557 priv->len = len; 558 priv->count = 0; 559 priv->data = &data->block[1]; 560 561 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv)); 562 wait_event(priv->waitq, (status = priv->status)); 563 priv->status = 0; 564 return i801_check_post(priv, status); 565 } 566 567 for (i = 1; i <= len; i++) { 568 if (i == len && read_write == I2C_SMBUS_READ) 569 smbcmd |= SMBHSTCNT_LAST_BYTE; 570 outb_p(smbcmd, SMBHSTCNT(priv)); 571 572 if (i == 1) 573 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START, 574 SMBHSTCNT(priv)); 575 576 status = i801_wait_byte_done(priv); 577 if (status) 578 goto exit; 579 580 if (i == 1 && read_write == I2C_SMBUS_READ 581 && command != I2C_SMBUS_I2C_BLOCK_DATA) { 582 len = inb_p(SMBHSTDAT0(priv)); 583 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { 584 dev_err(&priv->pci_dev->dev, 585 "Illegal SMBus block read size %d\n", 586 len); 587 /* Recover */ 588 while (inb_p(SMBHSTSTS(priv)) & 589 SMBHSTSTS_HOST_BUSY) 590 outb_p(SMBHSTSTS_BYTE_DONE, 591 SMBHSTSTS(priv)); 592 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); 593 return -EPROTO; 594 } 595 data->block[0] = len; 596 } 597 598 /* Retrieve/store value in SMBBLKDAT */ 599 if (read_write == I2C_SMBUS_READ) 600 data->block[i] = inb_p(SMBBLKDAT(priv)); 601 if (read_write == I2C_SMBUS_WRITE && i+1 <= len) 602 outb_p(data->block[i+1], SMBBLKDAT(priv)); 603 604 /* signals SMBBLKDAT ready */ 605 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 606 } 607 608 status = i801_wait_intr(priv); 609 exit: 610 return i801_check_post(priv, status); 611 } 612 613 static int i801_set_block_buffer_mode(struct i801_priv *priv) 614 { 615 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv)); 616 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0) 617 return -EIO; 618 return 0; 619 } 620 621 /* Block transaction function */ 622 static int i801_block_transaction(struct i801_priv *priv, 623 union i2c_smbus_data *data, char read_write, 624 int command, int hwpec) 625 { 626 int result = 0; 627 unsigned char hostc; 628 629 if (command == I2C_SMBUS_I2C_BLOCK_DATA) { 630 if (read_write == I2C_SMBUS_WRITE) { 631 /* set I2C_EN bit in configuration register */ 632 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc); 633 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, 634 hostc | SMBHSTCFG_I2C_EN); 635 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) { 636 dev_err(&priv->pci_dev->dev, 637 "I2C block read is unsupported!\n"); 638 return -EOPNOTSUPP; 639 } 640 } 641 642 if (read_write == I2C_SMBUS_WRITE 643 || command == I2C_SMBUS_I2C_BLOCK_DATA) { 644 if (data->block[0] < 1) 645 data->block[0] = 1; 646 if (data->block[0] > I2C_SMBUS_BLOCK_MAX) 647 data->block[0] = I2C_SMBUS_BLOCK_MAX; 648 } else { 649 data->block[0] = 32; /* max for SMBus block reads */ 650 } 651 652 /* Experience has shown that the block buffer can only be used for 653 SMBus (not I2C) block transactions, even though the datasheet 654 doesn't mention this limitation. */ 655 if ((priv->features & FEATURE_BLOCK_BUFFER) 656 && command != I2C_SMBUS_I2C_BLOCK_DATA 657 && i801_set_block_buffer_mode(priv) == 0) 658 result = i801_block_transaction_by_block(priv, data, 659 read_write, hwpec); 660 else 661 result = i801_block_transaction_byte_by_byte(priv, data, 662 read_write, 663 command, hwpec); 664 665 if (command == I2C_SMBUS_I2C_BLOCK_DATA 666 && read_write == I2C_SMBUS_WRITE) { 667 /* restore saved configuration register value */ 668 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc); 669 } 670 return result; 671 } 672 673 /* Return negative errno on error. */ 674 static s32 i801_access(struct i2c_adapter *adap, u16 addr, 675 unsigned short flags, char read_write, u8 command, 676 int size, union i2c_smbus_data *data) 677 { 678 int hwpec; 679 int block = 0; 680 int ret, xact = 0; 681 struct i801_priv *priv = i2c_get_adapdata(adap); 682 683 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) 684 && size != I2C_SMBUS_QUICK 685 && size != I2C_SMBUS_I2C_BLOCK_DATA; 686 687 switch (size) { 688 case I2C_SMBUS_QUICK: 689 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 690 SMBHSTADD(priv)); 691 xact = I801_QUICK; 692 break; 693 case I2C_SMBUS_BYTE: 694 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 695 SMBHSTADD(priv)); 696 if (read_write == I2C_SMBUS_WRITE) 697 outb_p(command, SMBHSTCMD(priv)); 698 xact = I801_BYTE; 699 break; 700 case I2C_SMBUS_BYTE_DATA: 701 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 702 SMBHSTADD(priv)); 703 outb_p(command, SMBHSTCMD(priv)); 704 if (read_write == I2C_SMBUS_WRITE) 705 outb_p(data->byte, SMBHSTDAT0(priv)); 706 xact = I801_BYTE_DATA; 707 break; 708 case I2C_SMBUS_WORD_DATA: 709 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 710 SMBHSTADD(priv)); 711 outb_p(command, SMBHSTCMD(priv)); 712 if (read_write == I2C_SMBUS_WRITE) { 713 outb_p(data->word & 0xff, SMBHSTDAT0(priv)); 714 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); 715 } 716 xact = I801_WORD_DATA; 717 break; 718 case I2C_SMBUS_BLOCK_DATA: 719 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 720 SMBHSTADD(priv)); 721 outb_p(command, SMBHSTCMD(priv)); 722 block = 1; 723 break; 724 case I2C_SMBUS_I2C_BLOCK_DATA: 725 /* NB: page 240 of ICH5 datasheet shows that the R/#W 726 * bit should be cleared here, even when reading */ 727 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv)); 728 if (read_write == I2C_SMBUS_READ) { 729 /* NB: page 240 of ICH5 datasheet also shows 730 * that DATA1 is the cmd field when reading */ 731 outb_p(command, SMBHSTDAT1(priv)); 732 } else 733 outb_p(command, SMBHSTCMD(priv)); 734 block = 1; 735 break; 736 default: 737 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n", 738 size); 739 return -EOPNOTSUPP; 740 } 741 742 if (hwpec) /* enable/disable hardware PEC */ 743 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv)); 744 else 745 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC), 746 SMBAUXCTL(priv)); 747 748 if (block) 749 ret = i801_block_transaction(priv, data, read_write, size, 750 hwpec); 751 else 752 ret = i801_transaction(priv, xact); 753 754 /* Some BIOSes don't like it when PEC is enabled at reboot or resume 755 time, so we forcibly disable it after every transaction. Turn off 756 E32B for the same reason. */ 757 if (hwpec || block) 758 outb_p(inb_p(SMBAUXCTL(priv)) & 759 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 760 761 if (block) 762 return ret; 763 if (ret) 764 return ret; 765 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK)) 766 return 0; 767 768 switch (xact & 0x7f) { 769 case I801_BYTE: /* Result put in SMBHSTDAT0 */ 770 case I801_BYTE_DATA: 771 data->byte = inb_p(SMBHSTDAT0(priv)); 772 break; 773 case I801_WORD_DATA: 774 data->word = inb_p(SMBHSTDAT0(priv)) + 775 (inb_p(SMBHSTDAT1(priv)) << 8); 776 break; 777 } 778 return 0; 779 } 780 781 782 static u32 i801_func(struct i2c_adapter *adapter) 783 { 784 struct i801_priv *priv = i2c_get_adapdata(adapter); 785 786 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 787 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 788 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | 789 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | 790 ((priv->features & FEATURE_I2C_BLOCK_READ) ? 791 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0); 792 } 793 794 static const struct i2c_algorithm smbus_algorithm = { 795 .smbus_xfer = i801_access, 796 .functionality = i801_func, 797 }; 798 799 static const struct pci_device_id i801_ids[] = { 800 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) }, 801 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) }, 802 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) }, 803 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) }, 804 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) }, 805 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) }, 806 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) }, 807 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) }, 808 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) }, 809 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) }, 810 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) }, 811 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) }, 812 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) }, 813 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) }, 814 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) }, 815 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) }, 816 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) }, 817 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) }, 818 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) }, 819 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) }, 820 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) }, 821 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) }, 822 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) }, 823 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) }, 824 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) }, 825 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) }, 826 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) }, 827 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) }, 828 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) }, 829 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) }, 830 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) }, 831 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) }, 832 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) }, 833 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) }, 834 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) }, 835 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) }, 836 { 0, } 837 }; 838 839 MODULE_DEVICE_TABLE(pci, i801_ids); 840 841 #if defined CONFIG_X86 && defined CONFIG_DMI 842 static unsigned char apanel_addr; 843 844 /* Scan the system ROM for the signature "FJKEYINF" */ 845 static __init const void __iomem *bios_signature(const void __iomem *bios) 846 { 847 ssize_t offset; 848 const unsigned char signature[] = "FJKEYINF"; 849 850 for (offset = 0; offset < 0x10000; offset += 0x10) { 851 if (check_signature(bios + offset, signature, 852 sizeof(signature)-1)) 853 return bios + offset; 854 } 855 return NULL; 856 } 857 858 static void __init input_apanel_init(void) 859 { 860 void __iomem *bios; 861 const void __iomem *p; 862 863 bios = ioremap(0xF0000, 0x10000); /* Can't fail */ 864 p = bios_signature(bios); 865 if (p) { 866 /* just use the first address */ 867 apanel_addr = readb(p + 8 + 3) >> 1; 868 } 869 iounmap(bios); 870 } 871 872 struct dmi_onboard_device_info { 873 const char *name; 874 u8 type; 875 unsigned short i2c_addr; 876 const char *i2c_type; 877 }; 878 879 static const struct dmi_onboard_device_info dmi_devices[] = { 880 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" }, 881 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" }, 882 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" }, 883 }; 884 885 static void dmi_check_onboard_device(u8 type, const char *name, 886 struct i2c_adapter *adap) 887 { 888 int i; 889 struct i2c_board_info info; 890 891 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) { 892 /* & ~0x80, ignore enabled/disabled bit */ 893 if ((type & ~0x80) != dmi_devices[i].type) 894 continue; 895 if (strcasecmp(name, dmi_devices[i].name)) 896 continue; 897 898 memset(&info, 0, sizeof(struct i2c_board_info)); 899 info.addr = dmi_devices[i].i2c_addr; 900 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); 901 i2c_new_device(adap, &info); 902 break; 903 } 904 } 905 906 /* We use our own function to check for onboard devices instead of 907 dmi_find_device() as some buggy BIOS's have the devices we are interested 908 in marked as disabled */ 909 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap) 910 { 911 int i, count; 912 913 if (dm->type != 10) 914 return; 915 916 count = (dm->length - sizeof(struct dmi_header)) / 2; 917 for (i = 0; i < count; i++) { 918 const u8 *d = (char *)(dm + 1) + (i * 2); 919 const char *name = ((char *) dm) + dm->length; 920 u8 type = d[0]; 921 u8 s = d[1]; 922 923 if (!s) 924 continue; 925 s--; 926 while (s > 0 && name[0]) { 927 name += strlen(name) + 1; 928 s--; 929 } 930 if (name[0] == 0) /* Bogus string reference */ 931 continue; 932 933 dmi_check_onboard_device(type, name, adap); 934 } 935 } 936 937 /* Register optional slaves */ 938 static void i801_probe_optional_slaves(struct i801_priv *priv) 939 { 940 /* Only register slaves on main SMBus channel */ 941 if (priv->features & FEATURE_IDF) 942 return; 943 944 if (apanel_addr) { 945 struct i2c_board_info info; 946 947 memset(&info, 0, sizeof(struct i2c_board_info)); 948 info.addr = apanel_addr; 949 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE); 950 i2c_new_device(&priv->adapter, &info); 951 } 952 953 if (dmi_name_in_vendors("FUJITSU")) 954 dmi_walk(dmi_check_onboard_devices, &priv->adapter); 955 } 956 #else 957 static void __init input_apanel_init(void) {} 958 static void i801_probe_optional_slaves(struct i801_priv *priv) {} 959 #endif /* CONFIG_X86 && CONFIG_DMI */ 960 961 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \ 962 defined CONFIG_DMI 963 static struct i801_mux_config i801_mux_config_asus_z8_d12 = { 964 .gpio_chip = "gpio_ich", 965 .values = { 0x02, 0x03 }, 966 .n_values = 2, 967 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD }, 968 .gpios = { 52, 53 }, 969 .n_gpios = 2, 970 }; 971 972 static struct i801_mux_config i801_mux_config_asus_z8_d18 = { 973 .gpio_chip = "gpio_ich", 974 .values = { 0x02, 0x03, 0x01 }, 975 .n_values = 3, 976 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD }, 977 .gpios = { 52, 53 }, 978 .n_gpios = 2, 979 }; 980 981 static const struct dmi_system_id mux_dmi_table[] = { 982 { 983 .matches = { 984 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 985 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"), 986 }, 987 .driver_data = &i801_mux_config_asus_z8_d12, 988 }, 989 { 990 .matches = { 991 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 992 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"), 993 }, 994 .driver_data = &i801_mux_config_asus_z8_d12, 995 }, 996 { 997 .matches = { 998 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 999 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"), 1000 }, 1001 .driver_data = &i801_mux_config_asus_z8_d12, 1002 }, 1003 { 1004 .matches = { 1005 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1006 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"), 1007 }, 1008 .driver_data = &i801_mux_config_asus_z8_d12, 1009 }, 1010 { 1011 .matches = { 1012 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1013 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"), 1014 }, 1015 .driver_data = &i801_mux_config_asus_z8_d12, 1016 }, 1017 { 1018 .matches = { 1019 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1020 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"), 1021 }, 1022 .driver_data = &i801_mux_config_asus_z8_d12, 1023 }, 1024 { 1025 .matches = { 1026 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1027 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"), 1028 }, 1029 .driver_data = &i801_mux_config_asus_z8_d18, 1030 }, 1031 { 1032 .matches = { 1033 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1034 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"), 1035 }, 1036 .driver_data = &i801_mux_config_asus_z8_d18, 1037 }, 1038 { 1039 .matches = { 1040 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1041 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"), 1042 }, 1043 .driver_data = &i801_mux_config_asus_z8_d12, 1044 }, 1045 { } 1046 }; 1047 1048 /* Setup multiplexing if needed */ 1049 static int i801_add_mux(struct i801_priv *priv) 1050 { 1051 struct device *dev = &priv->adapter.dev; 1052 const struct i801_mux_config *mux_config; 1053 struct i2c_mux_gpio_platform_data gpio_data; 1054 int err; 1055 1056 if (!priv->mux_drvdata) 1057 return 0; 1058 mux_config = priv->mux_drvdata; 1059 1060 /* Prepare the platform data */ 1061 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data)); 1062 gpio_data.parent = priv->adapter.nr; 1063 gpio_data.values = mux_config->values; 1064 gpio_data.n_values = mux_config->n_values; 1065 gpio_data.classes = mux_config->classes; 1066 gpio_data.gpio_chip = mux_config->gpio_chip; 1067 gpio_data.gpios = mux_config->gpios; 1068 gpio_data.n_gpios = mux_config->n_gpios; 1069 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE; 1070 1071 /* Register the mux device */ 1072 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio", 1073 PLATFORM_DEVID_AUTO, &gpio_data, 1074 sizeof(struct i2c_mux_gpio_platform_data)); 1075 if (IS_ERR(priv->mux_pdev)) { 1076 err = PTR_ERR(priv->mux_pdev); 1077 priv->mux_pdev = NULL; 1078 dev_err(dev, "Failed to register i2c-mux-gpio device\n"); 1079 return err; 1080 } 1081 1082 return 0; 1083 } 1084 1085 static void i801_del_mux(struct i801_priv *priv) 1086 { 1087 if (priv->mux_pdev) 1088 platform_device_unregister(priv->mux_pdev); 1089 } 1090 1091 static unsigned int i801_get_adapter_class(struct i801_priv *priv) 1092 { 1093 const struct dmi_system_id *id; 1094 const struct i801_mux_config *mux_config; 1095 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 1096 int i; 1097 1098 id = dmi_first_match(mux_dmi_table); 1099 if (id) { 1100 /* Remove branch classes from trunk */ 1101 mux_config = id->driver_data; 1102 for (i = 0; i < mux_config->n_values; i++) 1103 class &= ~mux_config->classes[i]; 1104 1105 /* Remember for later */ 1106 priv->mux_drvdata = mux_config; 1107 } 1108 1109 return class; 1110 } 1111 #else 1112 static inline int i801_add_mux(struct i801_priv *priv) { return 0; } 1113 static inline void i801_del_mux(struct i801_priv *priv) { } 1114 1115 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv) 1116 { 1117 return I2C_CLASS_HWMON | I2C_CLASS_SPD; 1118 } 1119 #endif 1120 1121 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id) 1122 { 1123 unsigned char temp; 1124 int err, i; 1125 struct i801_priv *priv; 1126 1127 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 1128 if (!priv) 1129 return -ENOMEM; 1130 1131 i2c_set_adapdata(&priv->adapter, priv); 1132 priv->adapter.owner = THIS_MODULE; 1133 priv->adapter.class = i801_get_adapter_class(priv); 1134 priv->adapter.algo = &smbus_algorithm; 1135 1136 priv->pci_dev = dev; 1137 switch (dev->device) { 1138 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0: 1139 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1: 1140 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2: 1141 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0: 1142 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1: 1143 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2: 1144 priv->features |= FEATURE_IDF; 1145 /* fall through */ 1146 default: 1147 priv->features |= FEATURE_I2C_BLOCK_READ; 1148 priv->features |= FEATURE_IRQ; 1149 /* fall through */ 1150 case PCI_DEVICE_ID_INTEL_82801DB_3: 1151 priv->features |= FEATURE_SMBUS_PEC; 1152 priv->features |= FEATURE_BLOCK_BUFFER; 1153 /* fall through */ 1154 case PCI_DEVICE_ID_INTEL_82801CA_3: 1155 case PCI_DEVICE_ID_INTEL_82801BA_2: 1156 case PCI_DEVICE_ID_INTEL_82801AB_3: 1157 case PCI_DEVICE_ID_INTEL_82801AA_3: 1158 break; 1159 } 1160 1161 /* Disable features on user request */ 1162 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) { 1163 if (priv->features & disable_features & (1 << i)) 1164 dev_notice(&dev->dev, "%s disabled by user\n", 1165 i801_feature_names[i]); 1166 } 1167 priv->features &= ~disable_features; 1168 1169 err = pci_enable_device(dev); 1170 if (err) { 1171 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", 1172 err); 1173 goto exit; 1174 } 1175 1176 /* Determine the address of the SMBus area */ 1177 priv->smba = pci_resource_start(dev, SMBBAR); 1178 if (!priv->smba) { 1179 dev_err(&dev->dev, "SMBus base address uninitialized, " 1180 "upgrade BIOS\n"); 1181 err = -ENODEV; 1182 goto exit; 1183 } 1184 1185 err = acpi_check_resource_conflict(&dev->resource[SMBBAR]); 1186 if (err) { 1187 err = -ENODEV; 1188 goto exit; 1189 } 1190 1191 err = pci_request_region(dev, SMBBAR, i801_driver.name); 1192 if (err) { 1193 dev_err(&dev->dev, "Failed to request SMBus region " 1194 "0x%lx-0x%Lx\n", priv->smba, 1195 (unsigned long long)pci_resource_end(dev, SMBBAR)); 1196 goto exit; 1197 } 1198 1199 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp); 1200 priv->original_hstcfg = temp; 1201 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ 1202 if (!(temp & SMBHSTCFG_HST_EN)) { 1203 dev_info(&dev->dev, "Enabling SMBus device\n"); 1204 temp |= SMBHSTCFG_HST_EN; 1205 } 1206 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp); 1207 1208 if (temp & SMBHSTCFG_SMB_SMI_EN) { 1209 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); 1210 /* Disable SMBus interrupt feature if SMBus using SMI# */ 1211 priv->features &= ~FEATURE_IRQ; 1212 } 1213 1214 /* Clear special mode bits */ 1215 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) 1216 outb_p(inb_p(SMBAUXCTL(priv)) & 1217 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 1218 1219 if (priv->features & FEATURE_IRQ) { 1220 init_waitqueue_head(&priv->waitq); 1221 1222 err = request_irq(dev->irq, i801_isr, IRQF_SHARED, 1223 i801_driver.name, priv); 1224 if (err) { 1225 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n", 1226 dev->irq, err); 1227 goto exit_release; 1228 } 1229 dev_info(&dev->dev, "SMBus using PCI Interrupt\n"); 1230 } 1231 1232 /* set up the sysfs linkage to our parent device */ 1233 priv->adapter.dev.parent = &dev->dev; 1234 1235 /* Retry up to 3 times on lost arbitration */ 1236 priv->adapter.retries = 3; 1237 1238 snprintf(priv->adapter.name, sizeof(priv->adapter.name), 1239 "SMBus I801 adapter at %04lx", priv->smba); 1240 err = i2c_add_adapter(&priv->adapter); 1241 if (err) { 1242 dev_err(&dev->dev, "Failed to add SMBus adapter\n"); 1243 goto exit_free_irq; 1244 } 1245 1246 i801_probe_optional_slaves(priv); 1247 /* We ignore errors - multiplexing is optional */ 1248 i801_add_mux(priv); 1249 1250 pci_set_drvdata(dev, priv); 1251 1252 return 0; 1253 1254 exit_free_irq: 1255 if (priv->features & FEATURE_IRQ) 1256 free_irq(dev->irq, priv); 1257 exit_release: 1258 pci_release_region(dev, SMBBAR); 1259 exit: 1260 kfree(priv); 1261 return err; 1262 } 1263 1264 static void i801_remove(struct pci_dev *dev) 1265 { 1266 struct i801_priv *priv = pci_get_drvdata(dev); 1267 1268 i801_del_mux(priv); 1269 i2c_del_adapter(&priv->adapter); 1270 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); 1271 1272 if (priv->features & FEATURE_IRQ) 1273 free_irq(dev->irq, priv); 1274 pci_release_region(dev, SMBBAR); 1275 1276 kfree(priv); 1277 /* 1278 * do not call pci_disable_device(dev) since it can cause hard hangs on 1279 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) 1280 */ 1281 } 1282 1283 #ifdef CONFIG_PM 1284 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg) 1285 { 1286 struct i801_priv *priv = pci_get_drvdata(dev); 1287 1288 pci_save_state(dev); 1289 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); 1290 pci_set_power_state(dev, pci_choose_state(dev, mesg)); 1291 return 0; 1292 } 1293 1294 static int i801_resume(struct pci_dev *dev) 1295 { 1296 pci_set_power_state(dev, PCI_D0); 1297 pci_restore_state(dev); 1298 return pci_enable_device(dev); 1299 } 1300 #else 1301 #define i801_suspend NULL 1302 #define i801_resume NULL 1303 #endif 1304 1305 static struct pci_driver i801_driver = { 1306 .name = "i801_smbus", 1307 .id_table = i801_ids, 1308 .probe = i801_probe, 1309 .remove = i801_remove, 1310 .suspend = i801_suspend, 1311 .resume = i801_resume, 1312 }; 1313 1314 static int __init i2c_i801_init(void) 1315 { 1316 if (dmi_name_in_vendors("FUJITSU")) 1317 input_apanel_init(); 1318 return pci_register_driver(&i801_driver); 1319 } 1320 1321 static void __exit i2c_i801_exit(void) 1322 { 1323 pci_unregister_driver(&i801_driver); 1324 } 1325 1326 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>"); 1327 MODULE_DESCRIPTION("I801 SMBus driver"); 1328 MODULE_LICENSE("GPL"); 1329 1330 module_init(i2c_i801_init); 1331 module_exit(i2c_i801_exit); 1332