1 /* 2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, 3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker 4 <mdsxyz123@yahoo.com> 5 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de> 6 Copyright (C) 2010 Intel Corporation, 7 David Woodhouse <dwmw2@infradead.org> 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 2 of the License, or 12 (at your option) any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 */ 19 20 /* 21 * Supports the following Intel I/O Controller Hubs (ICH): 22 * 23 * I/O Block I2C 24 * region SMBus Block proc. block 25 * Chip name PCI ID size PEC buffer call read 26 * --------------------------------------------------------------------------- 27 * 82801AA (ICH) 0x2413 16 no no no no 28 * 82801AB (ICH0) 0x2423 16 no no no no 29 * 82801BA (ICH2) 0x2443 16 no no no no 30 * 82801CA (ICH3) 0x2483 32 soft no no no 31 * 82801DB (ICH4) 0x24c3 32 hard yes no no 32 * 82801E (ICH5) 0x24d3 32 hard yes yes yes 33 * 6300ESB 0x25a4 32 hard yes yes yes 34 * 82801F (ICH6) 0x266a 32 hard yes yes yes 35 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes 36 * 82801G (ICH7) 0x27da 32 hard yes yes yes 37 * 82801H (ICH8) 0x283e 32 hard yes yes yes 38 * 82801I (ICH9) 0x2930 32 hard yes yes yes 39 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes 40 * ICH10 0x3a30 32 hard yes yes yes 41 * ICH10 0x3a60 32 hard yes yes yes 42 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes 43 * 6 Series (PCH) 0x1c22 32 hard yes yes yes 44 * Patsburg (PCH) 0x1d22 32 hard yes yes yes 45 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes 46 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes 47 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes 48 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes 49 * Panther Point (PCH) 0x1e22 32 hard yes yes yes 50 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes 51 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes 52 * Avoton (SOC) 0x1f3c 32 hard yes yes yes 53 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes 54 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes 55 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes 56 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes 57 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes 58 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes 59 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes 60 * BayTrail (SOC) 0x0f12 32 hard yes yes yes 61 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes 62 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes 63 * 64 * Features supported by this driver: 65 * Software PEC no 66 * Hardware PEC yes 67 * Block buffer yes 68 * Block process call transaction no 69 * I2C block read transaction yes (doesn't use the block buffer) 70 * Slave mode no 71 * Interrupt processing yes 72 * 73 * See the file Documentation/i2c/busses/i2c-i801 for details. 74 */ 75 76 #include <linux/interrupt.h> 77 #include <linux/module.h> 78 #include <linux/pci.h> 79 #include <linux/kernel.h> 80 #include <linux/stddef.h> 81 #include <linux/delay.h> 82 #include <linux/ioport.h> 83 #include <linux/init.h> 84 #include <linux/i2c.h> 85 #include <linux/acpi.h> 86 #include <linux/io.h> 87 #include <linux/dmi.h> 88 #include <linux/slab.h> 89 #include <linux/wait.h> 90 #include <linux/err.h> 91 92 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \ 93 defined CONFIG_DMI 94 #include <linux/gpio.h> 95 #include <linux/i2c-mux-gpio.h> 96 #include <linux/platform_device.h> 97 #endif 98 99 /* I801 SMBus address offsets */ 100 #define SMBHSTSTS(p) (0 + (p)->smba) 101 #define SMBHSTCNT(p) (2 + (p)->smba) 102 #define SMBHSTCMD(p) (3 + (p)->smba) 103 #define SMBHSTADD(p) (4 + (p)->smba) 104 #define SMBHSTDAT0(p) (5 + (p)->smba) 105 #define SMBHSTDAT1(p) (6 + (p)->smba) 106 #define SMBBLKDAT(p) (7 + (p)->smba) 107 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */ 108 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */ 109 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */ 110 111 /* PCI Address Constants */ 112 #define SMBBAR 4 113 #define SMBPCICTL 0x004 114 #define SMBPCISTS 0x006 115 #define SMBHSTCFG 0x040 116 117 /* Host status bits for SMBPCISTS */ 118 #define SMBPCISTS_INTS 0x08 119 120 /* Control bits for SMBPCICTL */ 121 #define SMBPCICTL_INTDIS 0x0400 122 123 /* Host configuration bits for SMBHSTCFG */ 124 #define SMBHSTCFG_HST_EN 1 125 #define SMBHSTCFG_SMB_SMI_EN 2 126 #define SMBHSTCFG_I2C_EN 4 127 128 /* Auxiliary control register bits, ICH4+ only */ 129 #define SMBAUXCTL_CRC 1 130 #define SMBAUXCTL_E32B 2 131 132 /* Other settings */ 133 #define MAX_RETRIES 400 134 135 /* I801 command constants */ 136 #define I801_QUICK 0x00 137 #define I801_BYTE 0x04 138 #define I801_BYTE_DATA 0x08 139 #define I801_WORD_DATA 0x0C 140 #define I801_PROC_CALL 0x10 /* unimplemented */ 141 #define I801_BLOCK_DATA 0x14 142 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ 143 144 /* I801 Host Control register bits */ 145 #define SMBHSTCNT_INTREN 0x01 146 #define SMBHSTCNT_KILL 0x02 147 #define SMBHSTCNT_LAST_BYTE 0x20 148 #define SMBHSTCNT_START 0x40 149 #define SMBHSTCNT_PEC_EN 0x80 /* ICH3 and later */ 150 151 /* I801 Hosts Status register bits */ 152 #define SMBHSTSTS_BYTE_DONE 0x80 153 #define SMBHSTSTS_INUSE_STS 0x40 154 #define SMBHSTSTS_SMBALERT_STS 0x20 155 #define SMBHSTSTS_FAILED 0x10 156 #define SMBHSTSTS_BUS_ERR 0x08 157 #define SMBHSTSTS_DEV_ERR 0x04 158 #define SMBHSTSTS_INTR 0x02 159 #define SMBHSTSTS_HOST_BUSY 0x01 160 161 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \ 162 SMBHSTSTS_DEV_ERR) 163 164 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \ 165 STATUS_ERROR_FLAGS) 166 167 /* Older devices have their ID defined in <linux/pci_ids.h> */ 168 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12 169 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292 170 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 171 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 172 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */ 173 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70 174 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71 175 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72 176 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 177 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c 178 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 179 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0 180 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 181 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 182 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2 183 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22 184 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d 185 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e 186 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f 187 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22 188 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2 189 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123 190 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23 191 192 struct i801_mux_config { 193 char *gpio_chip; 194 unsigned values[3]; 195 int n_values; 196 unsigned classes[3]; 197 unsigned gpios[2]; /* Relative to gpio_chip->base */ 198 int n_gpios; 199 }; 200 201 struct i801_priv { 202 struct i2c_adapter adapter; 203 unsigned long smba; 204 unsigned char original_hstcfg; 205 struct pci_dev *pci_dev; 206 unsigned int features; 207 208 /* isr processing */ 209 wait_queue_head_t waitq; 210 u8 status; 211 212 /* Command state used by isr for byte-by-byte block transactions */ 213 u8 cmd; 214 bool is_read; 215 int count; 216 int len; 217 u8 *data; 218 219 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \ 220 defined CONFIG_DMI 221 const struct i801_mux_config *mux_drvdata; 222 struct platform_device *mux_pdev; 223 #endif 224 }; 225 226 #define FEATURE_SMBUS_PEC (1 << 0) 227 #define FEATURE_BLOCK_BUFFER (1 << 1) 228 #define FEATURE_BLOCK_PROC (1 << 2) 229 #define FEATURE_I2C_BLOCK_READ (1 << 3) 230 #define FEATURE_IRQ (1 << 4) 231 /* Not really a feature, but it's convenient to handle it as such */ 232 #define FEATURE_IDF (1 << 15) 233 234 static const char *i801_feature_names[] = { 235 "SMBus PEC", 236 "Block buffer", 237 "Block process call", 238 "I2C block read", 239 "Interrupt", 240 }; 241 242 static unsigned int disable_features; 243 module_param(disable_features, uint, S_IRUGO | S_IWUSR); 244 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n" 245 "\t\t 0x01 disable SMBus PEC\n" 246 "\t\t 0x02 disable the block buffer\n" 247 "\t\t 0x08 disable the I2C block read functionality\n" 248 "\t\t 0x10 don't use interrupts "); 249 250 /* Make sure the SMBus host is ready to start transmitting. 251 Return 0 if it is, -EBUSY if it is not. */ 252 static int i801_check_pre(struct i801_priv *priv) 253 { 254 int status; 255 256 status = inb_p(SMBHSTSTS(priv)); 257 if (status & SMBHSTSTS_HOST_BUSY) { 258 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n"); 259 return -EBUSY; 260 } 261 262 status &= STATUS_FLAGS; 263 if (status) { 264 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n", 265 status); 266 outb_p(status, SMBHSTSTS(priv)); 267 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS; 268 if (status) { 269 dev_err(&priv->pci_dev->dev, 270 "Failed clearing status flags (%02x)\n", 271 status); 272 return -EBUSY; 273 } 274 } 275 276 return 0; 277 } 278 279 /* 280 * Convert the status register to an error code, and clear it. 281 * Note that status only contains the bits we want to clear, not the 282 * actual register value. 283 */ 284 static int i801_check_post(struct i801_priv *priv, int status) 285 { 286 int result = 0; 287 288 /* 289 * If the SMBus is still busy, we give up 290 * Note: This timeout condition only happens when using polling 291 * transactions. For interrupt operation, NAK/timeout is indicated by 292 * DEV_ERR. 293 */ 294 if (unlikely(status < 0)) { 295 dev_err(&priv->pci_dev->dev, "Transaction timeout\n"); 296 /* try to stop the current command */ 297 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n"); 298 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL, 299 SMBHSTCNT(priv)); 300 usleep_range(1000, 2000); 301 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL), 302 SMBHSTCNT(priv)); 303 304 /* Check if it worked */ 305 status = inb_p(SMBHSTSTS(priv)); 306 if ((status & SMBHSTSTS_HOST_BUSY) || 307 !(status & SMBHSTSTS_FAILED)) 308 dev_err(&priv->pci_dev->dev, 309 "Failed terminating the transaction\n"); 310 outb_p(STATUS_FLAGS, SMBHSTSTS(priv)); 311 return -ETIMEDOUT; 312 } 313 314 if (status & SMBHSTSTS_FAILED) { 315 result = -EIO; 316 dev_err(&priv->pci_dev->dev, "Transaction failed\n"); 317 } 318 if (status & SMBHSTSTS_DEV_ERR) { 319 result = -ENXIO; 320 dev_dbg(&priv->pci_dev->dev, "No response\n"); 321 } 322 if (status & SMBHSTSTS_BUS_ERR) { 323 result = -EAGAIN; 324 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n"); 325 } 326 327 /* Clear status flags except BYTE_DONE, to be cleared by caller */ 328 outb_p(status, SMBHSTSTS(priv)); 329 330 return result; 331 } 332 333 /* Wait for BUSY being cleared and either INTR or an error flag being set */ 334 static int i801_wait_intr(struct i801_priv *priv) 335 { 336 int timeout = 0; 337 int status; 338 339 /* We will always wait for a fraction of a second! */ 340 do { 341 usleep_range(250, 500); 342 status = inb_p(SMBHSTSTS(priv)); 343 } while (((status & SMBHSTSTS_HOST_BUSY) || 344 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) && 345 (timeout++ < MAX_RETRIES)); 346 347 if (timeout > MAX_RETRIES) { 348 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n"); 349 return -ETIMEDOUT; 350 } 351 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR); 352 } 353 354 /* Wait for either BYTE_DONE or an error flag being set */ 355 static int i801_wait_byte_done(struct i801_priv *priv) 356 { 357 int timeout = 0; 358 int status; 359 360 /* We will always wait for a fraction of a second! */ 361 do { 362 usleep_range(250, 500); 363 status = inb_p(SMBHSTSTS(priv)); 364 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) && 365 (timeout++ < MAX_RETRIES)); 366 367 if (timeout > MAX_RETRIES) { 368 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n"); 369 return -ETIMEDOUT; 370 } 371 return status & STATUS_ERROR_FLAGS; 372 } 373 374 static int i801_transaction(struct i801_priv *priv, int xact) 375 { 376 int status; 377 int result; 378 const struct i2c_adapter *adap = &priv->adapter; 379 380 result = i801_check_pre(priv); 381 if (result < 0) 382 return result; 383 384 if (priv->features & FEATURE_IRQ) { 385 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START, 386 SMBHSTCNT(priv)); 387 result = wait_event_timeout(priv->waitq, 388 (status = priv->status), 389 adap->timeout); 390 if (!result) { 391 status = -ETIMEDOUT; 392 dev_warn(&priv->pci_dev->dev, 393 "Timeout waiting for interrupt!\n"); 394 } 395 priv->status = 0; 396 return i801_check_post(priv, status); 397 } 398 399 /* the current contents of SMBHSTCNT can be overwritten, since PEC, 400 * SMBSCMD are passed in xact */ 401 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv)); 402 403 status = i801_wait_intr(priv); 404 return i801_check_post(priv, status); 405 } 406 407 static int i801_block_transaction_by_block(struct i801_priv *priv, 408 union i2c_smbus_data *data, 409 char read_write, int hwpec) 410 { 411 int i, len; 412 int status; 413 414 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ 415 416 /* Use 32-byte buffer to process this transaction */ 417 if (read_write == I2C_SMBUS_WRITE) { 418 len = data->block[0]; 419 outb_p(len, SMBHSTDAT0(priv)); 420 for (i = 0; i < len; i++) 421 outb_p(data->block[i+1], SMBBLKDAT(priv)); 422 } 423 424 status = i801_transaction(priv, I801_BLOCK_DATA | 425 (hwpec ? SMBHSTCNT_PEC_EN : 0)); 426 if (status) 427 return status; 428 429 if (read_write == I2C_SMBUS_READ) { 430 len = inb_p(SMBHSTDAT0(priv)); 431 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) 432 return -EPROTO; 433 434 data->block[0] = len; 435 for (i = 0; i < len; i++) 436 data->block[i + 1] = inb_p(SMBBLKDAT(priv)); 437 } 438 return 0; 439 } 440 441 static void i801_isr_byte_done(struct i801_priv *priv) 442 { 443 if (priv->is_read) { 444 /* For SMBus block reads, length is received with first byte */ 445 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) && 446 (priv->count == 0)) { 447 priv->len = inb_p(SMBHSTDAT0(priv)); 448 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) { 449 dev_err(&priv->pci_dev->dev, 450 "Illegal SMBus block read size %d\n", 451 priv->len); 452 /* FIXME: Recover */ 453 priv->len = I2C_SMBUS_BLOCK_MAX; 454 } else { 455 dev_dbg(&priv->pci_dev->dev, 456 "SMBus block read size is %d\n", 457 priv->len); 458 } 459 priv->data[-1] = priv->len; 460 } 461 462 /* Read next byte */ 463 if (priv->count < priv->len) 464 priv->data[priv->count++] = inb(SMBBLKDAT(priv)); 465 else 466 dev_dbg(&priv->pci_dev->dev, 467 "Discarding extra byte on block read\n"); 468 469 /* Set LAST_BYTE for last byte of read transaction */ 470 if (priv->count == priv->len - 1) 471 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE, 472 SMBHSTCNT(priv)); 473 } else if (priv->count < priv->len - 1) { 474 /* Write next byte, except for IRQ after last byte */ 475 outb_p(priv->data[++priv->count], SMBBLKDAT(priv)); 476 } 477 478 /* Clear BYTE_DONE to continue with next byte */ 479 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 480 } 481 482 /* 483 * There are two kinds of interrupts: 484 * 485 * 1) i801 signals transaction completion with one of these interrupts: 486 * INTR - Success 487 * DEV_ERR - Invalid command, NAK or communication timeout 488 * BUS_ERR - SMI# transaction collision 489 * FAILED - transaction was canceled due to a KILL request 490 * When any of these occur, update ->status and wake up the waitq. 491 * ->status must be cleared before kicking off the next transaction. 492 * 493 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt 494 * occurs for each byte of a byte-by-byte to prepare the next byte. 495 */ 496 static irqreturn_t i801_isr(int irq, void *dev_id) 497 { 498 struct i801_priv *priv = dev_id; 499 u16 pcists; 500 u8 status; 501 502 /* Confirm this is our interrupt */ 503 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); 504 if (!(pcists & SMBPCISTS_INTS)) 505 return IRQ_NONE; 506 507 status = inb_p(SMBHSTSTS(priv)); 508 if (status & SMBHSTSTS_BYTE_DONE) 509 i801_isr_byte_done(priv); 510 511 /* 512 * Clear irq sources and report transaction result. 513 * ->status must be cleared before the next transaction is started. 514 */ 515 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS; 516 if (status) { 517 outb_p(status, SMBHSTSTS(priv)); 518 priv->status |= status; 519 wake_up(&priv->waitq); 520 } 521 522 return IRQ_HANDLED; 523 } 524 525 /* 526 * For "byte-by-byte" block transactions: 527 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1 528 * I2C read uses cmd=I801_I2C_BLOCK_DATA 529 */ 530 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, 531 union i2c_smbus_data *data, 532 char read_write, int command, 533 int hwpec) 534 { 535 int i, len; 536 int smbcmd; 537 int status; 538 int result; 539 const struct i2c_adapter *adap = &priv->adapter; 540 541 result = i801_check_pre(priv); 542 if (result < 0) 543 return result; 544 545 len = data->block[0]; 546 547 if (read_write == I2C_SMBUS_WRITE) { 548 outb_p(len, SMBHSTDAT0(priv)); 549 outb_p(data->block[1], SMBBLKDAT(priv)); 550 } 551 552 if (command == I2C_SMBUS_I2C_BLOCK_DATA && 553 read_write == I2C_SMBUS_READ) 554 smbcmd = I801_I2C_BLOCK_DATA; 555 else 556 smbcmd = I801_BLOCK_DATA; 557 558 if (priv->features & FEATURE_IRQ) { 559 priv->is_read = (read_write == I2C_SMBUS_READ); 560 if (len == 1 && priv->is_read) 561 smbcmd |= SMBHSTCNT_LAST_BYTE; 562 priv->cmd = smbcmd | SMBHSTCNT_INTREN; 563 priv->len = len; 564 priv->count = 0; 565 priv->data = &data->block[1]; 566 567 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv)); 568 result = wait_event_timeout(priv->waitq, 569 (status = priv->status), 570 adap->timeout); 571 if (!result) { 572 status = -ETIMEDOUT; 573 dev_warn(&priv->pci_dev->dev, 574 "Timeout waiting for interrupt!\n"); 575 } 576 priv->status = 0; 577 return i801_check_post(priv, status); 578 } 579 580 for (i = 1; i <= len; i++) { 581 if (i == len && read_write == I2C_SMBUS_READ) 582 smbcmd |= SMBHSTCNT_LAST_BYTE; 583 outb_p(smbcmd, SMBHSTCNT(priv)); 584 585 if (i == 1) 586 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START, 587 SMBHSTCNT(priv)); 588 589 status = i801_wait_byte_done(priv); 590 if (status) 591 goto exit; 592 593 if (i == 1 && read_write == I2C_SMBUS_READ 594 && command != I2C_SMBUS_I2C_BLOCK_DATA) { 595 len = inb_p(SMBHSTDAT0(priv)); 596 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { 597 dev_err(&priv->pci_dev->dev, 598 "Illegal SMBus block read size %d\n", 599 len); 600 /* Recover */ 601 while (inb_p(SMBHSTSTS(priv)) & 602 SMBHSTSTS_HOST_BUSY) 603 outb_p(SMBHSTSTS_BYTE_DONE, 604 SMBHSTSTS(priv)); 605 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); 606 return -EPROTO; 607 } 608 data->block[0] = len; 609 } 610 611 /* Retrieve/store value in SMBBLKDAT */ 612 if (read_write == I2C_SMBUS_READ) 613 data->block[i] = inb_p(SMBBLKDAT(priv)); 614 if (read_write == I2C_SMBUS_WRITE && i+1 <= len) 615 outb_p(data->block[i+1], SMBBLKDAT(priv)); 616 617 /* signals SMBBLKDAT ready */ 618 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 619 } 620 621 status = i801_wait_intr(priv); 622 exit: 623 return i801_check_post(priv, status); 624 } 625 626 static int i801_set_block_buffer_mode(struct i801_priv *priv) 627 { 628 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv)); 629 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0) 630 return -EIO; 631 return 0; 632 } 633 634 /* Block transaction function */ 635 static int i801_block_transaction(struct i801_priv *priv, 636 union i2c_smbus_data *data, char read_write, 637 int command, int hwpec) 638 { 639 int result = 0; 640 unsigned char hostc; 641 642 if (command == I2C_SMBUS_I2C_BLOCK_DATA) { 643 if (read_write == I2C_SMBUS_WRITE) { 644 /* set I2C_EN bit in configuration register */ 645 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc); 646 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, 647 hostc | SMBHSTCFG_I2C_EN); 648 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) { 649 dev_err(&priv->pci_dev->dev, 650 "I2C block read is unsupported!\n"); 651 return -EOPNOTSUPP; 652 } 653 } 654 655 if (read_write == I2C_SMBUS_WRITE 656 || command == I2C_SMBUS_I2C_BLOCK_DATA) { 657 if (data->block[0] < 1) 658 data->block[0] = 1; 659 if (data->block[0] > I2C_SMBUS_BLOCK_MAX) 660 data->block[0] = I2C_SMBUS_BLOCK_MAX; 661 } else { 662 data->block[0] = 32; /* max for SMBus block reads */ 663 } 664 665 /* Experience has shown that the block buffer can only be used for 666 SMBus (not I2C) block transactions, even though the datasheet 667 doesn't mention this limitation. */ 668 if ((priv->features & FEATURE_BLOCK_BUFFER) 669 && command != I2C_SMBUS_I2C_BLOCK_DATA 670 && i801_set_block_buffer_mode(priv) == 0) 671 result = i801_block_transaction_by_block(priv, data, 672 read_write, hwpec); 673 else 674 result = i801_block_transaction_byte_by_byte(priv, data, 675 read_write, 676 command, hwpec); 677 678 if (command == I2C_SMBUS_I2C_BLOCK_DATA 679 && read_write == I2C_SMBUS_WRITE) { 680 /* restore saved configuration register value */ 681 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc); 682 } 683 return result; 684 } 685 686 /* Return negative errno on error. */ 687 static s32 i801_access(struct i2c_adapter *adap, u16 addr, 688 unsigned short flags, char read_write, u8 command, 689 int size, union i2c_smbus_data *data) 690 { 691 int hwpec; 692 int block = 0; 693 int ret, xact = 0; 694 struct i801_priv *priv = i2c_get_adapdata(adap); 695 696 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) 697 && size != I2C_SMBUS_QUICK 698 && size != I2C_SMBUS_I2C_BLOCK_DATA; 699 700 switch (size) { 701 case I2C_SMBUS_QUICK: 702 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 703 SMBHSTADD(priv)); 704 xact = I801_QUICK; 705 break; 706 case I2C_SMBUS_BYTE: 707 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 708 SMBHSTADD(priv)); 709 if (read_write == I2C_SMBUS_WRITE) 710 outb_p(command, SMBHSTCMD(priv)); 711 xact = I801_BYTE; 712 break; 713 case I2C_SMBUS_BYTE_DATA: 714 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 715 SMBHSTADD(priv)); 716 outb_p(command, SMBHSTCMD(priv)); 717 if (read_write == I2C_SMBUS_WRITE) 718 outb_p(data->byte, SMBHSTDAT0(priv)); 719 xact = I801_BYTE_DATA; 720 break; 721 case I2C_SMBUS_WORD_DATA: 722 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 723 SMBHSTADD(priv)); 724 outb_p(command, SMBHSTCMD(priv)); 725 if (read_write == I2C_SMBUS_WRITE) { 726 outb_p(data->word & 0xff, SMBHSTDAT0(priv)); 727 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); 728 } 729 xact = I801_WORD_DATA; 730 break; 731 case I2C_SMBUS_BLOCK_DATA: 732 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 733 SMBHSTADD(priv)); 734 outb_p(command, SMBHSTCMD(priv)); 735 block = 1; 736 break; 737 case I2C_SMBUS_I2C_BLOCK_DATA: 738 /* NB: page 240 of ICH5 datasheet shows that the R/#W 739 * bit should be cleared here, even when reading */ 740 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv)); 741 if (read_write == I2C_SMBUS_READ) { 742 /* NB: page 240 of ICH5 datasheet also shows 743 * that DATA1 is the cmd field when reading */ 744 outb_p(command, SMBHSTDAT1(priv)); 745 } else 746 outb_p(command, SMBHSTCMD(priv)); 747 block = 1; 748 break; 749 default: 750 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n", 751 size); 752 return -EOPNOTSUPP; 753 } 754 755 if (hwpec) /* enable/disable hardware PEC */ 756 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv)); 757 else 758 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC), 759 SMBAUXCTL(priv)); 760 761 if (block) 762 ret = i801_block_transaction(priv, data, read_write, size, 763 hwpec); 764 else 765 ret = i801_transaction(priv, xact); 766 767 /* Some BIOSes don't like it when PEC is enabled at reboot or resume 768 time, so we forcibly disable it after every transaction. Turn off 769 E32B for the same reason. */ 770 if (hwpec || block) 771 outb_p(inb_p(SMBAUXCTL(priv)) & 772 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 773 774 if (block) 775 return ret; 776 if (ret) 777 return ret; 778 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK)) 779 return 0; 780 781 switch (xact & 0x7f) { 782 case I801_BYTE: /* Result put in SMBHSTDAT0 */ 783 case I801_BYTE_DATA: 784 data->byte = inb_p(SMBHSTDAT0(priv)); 785 break; 786 case I801_WORD_DATA: 787 data->word = inb_p(SMBHSTDAT0(priv)) + 788 (inb_p(SMBHSTDAT1(priv)) << 8); 789 break; 790 } 791 return 0; 792 } 793 794 795 static u32 i801_func(struct i2c_adapter *adapter) 796 { 797 struct i801_priv *priv = i2c_get_adapdata(adapter); 798 799 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 800 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 801 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | 802 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | 803 ((priv->features & FEATURE_I2C_BLOCK_READ) ? 804 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0); 805 } 806 807 static const struct i2c_algorithm smbus_algorithm = { 808 .smbus_xfer = i801_access, 809 .functionality = i801_func, 810 }; 811 812 static const struct pci_device_id i801_ids[] = { 813 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) }, 814 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) }, 815 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) }, 816 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) }, 817 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) }, 818 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) }, 819 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) }, 820 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) }, 821 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) }, 822 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) }, 823 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) }, 824 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) }, 825 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) }, 826 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) }, 827 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) }, 828 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) }, 829 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) }, 830 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) }, 831 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) }, 832 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) }, 833 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) }, 834 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) }, 835 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) }, 836 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) }, 837 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) }, 838 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) }, 839 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) }, 840 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) }, 841 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) }, 842 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) }, 843 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) }, 844 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) }, 845 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) }, 846 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) }, 847 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) }, 848 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) }, 849 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) }, 850 { 0, } 851 }; 852 853 MODULE_DEVICE_TABLE(pci, i801_ids); 854 855 #if defined CONFIG_X86 && defined CONFIG_DMI 856 static unsigned char apanel_addr; 857 858 /* Scan the system ROM for the signature "FJKEYINF" */ 859 static __init const void __iomem *bios_signature(const void __iomem *bios) 860 { 861 ssize_t offset; 862 const unsigned char signature[] = "FJKEYINF"; 863 864 for (offset = 0; offset < 0x10000; offset += 0x10) { 865 if (check_signature(bios + offset, signature, 866 sizeof(signature)-1)) 867 return bios + offset; 868 } 869 return NULL; 870 } 871 872 static void __init input_apanel_init(void) 873 { 874 void __iomem *bios; 875 const void __iomem *p; 876 877 bios = ioremap(0xF0000, 0x10000); /* Can't fail */ 878 p = bios_signature(bios); 879 if (p) { 880 /* just use the first address */ 881 apanel_addr = readb(p + 8 + 3) >> 1; 882 } 883 iounmap(bios); 884 } 885 886 struct dmi_onboard_device_info { 887 const char *name; 888 u8 type; 889 unsigned short i2c_addr; 890 const char *i2c_type; 891 }; 892 893 static const struct dmi_onboard_device_info dmi_devices[] = { 894 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" }, 895 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" }, 896 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" }, 897 }; 898 899 static void dmi_check_onboard_device(u8 type, const char *name, 900 struct i2c_adapter *adap) 901 { 902 int i; 903 struct i2c_board_info info; 904 905 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) { 906 /* & ~0x80, ignore enabled/disabled bit */ 907 if ((type & ~0x80) != dmi_devices[i].type) 908 continue; 909 if (strcasecmp(name, dmi_devices[i].name)) 910 continue; 911 912 memset(&info, 0, sizeof(struct i2c_board_info)); 913 info.addr = dmi_devices[i].i2c_addr; 914 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); 915 i2c_new_device(adap, &info); 916 break; 917 } 918 } 919 920 /* We use our own function to check for onboard devices instead of 921 dmi_find_device() as some buggy BIOS's have the devices we are interested 922 in marked as disabled */ 923 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap) 924 { 925 int i, count; 926 927 if (dm->type != 10) 928 return; 929 930 count = (dm->length - sizeof(struct dmi_header)) / 2; 931 for (i = 0; i < count; i++) { 932 const u8 *d = (char *)(dm + 1) + (i * 2); 933 const char *name = ((char *) dm) + dm->length; 934 u8 type = d[0]; 935 u8 s = d[1]; 936 937 if (!s) 938 continue; 939 s--; 940 while (s > 0 && name[0]) { 941 name += strlen(name) + 1; 942 s--; 943 } 944 if (name[0] == 0) /* Bogus string reference */ 945 continue; 946 947 dmi_check_onboard_device(type, name, adap); 948 } 949 } 950 951 /* Register optional slaves */ 952 static void i801_probe_optional_slaves(struct i801_priv *priv) 953 { 954 /* Only register slaves on main SMBus channel */ 955 if (priv->features & FEATURE_IDF) 956 return; 957 958 if (apanel_addr) { 959 struct i2c_board_info info; 960 961 memset(&info, 0, sizeof(struct i2c_board_info)); 962 info.addr = apanel_addr; 963 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE); 964 i2c_new_device(&priv->adapter, &info); 965 } 966 967 if (dmi_name_in_vendors("FUJITSU")) 968 dmi_walk(dmi_check_onboard_devices, &priv->adapter); 969 } 970 #else 971 static void __init input_apanel_init(void) {} 972 static void i801_probe_optional_slaves(struct i801_priv *priv) {} 973 #endif /* CONFIG_X86 && CONFIG_DMI */ 974 975 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \ 976 defined CONFIG_DMI 977 static struct i801_mux_config i801_mux_config_asus_z8_d12 = { 978 .gpio_chip = "gpio_ich", 979 .values = { 0x02, 0x03 }, 980 .n_values = 2, 981 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD }, 982 .gpios = { 52, 53 }, 983 .n_gpios = 2, 984 }; 985 986 static struct i801_mux_config i801_mux_config_asus_z8_d18 = { 987 .gpio_chip = "gpio_ich", 988 .values = { 0x02, 0x03, 0x01 }, 989 .n_values = 3, 990 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD }, 991 .gpios = { 52, 53 }, 992 .n_gpios = 2, 993 }; 994 995 static const struct dmi_system_id mux_dmi_table[] = { 996 { 997 .matches = { 998 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 999 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"), 1000 }, 1001 .driver_data = &i801_mux_config_asus_z8_d12, 1002 }, 1003 { 1004 .matches = { 1005 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1006 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"), 1007 }, 1008 .driver_data = &i801_mux_config_asus_z8_d12, 1009 }, 1010 { 1011 .matches = { 1012 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1013 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"), 1014 }, 1015 .driver_data = &i801_mux_config_asus_z8_d12, 1016 }, 1017 { 1018 .matches = { 1019 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1020 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"), 1021 }, 1022 .driver_data = &i801_mux_config_asus_z8_d12, 1023 }, 1024 { 1025 .matches = { 1026 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1027 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"), 1028 }, 1029 .driver_data = &i801_mux_config_asus_z8_d12, 1030 }, 1031 { 1032 .matches = { 1033 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1034 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"), 1035 }, 1036 .driver_data = &i801_mux_config_asus_z8_d12, 1037 }, 1038 { 1039 .matches = { 1040 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1041 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"), 1042 }, 1043 .driver_data = &i801_mux_config_asus_z8_d18, 1044 }, 1045 { 1046 .matches = { 1047 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1048 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"), 1049 }, 1050 .driver_data = &i801_mux_config_asus_z8_d18, 1051 }, 1052 { 1053 .matches = { 1054 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1055 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"), 1056 }, 1057 .driver_data = &i801_mux_config_asus_z8_d12, 1058 }, 1059 { } 1060 }; 1061 1062 /* Setup multiplexing if needed */ 1063 static int i801_add_mux(struct i801_priv *priv) 1064 { 1065 struct device *dev = &priv->adapter.dev; 1066 const struct i801_mux_config *mux_config; 1067 struct i2c_mux_gpio_platform_data gpio_data; 1068 int err; 1069 1070 if (!priv->mux_drvdata) 1071 return 0; 1072 mux_config = priv->mux_drvdata; 1073 1074 /* Prepare the platform data */ 1075 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data)); 1076 gpio_data.parent = priv->adapter.nr; 1077 gpio_data.values = mux_config->values; 1078 gpio_data.n_values = mux_config->n_values; 1079 gpio_data.classes = mux_config->classes; 1080 gpio_data.gpio_chip = mux_config->gpio_chip; 1081 gpio_data.gpios = mux_config->gpios; 1082 gpio_data.n_gpios = mux_config->n_gpios; 1083 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE; 1084 1085 /* Register the mux device */ 1086 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio", 1087 PLATFORM_DEVID_AUTO, &gpio_data, 1088 sizeof(struct i2c_mux_gpio_platform_data)); 1089 if (IS_ERR(priv->mux_pdev)) { 1090 err = PTR_ERR(priv->mux_pdev); 1091 priv->mux_pdev = NULL; 1092 dev_err(dev, "Failed to register i2c-mux-gpio device\n"); 1093 return err; 1094 } 1095 1096 return 0; 1097 } 1098 1099 static void i801_del_mux(struct i801_priv *priv) 1100 { 1101 if (priv->mux_pdev) 1102 platform_device_unregister(priv->mux_pdev); 1103 } 1104 1105 static unsigned int i801_get_adapter_class(struct i801_priv *priv) 1106 { 1107 const struct dmi_system_id *id; 1108 const struct i801_mux_config *mux_config; 1109 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 1110 int i; 1111 1112 id = dmi_first_match(mux_dmi_table); 1113 if (id) { 1114 /* Remove branch classes from trunk */ 1115 mux_config = id->driver_data; 1116 for (i = 0; i < mux_config->n_values; i++) 1117 class &= ~mux_config->classes[i]; 1118 1119 /* Remember for later */ 1120 priv->mux_drvdata = mux_config; 1121 } 1122 1123 return class; 1124 } 1125 #else 1126 static inline int i801_add_mux(struct i801_priv *priv) { return 0; } 1127 static inline void i801_del_mux(struct i801_priv *priv) { } 1128 1129 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv) 1130 { 1131 return I2C_CLASS_HWMON | I2C_CLASS_SPD; 1132 } 1133 #endif 1134 1135 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id) 1136 { 1137 unsigned char temp; 1138 int err, i; 1139 struct i801_priv *priv; 1140 1141 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL); 1142 if (!priv) 1143 return -ENOMEM; 1144 1145 i2c_set_adapdata(&priv->adapter, priv); 1146 priv->adapter.owner = THIS_MODULE; 1147 priv->adapter.class = i801_get_adapter_class(priv); 1148 priv->adapter.algo = &smbus_algorithm; 1149 1150 priv->pci_dev = dev; 1151 switch (dev->device) { 1152 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0: 1153 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1: 1154 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2: 1155 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0: 1156 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1: 1157 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2: 1158 priv->features |= FEATURE_IDF; 1159 /* fall through */ 1160 default: 1161 priv->features |= FEATURE_I2C_BLOCK_READ; 1162 priv->features |= FEATURE_IRQ; 1163 /* fall through */ 1164 case PCI_DEVICE_ID_INTEL_82801DB_3: 1165 priv->features |= FEATURE_SMBUS_PEC; 1166 priv->features |= FEATURE_BLOCK_BUFFER; 1167 /* fall through */ 1168 case PCI_DEVICE_ID_INTEL_82801CA_3: 1169 case PCI_DEVICE_ID_INTEL_82801BA_2: 1170 case PCI_DEVICE_ID_INTEL_82801AB_3: 1171 case PCI_DEVICE_ID_INTEL_82801AA_3: 1172 break; 1173 } 1174 1175 /* Disable features on user request */ 1176 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) { 1177 if (priv->features & disable_features & (1 << i)) 1178 dev_notice(&dev->dev, "%s disabled by user\n", 1179 i801_feature_names[i]); 1180 } 1181 priv->features &= ~disable_features; 1182 1183 err = pcim_enable_device(dev); 1184 if (err) { 1185 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", 1186 err); 1187 return err; 1188 } 1189 pcim_pin_device(dev); 1190 1191 /* Determine the address of the SMBus area */ 1192 priv->smba = pci_resource_start(dev, SMBBAR); 1193 if (!priv->smba) { 1194 dev_err(&dev->dev, 1195 "SMBus base address uninitialized, upgrade BIOS\n"); 1196 return -ENODEV; 1197 } 1198 1199 err = acpi_check_resource_conflict(&dev->resource[SMBBAR]); 1200 if (err) { 1201 return -ENODEV; 1202 } 1203 1204 err = pcim_iomap_regions(dev, 1 << SMBBAR, 1205 dev_driver_string(&dev->dev)); 1206 if (err) { 1207 dev_err(&dev->dev, 1208 "Failed to request SMBus region 0x%lx-0x%Lx\n", 1209 priv->smba, 1210 (unsigned long long)pci_resource_end(dev, SMBBAR)); 1211 return err; 1212 } 1213 1214 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp); 1215 priv->original_hstcfg = temp; 1216 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ 1217 if (!(temp & SMBHSTCFG_HST_EN)) { 1218 dev_info(&dev->dev, "Enabling SMBus device\n"); 1219 temp |= SMBHSTCFG_HST_EN; 1220 } 1221 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp); 1222 1223 if (temp & SMBHSTCFG_SMB_SMI_EN) { 1224 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); 1225 /* Disable SMBus interrupt feature if SMBus using SMI# */ 1226 priv->features &= ~FEATURE_IRQ; 1227 } 1228 1229 /* Clear special mode bits */ 1230 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) 1231 outb_p(inb_p(SMBAUXCTL(priv)) & 1232 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 1233 1234 /* Default timeout in interrupt mode: 200 ms */ 1235 priv->adapter.timeout = HZ / 5; 1236 1237 if (priv->features & FEATURE_IRQ) { 1238 u16 pcictl, pcists; 1239 1240 /* Complain if an interrupt is already pending */ 1241 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); 1242 if (pcists & SMBPCISTS_INTS) 1243 dev_warn(&dev->dev, "An interrupt is pending!\n"); 1244 1245 /* Check if interrupts have been disabled */ 1246 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl); 1247 if (pcictl & SMBPCICTL_INTDIS) { 1248 dev_info(&dev->dev, "Interrupts are disabled\n"); 1249 priv->features &= ~FEATURE_IRQ; 1250 } 1251 } 1252 1253 if (priv->features & FEATURE_IRQ) { 1254 init_waitqueue_head(&priv->waitq); 1255 1256 err = devm_request_irq(&dev->dev, dev->irq, i801_isr, 1257 IRQF_SHARED, 1258 dev_driver_string(&dev->dev), priv); 1259 if (err) { 1260 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n", 1261 dev->irq, err); 1262 priv->features &= ~FEATURE_IRQ; 1263 } 1264 } 1265 dev_info(&dev->dev, "SMBus using %s\n", 1266 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling"); 1267 1268 /* set up the sysfs linkage to our parent device */ 1269 priv->adapter.dev.parent = &dev->dev; 1270 1271 /* Retry up to 3 times on lost arbitration */ 1272 priv->adapter.retries = 3; 1273 1274 snprintf(priv->adapter.name, sizeof(priv->adapter.name), 1275 "SMBus I801 adapter at %04lx", priv->smba); 1276 err = i2c_add_adapter(&priv->adapter); 1277 if (err) { 1278 dev_err(&dev->dev, "Failed to add SMBus adapter\n"); 1279 return err; 1280 } 1281 1282 i801_probe_optional_slaves(priv); 1283 /* We ignore errors - multiplexing is optional */ 1284 i801_add_mux(priv); 1285 1286 pci_set_drvdata(dev, priv); 1287 1288 return 0; 1289 } 1290 1291 static void i801_remove(struct pci_dev *dev) 1292 { 1293 struct i801_priv *priv = pci_get_drvdata(dev); 1294 1295 i801_del_mux(priv); 1296 i2c_del_adapter(&priv->adapter); 1297 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); 1298 1299 /* 1300 * do not call pci_disable_device(dev) since it can cause hard hangs on 1301 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) 1302 */ 1303 } 1304 1305 #ifdef CONFIG_PM 1306 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg) 1307 { 1308 struct i801_priv *priv = pci_get_drvdata(dev); 1309 1310 pci_save_state(dev); 1311 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); 1312 pci_set_power_state(dev, pci_choose_state(dev, mesg)); 1313 return 0; 1314 } 1315 1316 static int i801_resume(struct pci_dev *dev) 1317 { 1318 pci_set_power_state(dev, PCI_D0); 1319 pci_restore_state(dev); 1320 return 0; 1321 } 1322 #else 1323 #define i801_suspend NULL 1324 #define i801_resume NULL 1325 #endif 1326 1327 static struct pci_driver i801_driver = { 1328 .name = "i801_smbus", 1329 .id_table = i801_ids, 1330 .probe = i801_probe, 1331 .remove = i801_remove, 1332 .suspend = i801_suspend, 1333 .resume = i801_resume, 1334 }; 1335 1336 static int __init i2c_i801_init(void) 1337 { 1338 if (dmi_name_in_vendors("FUJITSU")) 1339 input_apanel_init(); 1340 return pci_register_driver(&i801_driver); 1341 } 1342 1343 static void __exit i2c_i801_exit(void) 1344 { 1345 pci_unregister_driver(&i801_driver); 1346 } 1347 1348 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>"); 1349 MODULE_DESCRIPTION("I801 SMBus driver"); 1350 MODULE_LICENSE("GPL"); 1351 1352 module_init(i2c_i801_init); 1353 module_exit(i2c_i801_exit); 1354