1 /* 2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, 3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker 4 <mdsxyz123@yahoo.com> 5 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de> 6 Copyright (C) 2010 Intel Corporation, 7 David Woodhouse <dwmw2@infradead.org> 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 2 of the License, or 12 (at your option) any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 */ 19 20 /* 21 * Supports the following Intel I/O Controller Hubs (ICH): 22 * 23 * I/O Block I2C 24 * region SMBus Block proc. block 25 * Chip name PCI ID size PEC buffer call read 26 * --------------------------------------------------------------------------- 27 * 82801AA (ICH) 0x2413 16 no no no no 28 * 82801AB (ICH0) 0x2423 16 no no no no 29 * 82801BA (ICH2) 0x2443 16 no no no no 30 * 82801CA (ICH3) 0x2483 32 soft no no no 31 * 82801DB (ICH4) 0x24c3 32 hard yes no no 32 * 82801E (ICH5) 0x24d3 32 hard yes yes yes 33 * 6300ESB 0x25a4 32 hard yes yes yes 34 * 82801F (ICH6) 0x266a 32 hard yes yes yes 35 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes 36 * 82801G (ICH7) 0x27da 32 hard yes yes yes 37 * 82801H (ICH8) 0x283e 32 hard yes yes yes 38 * 82801I (ICH9) 0x2930 32 hard yes yes yes 39 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes 40 * ICH10 0x3a30 32 hard yes yes yes 41 * ICH10 0x3a60 32 hard yes yes yes 42 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes 43 * 6 Series (PCH) 0x1c22 32 hard yes yes yes 44 * Patsburg (PCH) 0x1d22 32 hard yes yes yes 45 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes 46 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes 47 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes 48 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes 49 * Panther Point (PCH) 0x1e22 32 hard yes yes yes 50 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes 51 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes 52 * Avoton (SOC) 0x1f3c 32 hard yes yes yes 53 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes 54 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes 55 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes 56 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes 57 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes 58 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes 59 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes 60 * BayTrail (SOC) 0x0f12 32 hard yes yes yes 61 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes 62 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes 63 * DNV (SOC) 0x19df 32 hard yes yes yes 64 * Broxton (SOC) 0x5ad4 32 hard yes yes yes 65 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes 66 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes 67 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes 68 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes 69 * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes 70 * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes 71 * 72 * Features supported by this driver: 73 * Software PEC no 74 * Hardware PEC yes 75 * Block buffer yes 76 * Block process call transaction no 77 * I2C block read transaction yes (doesn't use the block buffer) 78 * Slave mode no 79 * SMBus Host Notify yes 80 * Interrupt processing yes 81 * 82 * See the file Documentation/i2c/busses/i2c-i801 for details. 83 */ 84 85 #include <linux/interrupt.h> 86 #include <linux/module.h> 87 #include <linux/pci.h> 88 #include <linux/kernel.h> 89 #include <linux/stddef.h> 90 #include <linux/delay.h> 91 #include <linux/ioport.h> 92 #include <linux/init.h> 93 #include <linux/i2c.h> 94 #include <linux/i2c-smbus.h> 95 #include <linux/acpi.h> 96 #include <linux/io.h> 97 #include <linux/dmi.h> 98 #include <linux/slab.h> 99 #include <linux/wait.h> 100 #include <linux/err.h> 101 #include <linux/platform_device.h> 102 #include <linux/platform_data/itco_wdt.h> 103 #include <linux/pm_runtime.h> 104 105 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 106 #include <linux/gpio.h> 107 #include <linux/i2c-mux-gpio.h> 108 #endif 109 110 /* I801 SMBus address offsets */ 111 #define SMBHSTSTS(p) (0 + (p)->smba) 112 #define SMBHSTCNT(p) (2 + (p)->smba) 113 #define SMBHSTCMD(p) (3 + (p)->smba) 114 #define SMBHSTADD(p) (4 + (p)->smba) 115 #define SMBHSTDAT0(p) (5 + (p)->smba) 116 #define SMBHSTDAT1(p) (6 + (p)->smba) 117 #define SMBBLKDAT(p) (7 + (p)->smba) 118 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */ 119 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */ 120 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */ 121 #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */ 122 #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */ 123 #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */ 124 125 /* PCI Address Constants */ 126 #define SMBBAR 4 127 #define SMBPCICTL 0x004 128 #define SMBPCISTS 0x006 129 #define SMBHSTCFG 0x040 130 #define TCOBASE 0x050 131 #define TCOCTL 0x054 132 133 #define ACPIBASE 0x040 134 #define ACPIBASE_SMI_OFF 0x030 135 #define ACPICTRL 0x044 136 #define ACPICTRL_EN 0x080 137 138 #define SBREG_BAR 0x10 139 #define SBREG_SMBCTRL 0xc6000c 140 141 /* Host status bits for SMBPCISTS */ 142 #define SMBPCISTS_INTS BIT(3) 143 144 /* Control bits for SMBPCICTL */ 145 #define SMBPCICTL_INTDIS BIT(10) 146 147 /* Host configuration bits for SMBHSTCFG */ 148 #define SMBHSTCFG_HST_EN BIT(0) 149 #define SMBHSTCFG_SMB_SMI_EN BIT(1) 150 #define SMBHSTCFG_I2C_EN BIT(2) 151 #define SMBHSTCFG_SPD_WD BIT(4) 152 153 /* TCO configuration bits for TCOCTL */ 154 #define TCOCTL_EN BIT(8) 155 156 /* Auxiliary status register bits, ICH4+ only */ 157 #define SMBAUXSTS_CRCE BIT(0) 158 #define SMBAUXSTS_STCO BIT(1) 159 160 /* Auxiliary control register bits, ICH4+ only */ 161 #define SMBAUXCTL_CRC BIT(0) 162 #define SMBAUXCTL_E32B BIT(1) 163 164 /* Other settings */ 165 #define MAX_RETRIES 400 166 167 /* I801 command constants */ 168 #define I801_QUICK 0x00 169 #define I801_BYTE 0x04 170 #define I801_BYTE_DATA 0x08 171 #define I801_WORD_DATA 0x0C 172 #define I801_PROC_CALL 0x10 /* unimplemented */ 173 #define I801_BLOCK_DATA 0x14 174 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ 175 176 /* I801 Host Control register bits */ 177 #define SMBHSTCNT_INTREN BIT(0) 178 #define SMBHSTCNT_KILL BIT(1) 179 #define SMBHSTCNT_LAST_BYTE BIT(5) 180 #define SMBHSTCNT_START BIT(6) 181 #define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */ 182 183 /* I801 Hosts Status register bits */ 184 #define SMBHSTSTS_BYTE_DONE BIT(7) 185 #define SMBHSTSTS_INUSE_STS BIT(6) 186 #define SMBHSTSTS_SMBALERT_STS BIT(5) 187 #define SMBHSTSTS_FAILED BIT(4) 188 #define SMBHSTSTS_BUS_ERR BIT(3) 189 #define SMBHSTSTS_DEV_ERR BIT(2) 190 #define SMBHSTSTS_INTR BIT(1) 191 #define SMBHSTSTS_HOST_BUSY BIT(0) 192 193 /* Host Notify Status register bits */ 194 #define SMBSLVSTS_HST_NTFY_STS BIT(0) 195 196 /* Host Notify Command register bits */ 197 #define SMBSLVCMD_HST_NTFY_INTREN BIT(0) 198 199 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \ 200 SMBHSTSTS_DEV_ERR) 201 202 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \ 203 STATUS_ERROR_FLAGS) 204 205 /* Older devices have their ID defined in <linux/pci_ids.h> */ 206 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12 207 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df 208 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 209 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 210 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */ 211 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70 212 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71 213 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72 214 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 215 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c 216 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292 217 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 218 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0 219 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4 220 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 221 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4 222 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 223 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2 224 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22 225 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d 226 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e 227 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f 228 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22 229 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2 230 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23 231 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3 232 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123 233 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3 234 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223 235 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3 236 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323 237 238 struct i801_mux_config { 239 char *gpio_chip; 240 unsigned values[3]; 241 int n_values; 242 unsigned classes[3]; 243 unsigned gpios[2]; /* Relative to gpio_chip->base */ 244 int n_gpios; 245 }; 246 247 struct i801_priv { 248 struct i2c_adapter adapter; 249 unsigned long smba; 250 unsigned char original_hstcfg; 251 unsigned char original_slvcmd; 252 struct pci_dev *pci_dev; 253 unsigned int features; 254 255 /* isr processing */ 256 wait_queue_head_t waitq; 257 u8 status; 258 259 /* Command state used by isr for byte-by-byte block transactions */ 260 u8 cmd; 261 bool is_read; 262 int count; 263 int len; 264 u8 *data; 265 266 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 267 const struct i801_mux_config *mux_drvdata; 268 struct platform_device *mux_pdev; 269 #endif 270 struct platform_device *tco_pdev; 271 272 /* 273 * If set to true the host controller registers are reserved for 274 * ACPI AML use. Protected by acpi_lock. 275 */ 276 bool acpi_reserved; 277 struct mutex acpi_lock; 278 }; 279 280 #define FEATURE_SMBUS_PEC BIT(0) 281 #define FEATURE_BLOCK_BUFFER BIT(1) 282 #define FEATURE_BLOCK_PROC BIT(2) 283 #define FEATURE_I2C_BLOCK_READ BIT(3) 284 #define FEATURE_IRQ BIT(4) 285 #define FEATURE_HOST_NOTIFY BIT(5) 286 /* Not really a feature, but it's convenient to handle it as such */ 287 #define FEATURE_IDF BIT(15) 288 #define FEATURE_TCO BIT(16) 289 290 static const char *i801_feature_names[] = { 291 "SMBus PEC", 292 "Block buffer", 293 "Block process call", 294 "I2C block read", 295 "Interrupt", 296 "SMBus Host Notify", 297 }; 298 299 static unsigned int disable_features; 300 module_param(disable_features, uint, S_IRUGO | S_IWUSR); 301 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n" 302 "\t\t 0x01 disable SMBus PEC\n" 303 "\t\t 0x02 disable the block buffer\n" 304 "\t\t 0x08 disable the I2C block read functionality\n" 305 "\t\t 0x10 don't use interrupts\n" 306 "\t\t 0x20 disable SMBus Host Notify "); 307 308 /* Make sure the SMBus host is ready to start transmitting. 309 Return 0 if it is, -EBUSY if it is not. */ 310 static int i801_check_pre(struct i801_priv *priv) 311 { 312 int status; 313 314 status = inb_p(SMBHSTSTS(priv)); 315 if (status & SMBHSTSTS_HOST_BUSY) { 316 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n"); 317 return -EBUSY; 318 } 319 320 status &= STATUS_FLAGS; 321 if (status) { 322 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n", 323 status); 324 outb_p(status, SMBHSTSTS(priv)); 325 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS; 326 if (status) { 327 dev_err(&priv->pci_dev->dev, 328 "Failed clearing status flags (%02x)\n", 329 status); 330 return -EBUSY; 331 } 332 } 333 334 /* 335 * Clear CRC status if needed. 336 * During normal operation, i801_check_post() takes care 337 * of it after every operation. We do it here only in case 338 * the hardware was already in this state when the driver 339 * started. 340 */ 341 if (priv->features & FEATURE_SMBUS_PEC) { 342 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE; 343 if (status) { 344 dev_dbg(&priv->pci_dev->dev, 345 "Clearing aux status flags (%02x)\n", status); 346 outb_p(status, SMBAUXSTS(priv)); 347 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE; 348 if (status) { 349 dev_err(&priv->pci_dev->dev, 350 "Failed clearing aux status flags (%02x)\n", 351 status); 352 return -EBUSY; 353 } 354 } 355 } 356 357 return 0; 358 } 359 360 /* 361 * Convert the status register to an error code, and clear it. 362 * Note that status only contains the bits we want to clear, not the 363 * actual register value. 364 */ 365 static int i801_check_post(struct i801_priv *priv, int status) 366 { 367 int result = 0; 368 369 /* 370 * If the SMBus is still busy, we give up 371 * Note: This timeout condition only happens when using polling 372 * transactions. For interrupt operation, NAK/timeout is indicated by 373 * DEV_ERR. 374 */ 375 if (unlikely(status < 0)) { 376 dev_err(&priv->pci_dev->dev, "Transaction timeout\n"); 377 /* try to stop the current command */ 378 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n"); 379 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL, 380 SMBHSTCNT(priv)); 381 usleep_range(1000, 2000); 382 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL), 383 SMBHSTCNT(priv)); 384 385 /* Check if it worked */ 386 status = inb_p(SMBHSTSTS(priv)); 387 if ((status & SMBHSTSTS_HOST_BUSY) || 388 !(status & SMBHSTSTS_FAILED)) 389 dev_err(&priv->pci_dev->dev, 390 "Failed terminating the transaction\n"); 391 outb_p(STATUS_FLAGS, SMBHSTSTS(priv)); 392 return -ETIMEDOUT; 393 } 394 395 if (status & SMBHSTSTS_FAILED) { 396 result = -EIO; 397 dev_err(&priv->pci_dev->dev, "Transaction failed\n"); 398 } 399 if (status & SMBHSTSTS_DEV_ERR) { 400 /* 401 * This may be a PEC error, check and clear it. 402 * 403 * AUXSTS is handled differently from HSTSTS. 404 * For HSTSTS, i801_isr() or i801_wait_intr() 405 * has already cleared the error bits in hardware, 406 * and we are passed a copy of the original value 407 * in "status". 408 * For AUXSTS, the hardware register is left 409 * for us to handle here. 410 * This is asymmetric, slightly iffy, but safe, 411 * since all this code is serialized and the CRCE 412 * bit is harmless as long as it's cleared before 413 * the next operation. 414 */ 415 if ((priv->features & FEATURE_SMBUS_PEC) && 416 (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) { 417 outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv)); 418 result = -EBADMSG; 419 dev_dbg(&priv->pci_dev->dev, "PEC error\n"); 420 } else { 421 result = -ENXIO; 422 dev_dbg(&priv->pci_dev->dev, "No response\n"); 423 } 424 } 425 if (status & SMBHSTSTS_BUS_ERR) { 426 result = -EAGAIN; 427 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n"); 428 } 429 430 /* Clear status flags except BYTE_DONE, to be cleared by caller */ 431 outb_p(status, SMBHSTSTS(priv)); 432 433 return result; 434 } 435 436 /* Wait for BUSY being cleared and either INTR or an error flag being set */ 437 static int i801_wait_intr(struct i801_priv *priv) 438 { 439 int timeout = 0; 440 int status; 441 442 /* We will always wait for a fraction of a second! */ 443 do { 444 usleep_range(250, 500); 445 status = inb_p(SMBHSTSTS(priv)); 446 } while (((status & SMBHSTSTS_HOST_BUSY) || 447 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) && 448 (timeout++ < MAX_RETRIES)); 449 450 if (timeout > MAX_RETRIES) { 451 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n"); 452 return -ETIMEDOUT; 453 } 454 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR); 455 } 456 457 /* Wait for either BYTE_DONE or an error flag being set */ 458 static int i801_wait_byte_done(struct i801_priv *priv) 459 { 460 int timeout = 0; 461 int status; 462 463 /* We will always wait for a fraction of a second! */ 464 do { 465 usleep_range(250, 500); 466 status = inb_p(SMBHSTSTS(priv)); 467 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) && 468 (timeout++ < MAX_RETRIES)); 469 470 if (timeout > MAX_RETRIES) { 471 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n"); 472 return -ETIMEDOUT; 473 } 474 return status & STATUS_ERROR_FLAGS; 475 } 476 477 static int i801_transaction(struct i801_priv *priv, int xact) 478 { 479 int status; 480 int result; 481 const struct i2c_adapter *adap = &priv->adapter; 482 483 result = i801_check_pre(priv); 484 if (result < 0) 485 return result; 486 487 if (priv->features & FEATURE_IRQ) { 488 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START, 489 SMBHSTCNT(priv)); 490 result = wait_event_timeout(priv->waitq, 491 (status = priv->status), 492 adap->timeout); 493 if (!result) { 494 status = -ETIMEDOUT; 495 dev_warn(&priv->pci_dev->dev, 496 "Timeout waiting for interrupt!\n"); 497 } 498 priv->status = 0; 499 return i801_check_post(priv, status); 500 } 501 502 /* the current contents of SMBHSTCNT can be overwritten, since PEC, 503 * SMBSCMD are passed in xact */ 504 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv)); 505 506 status = i801_wait_intr(priv); 507 return i801_check_post(priv, status); 508 } 509 510 static int i801_block_transaction_by_block(struct i801_priv *priv, 511 union i2c_smbus_data *data, 512 char read_write, int hwpec) 513 { 514 int i, len; 515 int status; 516 517 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ 518 519 /* Use 32-byte buffer to process this transaction */ 520 if (read_write == I2C_SMBUS_WRITE) { 521 len = data->block[0]; 522 outb_p(len, SMBHSTDAT0(priv)); 523 for (i = 0; i < len; i++) 524 outb_p(data->block[i+1], SMBBLKDAT(priv)); 525 } 526 527 status = i801_transaction(priv, I801_BLOCK_DATA | 528 (hwpec ? SMBHSTCNT_PEC_EN : 0)); 529 if (status) 530 return status; 531 532 if (read_write == I2C_SMBUS_READ) { 533 len = inb_p(SMBHSTDAT0(priv)); 534 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) 535 return -EPROTO; 536 537 data->block[0] = len; 538 for (i = 0; i < len; i++) 539 data->block[i + 1] = inb_p(SMBBLKDAT(priv)); 540 } 541 return 0; 542 } 543 544 static void i801_isr_byte_done(struct i801_priv *priv) 545 { 546 if (priv->is_read) { 547 /* For SMBus block reads, length is received with first byte */ 548 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) && 549 (priv->count == 0)) { 550 priv->len = inb_p(SMBHSTDAT0(priv)); 551 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) { 552 dev_err(&priv->pci_dev->dev, 553 "Illegal SMBus block read size %d\n", 554 priv->len); 555 /* FIXME: Recover */ 556 priv->len = I2C_SMBUS_BLOCK_MAX; 557 } else { 558 dev_dbg(&priv->pci_dev->dev, 559 "SMBus block read size is %d\n", 560 priv->len); 561 } 562 priv->data[-1] = priv->len; 563 } 564 565 /* Read next byte */ 566 if (priv->count < priv->len) 567 priv->data[priv->count++] = inb(SMBBLKDAT(priv)); 568 else 569 dev_dbg(&priv->pci_dev->dev, 570 "Discarding extra byte on block read\n"); 571 572 /* Set LAST_BYTE for last byte of read transaction */ 573 if (priv->count == priv->len - 1) 574 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE, 575 SMBHSTCNT(priv)); 576 } else if (priv->count < priv->len - 1) { 577 /* Write next byte, except for IRQ after last byte */ 578 outb_p(priv->data[++priv->count], SMBBLKDAT(priv)); 579 } 580 581 /* Clear BYTE_DONE to continue with next byte */ 582 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 583 } 584 585 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv) 586 { 587 unsigned short addr; 588 589 addr = inb_p(SMBNTFDADD(priv)) >> 1; 590 591 /* 592 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba) 593 * always returns 0. Our current implementation doesn't provide 594 * data, so we just ignore it. 595 */ 596 i2c_handle_smbus_host_notify(&priv->adapter, addr); 597 598 /* clear Host Notify bit and return */ 599 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 600 return IRQ_HANDLED; 601 } 602 603 /* 604 * There are three kinds of interrupts: 605 * 606 * 1) i801 signals transaction completion with one of these interrupts: 607 * INTR - Success 608 * DEV_ERR - Invalid command, NAK or communication timeout 609 * BUS_ERR - SMI# transaction collision 610 * FAILED - transaction was canceled due to a KILL request 611 * When any of these occur, update ->status and wake up the waitq. 612 * ->status must be cleared before kicking off the next transaction. 613 * 614 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt 615 * occurs for each byte of a byte-by-byte to prepare the next byte. 616 * 617 * 3) Host Notify interrupts 618 */ 619 static irqreturn_t i801_isr(int irq, void *dev_id) 620 { 621 struct i801_priv *priv = dev_id; 622 u16 pcists; 623 u8 status; 624 625 /* Confirm this is our interrupt */ 626 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); 627 if (!(pcists & SMBPCISTS_INTS)) 628 return IRQ_NONE; 629 630 if (priv->features & FEATURE_HOST_NOTIFY) { 631 status = inb_p(SMBSLVSTS(priv)); 632 if (status & SMBSLVSTS_HST_NTFY_STS) 633 return i801_host_notify_isr(priv); 634 } 635 636 status = inb_p(SMBHSTSTS(priv)); 637 if (status & SMBHSTSTS_BYTE_DONE) 638 i801_isr_byte_done(priv); 639 640 /* 641 * Clear irq sources and report transaction result. 642 * ->status must be cleared before the next transaction is started. 643 */ 644 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS; 645 if (status) { 646 outb_p(status, SMBHSTSTS(priv)); 647 priv->status = status; 648 wake_up(&priv->waitq); 649 } 650 651 return IRQ_HANDLED; 652 } 653 654 /* 655 * For "byte-by-byte" block transactions: 656 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1 657 * I2C read uses cmd=I801_I2C_BLOCK_DATA 658 */ 659 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, 660 union i2c_smbus_data *data, 661 char read_write, int command, 662 int hwpec) 663 { 664 int i, len; 665 int smbcmd; 666 int status; 667 int result; 668 const struct i2c_adapter *adap = &priv->adapter; 669 670 result = i801_check_pre(priv); 671 if (result < 0) 672 return result; 673 674 len = data->block[0]; 675 676 if (read_write == I2C_SMBUS_WRITE) { 677 outb_p(len, SMBHSTDAT0(priv)); 678 outb_p(data->block[1], SMBBLKDAT(priv)); 679 } 680 681 if (command == I2C_SMBUS_I2C_BLOCK_DATA && 682 read_write == I2C_SMBUS_READ) 683 smbcmd = I801_I2C_BLOCK_DATA; 684 else 685 smbcmd = I801_BLOCK_DATA; 686 687 if (priv->features & FEATURE_IRQ) { 688 priv->is_read = (read_write == I2C_SMBUS_READ); 689 if (len == 1 && priv->is_read) 690 smbcmd |= SMBHSTCNT_LAST_BYTE; 691 priv->cmd = smbcmd | SMBHSTCNT_INTREN; 692 priv->len = len; 693 priv->count = 0; 694 priv->data = &data->block[1]; 695 696 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv)); 697 result = wait_event_timeout(priv->waitq, 698 (status = priv->status), 699 adap->timeout); 700 if (!result) { 701 status = -ETIMEDOUT; 702 dev_warn(&priv->pci_dev->dev, 703 "Timeout waiting for interrupt!\n"); 704 } 705 priv->status = 0; 706 return i801_check_post(priv, status); 707 } 708 709 for (i = 1; i <= len; i++) { 710 if (i == len && read_write == I2C_SMBUS_READ) 711 smbcmd |= SMBHSTCNT_LAST_BYTE; 712 outb_p(smbcmd, SMBHSTCNT(priv)); 713 714 if (i == 1) 715 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START, 716 SMBHSTCNT(priv)); 717 718 status = i801_wait_byte_done(priv); 719 if (status) 720 goto exit; 721 722 if (i == 1 && read_write == I2C_SMBUS_READ 723 && command != I2C_SMBUS_I2C_BLOCK_DATA) { 724 len = inb_p(SMBHSTDAT0(priv)); 725 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { 726 dev_err(&priv->pci_dev->dev, 727 "Illegal SMBus block read size %d\n", 728 len); 729 /* Recover */ 730 while (inb_p(SMBHSTSTS(priv)) & 731 SMBHSTSTS_HOST_BUSY) 732 outb_p(SMBHSTSTS_BYTE_DONE, 733 SMBHSTSTS(priv)); 734 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); 735 return -EPROTO; 736 } 737 data->block[0] = len; 738 } 739 740 /* Retrieve/store value in SMBBLKDAT */ 741 if (read_write == I2C_SMBUS_READ) 742 data->block[i] = inb_p(SMBBLKDAT(priv)); 743 if (read_write == I2C_SMBUS_WRITE && i+1 <= len) 744 outb_p(data->block[i+1], SMBBLKDAT(priv)); 745 746 /* signals SMBBLKDAT ready */ 747 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 748 } 749 750 status = i801_wait_intr(priv); 751 exit: 752 return i801_check_post(priv, status); 753 } 754 755 static int i801_set_block_buffer_mode(struct i801_priv *priv) 756 { 757 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv)); 758 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0) 759 return -EIO; 760 return 0; 761 } 762 763 /* Block transaction function */ 764 static int i801_block_transaction(struct i801_priv *priv, 765 union i2c_smbus_data *data, char read_write, 766 int command, int hwpec) 767 { 768 int result = 0; 769 unsigned char hostc; 770 771 if (command == I2C_SMBUS_I2C_BLOCK_DATA) { 772 if (read_write == I2C_SMBUS_WRITE) { 773 /* set I2C_EN bit in configuration register */ 774 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc); 775 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, 776 hostc | SMBHSTCFG_I2C_EN); 777 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) { 778 dev_err(&priv->pci_dev->dev, 779 "I2C block read is unsupported!\n"); 780 return -EOPNOTSUPP; 781 } 782 } 783 784 if (read_write == I2C_SMBUS_WRITE 785 || command == I2C_SMBUS_I2C_BLOCK_DATA) { 786 if (data->block[0] < 1) 787 data->block[0] = 1; 788 if (data->block[0] > I2C_SMBUS_BLOCK_MAX) 789 data->block[0] = I2C_SMBUS_BLOCK_MAX; 790 } else { 791 data->block[0] = 32; /* max for SMBus block reads */ 792 } 793 794 /* Experience has shown that the block buffer can only be used for 795 SMBus (not I2C) block transactions, even though the datasheet 796 doesn't mention this limitation. */ 797 if ((priv->features & FEATURE_BLOCK_BUFFER) 798 && command != I2C_SMBUS_I2C_BLOCK_DATA 799 && i801_set_block_buffer_mode(priv) == 0) 800 result = i801_block_transaction_by_block(priv, data, 801 read_write, hwpec); 802 else 803 result = i801_block_transaction_byte_by_byte(priv, data, 804 read_write, 805 command, hwpec); 806 807 if (command == I2C_SMBUS_I2C_BLOCK_DATA 808 && read_write == I2C_SMBUS_WRITE) { 809 /* restore saved configuration register value */ 810 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc); 811 } 812 return result; 813 } 814 815 /* Return negative errno on error. */ 816 static s32 i801_access(struct i2c_adapter *adap, u16 addr, 817 unsigned short flags, char read_write, u8 command, 818 int size, union i2c_smbus_data *data) 819 { 820 int hwpec; 821 int block = 0; 822 int ret = 0, xact = 0; 823 struct i801_priv *priv = i2c_get_adapdata(adap); 824 825 mutex_lock(&priv->acpi_lock); 826 if (priv->acpi_reserved) { 827 mutex_unlock(&priv->acpi_lock); 828 return -EBUSY; 829 } 830 831 pm_runtime_get_sync(&priv->pci_dev->dev); 832 833 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) 834 && size != I2C_SMBUS_QUICK 835 && size != I2C_SMBUS_I2C_BLOCK_DATA; 836 837 switch (size) { 838 case I2C_SMBUS_QUICK: 839 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 840 SMBHSTADD(priv)); 841 xact = I801_QUICK; 842 break; 843 case I2C_SMBUS_BYTE: 844 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 845 SMBHSTADD(priv)); 846 if (read_write == I2C_SMBUS_WRITE) 847 outb_p(command, SMBHSTCMD(priv)); 848 xact = I801_BYTE; 849 break; 850 case I2C_SMBUS_BYTE_DATA: 851 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 852 SMBHSTADD(priv)); 853 outb_p(command, SMBHSTCMD(priv)); 854 if (read_write == I2C_SMBUS_WRITE) 855 outb_p(data->byte, SMBHSTDAT0(priv)); 856 xact = I801_BYTE_DATA; 857 break; 858 case I2C_SMBUS_WORD_DATA: 859 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 860 SMBHSTADD(priv)); 861 outb_p(command, SMBHSTCMD(priv)); 862 if (read_write == I2C_SMBUS_WRITE) { 863 outb_p(data->word & 0xff, SMBHSTDAT0(priv)); 864 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); 865 } 866 xact = I801_WORD_DATA; 867 break; 868 case I2C_SMBUS_BLOCK_DATA: 869 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 870 SMBHSTADD(priv)); 871 outb_p(command, SMBHSTCMD(priv)); 872 block = 1; 873 break; 874 case I2C_SMBUS_I2C_BLOCK_DATA: 875 /* 876 * NB: page 240 of ICH5 datasheet shows that the R/#W 877 * bit should be cleared here, even when reading. 878 * However if SPD Write Disable is set (Lynx Point and later), 879 * the read will fail if we don't set the R/#W bit. 880 */ 881 outb_p(((addr & 0x7f) << 1) | 882 ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ? 883 (read_write & 0x01) : 0), 884 SMBHSTADD(priv)); 885 if (read_write == I2C_SMBUS_READ) { 886 /* NB: page 240 of ICH5 datasheet also shows 887 * that DATA1 is the cmd field when reading */ 888 outb_p(command, SMBHSTDAT1(priv)); 889 } else 890 outb_p(command, SMBHSTCMD(priv)); 891 block = 1; 892 break; 893 default: 894 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n", 895 size); 896 ret = -EOPNOTSUPP; 897 goto out; 898 } 899 900 if (hwpec) /* enable/disable hardware PEC */ 901 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv)); 902 else 903 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC), 904 SMBAUXCTL(priv)); 905 906 if (block) 907 ret = i801_block_transaction(priv, data, read_write, size, 908 hwpec); 909 else 910 ret = i801_transaction(priv, xact); 911 912 /* Some BIOSes don't like it when PEC is enabled at reboot or resume 913 time, so we forcibly disable it after every transaction. Turn off 914 E32B for the same reason. */ 915 if (hwpec || block) 916 outb_p(inb_p(SMBAUXCTL(priv)) & 917 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 918 919 if (block) 920 goto out; 921 if (ret) 922 goto out; 923 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK)) 924 goto out; 925 926 switch (xact & 0x7f) { 927 case I801_BYTE: /* Result put in SMBHSTDAT0 */ 928 case I801_BYTE_DATA: 929 data->byte = inb_p(SMBHSTDAT0(priv)); 930 break; 931 case I801_WORD_DATA: 932 data->word = inb_p(SMBHSTDAT0(priv)) + 933 (inb_p(SMBHSTDAT1(priv)) << 8); 934 break; 935 } 936 937 out: 938 pm_runtime_mark_last_busy(&priv->pci_dev->dev); 939 pm_runtime_put_autosuspend(&priv->pci_dev->dev); 940 mutex_unlock(&priv->acpi_lock); 941 return ret; 942 } 943 944 945 static u32 i801_func(struct i2c_adapter *adapter) 946 { 947 struct i801_priv *priv = i2c_get_adapdata(adapter); 948 949 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 950 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 951 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | 952 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | 953 ((priv->features & FEATURE_I2C_BLOCK_READ) ? 954 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) | 955 ((priv->features & FEATURE_HOST_NOTIFY) ? 956 I2C_FUNC_SMBUS_HOST_NOTIFY : 0); 957 } 958 959 static void i801_enable_host_notify(struct i2c_adapter *adapter) 960 { 961 struct i801_priv *priv = i2c_get_adapdata(adapter); 962 963 if (!(priv->features & FEATURE_HOST_NOTIFY)) 964 return; 965 966 priv->original_slvcmd = inb_p(SMBSLVCMD(priv)); 967 968 if (!(SMBSLVCMD_HST_NTFY_INTREN & priv->original_slvcmd)) 969 outb_p(SMBSLVCMD_HST_NTFY_INTREN | priv->original_slvcmd, 970 SMBSLVCMD(priv)); 971 972 /* clear Host Notify bit to allow a new notification */ 973 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 974 } 975 976 static void i801_disable_host_notify(struct i801_priv *priv) 977 { 978 if (!(priv->features & FEATURE_HOST_NOTIFY)) 979 return; 980 981 outb_p(priv->original_slvcmd, SMBSLVCMD(priv)); 982 } 983 984 static const struct i2c_algorithm smbus_algorithm = { 985 .smbus_xfer = i801_access, 986 .functionality = i801_func, 987 }; 988 989 static const struct pci_device_id i801_ids[] = { 990 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) }, 991 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) }, 992 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) }, 993 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) }, 994 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) }, 995 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) }, 996 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) }, 997 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) }, 998 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) }, 999 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) }, 1000 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) }, 1001 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) }, 1002 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) }, 1003 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) }, 1004 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) }, 1005 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) }, 1006 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) }, 1007 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) }, 1008 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) }, 1009 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) }, 1010 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) }, 1011 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) }, 1012 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) }, 1013 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) }, 1014 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) }, 1015 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) }, 1016 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) }, 1017 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) }, 1018 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) }, 1019 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) }, 1020 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) }, 1021 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS) }, 1022 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) }, 1023 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) }, 1024 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) }, 1025 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) }, 1026 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) }, 1027 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) }, 1028 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) }, 1029 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) }, 1030 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) }, 1031 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) }, 1032 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) }, 1033 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS) }, 1034 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS) }, 1035 { 0, } 1036 }; 1037 1038 MODULE_DEVICE_TABLE(pci, i801_ids); 1039 1040 #if defined CONFIG_X86 && defined CONFIG_DMI 1041 static unsigned char apanel_addr; 1042 1043 /* Scan the system ROM for the signature "FJKEYINF" */ 1044 static __init const void __iomem *bios_signature(const void __iomem *bios) 1045 { 1046 ssize_t offset; 1047 const unsigned char signature[] = "FJKEYINF"; 1048 1049 for (offset = 0; offset < 0x10000; offset += 0x10) { 1050 if (check_signature(bios + offset, signature, 1051 sizeof(signature)-1)) 1052 return bios + offset; 1053 } 1054 return NULL; 1055 } 1056 1057 static void __init input_apanel_init(void) 1058 { 1059 void __iomem *bios; 1060 const void __iomem *p; 1061 1062 bios = ioremap(0xF0000, 0x10000); /* Can't fail */ 1063 p = bios_signature(bios); 1064 if (p) { 1065 /* just use the first address */ 1066 apanel_addr = readb(p + 8 + 3) >> 1; 1067 } 1068 iounmap(bios); 1069 } 1070 1071 struct dmi_onboard_device_info { 1072 const char *name; 1073 u8 type; 1074 unsigned short i2c_addr; 1075 const char *i2c_type; 1076 }; 1077 1078 static const struct dmi_onboard_device_info dmi_devices[] = { 1079 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" }, 1080 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" }, 1081 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" }, 1082 }; 1083 1084 static void dmi_check_onboard_device(u8 type, const char *name, 1085 struct i2c_adapter *adap) 1086 { 1087 int i; 1088 struct i2c_board_info info; 1089 1090 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) { 1091 /* & ~0x80, ignore enabled/disabled bit */ 1092 if ((type & ~0x80) != dmi_devices[i].type) 1093 continue; 1094 if (strcasecmp(name, dmi_devices[i].name)) 1095 continue; 1096 1097 memset(&info, 0, sizeof(struct i2c_board_info)); 1098 info.addr = dmi_devices[i].i2c_addr; 1099 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); 1100 i2c_new_device(adap, &info); 1101 break; 1102 } 1103 } 1104 1105 /* We use our own function to check for onboard devices instead of 1106 dmi_find_device() as some buggy BIOS's have the devices we are interested 1107 in marked as disabled */ 1108 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap) 1109 { 1110 int i, count; 1111 1112 if (dm->type != 10) 1113 return; 1114 1115 count = (dm->length - sizeof(struct dmi_header)) / 2; 1116 for (i = 0; i < count; i++) { 1117 const u8 *d = (char *)(dm + 1) + (i * 2); 1118 const char *name = ((char *) dm) + dm->length; 1119 u8 type = d[0]; 1120 u8 s = d[1]; 1121 1122 if (!s) 1123 continue; 1124 s--; 1125 while (s > 0 && name[0]) { 1126 name += strlen(name) + 1; 1127 s--; 1128 } 1129 if (name[0] == 0) /* Bogus string reference */ 1130 continue; 1131 1132 dmi_check_onboard_device(type, name, adap); 1133 } 1134 } 1135 1136 /* Register optional slaves */ 1137 static void i801_probe_optional_slaves(struct i801_priv *priv) 1138 { 1139 /* Only register slaves on main SMBus channel */ 1140 if (priv->features & FEATURE_IDF) 1141 return; 1142 1143 if (apanel_addr) { 1144 struct i2c_board_info info; 1145 1146 memset(&info, 0, sizeof(struct i2c_board_info)); 1147 info.addr = apanel_addr; 1148 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE); 1149 i2c_new_device(&priv->adapter, &info); 1150 } 1151 1152 if (dmi_name_in_vendors("FUJITSU")) 1153 dmi_walk(dmi_check_onboard_devices, &priv->adapter); 1154 } 1155 #else 1156 static void __init input_apanel_init(void) {} 1157 static void i801_probe_optional_slaves(struct i801_priv *priv) {} 1158 #endif /* CONFIG_X86 && CONFIG_DMI */ 1159 1160 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 1161 static struct i801_mux_config i801_mux_config_asus_z8_d12 = { 1162 .gpio_chip = "gpio_ich", 1163 .values = { 0x02, 0x03 }, 1164 .n_values = 2, 1165 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD }, 1166 .gpios = { 52, 53 }, 1167 .n_gpios = 2, 1168 }; 1169 1170 static struct i801_mux_config i801_mux_config_asus_z8_d18 = { 1171 .gpio_chip = "gpio_ich", 1172 .values = { 0x02, 0x03, 0x01 }, 1173 .n_values = 3, 1174 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD }, 1175 .gpios = { 52, 53 }, 1176 .n_gpios = 2, 1177 }; 1178 1179 static const struct dmi_system_id mux_dmi_table[] = { 1180 { 1181 .matches = { 1182 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1183 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"), 1184 }, 1185 .driver_data = &i801_mux_config_asus_z8_d12, 1186 }, 1187 { 1188 .matches = { 1189 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1190 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"), 1191 }, 1192 .driver_data = &i801_mux_config_asus_z8_d12, 1193 }, 1194 { 1195 .matches = { 1196 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1197 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"), 1198 }, 1199 .driver_data = &i801_mux_config_asus_z8_d12, 1200 }, 1201 { 1202 .matches = { 1203 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1204 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"), 1205 }, 1206 .driver_data = &i801_mux_config_asus_z8_d12, 1207 }, 1208 { 1209 .matches = { 1210 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1211 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"), 1212 }, 1213 .driver_data = &i801_mux_config_asus_z8_d12, 1214 }, 1215 { 1216 .matches = { 1217 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1218 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"), 1219 }, 1220 .driver_data = &i801_mux_config_asus_z8_d12, 1221 }, 1222 { 1223 .matches = { 1224 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1225 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"), 1226 }, 1227 .driver_data = &i801_mux_config_asus_z8_d18, 1228 }, 1229 { 1230 .matches = { 1231 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1232 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"), 1233 }, 1234 .driver_data = &i801_mux_config_asus_z8_d18, 1235 }, 1236 { 1237 .matches = { 1238 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1239 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"), 1240 }, 1241 .driver_data = &i801_mux_config_asus_z8_d12, 1242 }, 1243 { } 1244 }; 1245 1246 /* Setup multiplexing if needed */ 1247 static int i801_add_mux(struct i801_priv *priv) 1248 { 1249 struct device *dev = &priv->adapter.dev; 1250 const struct i801_mux_config *mux_config; 1251 struct i2c_mux_gpio_platform_data gpio_data; 1252 int err; 1253 1254 if (!priv->mux_drvdata) 1255 return 0; 1256 mux_config = priv->mux_drvdata; 1257 1258 /* Prepare the platform data */ 1259 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data)); 1260 gpio_data.parent = priv->adapter.nr; 1261 gpio_data.values = mux_config->values; 1262 gpio_data.n_values = mux_config->n_values; 1263 gpio_data.classes = mux_config->classes; 1264 gpio_data.gpio_chip = mux_config->gpio_chip; 1265 gpio_data.gpios = mux_config->gpios; 1266 gpio_data.n_gpios = mux_config->n_gpios; 1267 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE; 1268 1269 /* Register the mux device */ 1270 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio", 1271 PLATFORM_DEVID_AUTO, &gpio_data, 1272 sizeof(struct i2c_mux_gpio_platform_data)); 1273 if (IS_ERR(priv->mux_pdev)) { 1274 err = PTR_ERR(priv->mux_pdev); 1275 priv->mux_pdev = NULL; 1276 dev_err(dev, "Failed to register i2c-mux-gpio device\n"); 1277 return err; 1278 } 1279 1280 return 0; 1281 } 1282 1283 static void i801_del_mux(struct i801_priv *priv) 1284 { 1285 if (priv->mux_pdev) 1286 platform_device_unregister(priv->mux_pdev); 1287 } 1288 1289 static unsigned int i801_get_adapter_class(struct i801_priv *priv) 1290 { 1291 const struct dmi_system_id *id; 1292 const struct i801_mux_config *mux_config; 1293 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 1294 int i; 1295 1296 id = dmi_first_match(mux_dmi_table); 1297 if (id) { 1298 /* Remove branch classes from trunk */ 1299 mux_config = id->driver_data; 1300 for (i = 0; i < mux_config->n_values; i++) 1301 class &= ~mux_config->classes[i]; 1302 1303 /* Remember for later */ 1304 priv->mux_drvdata = mux_config; 1305 } 1306 1307 return class; 1308 } 1309 #else 1310 static inline int i801_add_mux(struct i801_priv *priv) { return 0; } 1311 static inline void i801_del_mux(struct i801_priv *priv) { } 1312 1313 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv) 1314 { 1315 return I2C_CLASS_HWMON | I2C_CLASS_SPD; 1316 } 1317 #endif 1318 1319 static const struct itco_wdt_platform_data tco_platform_data = { 1320 .name = "Intel PCH", 1321 .version = 4, 1322 }; 1323 1324 static DEFINE_SPINLOCK(p2sb_spinlock); 1325 1326 static void i801_add_tco(struct i801_priv *priv) 1327 { 1328 struct pci_dev *pci_dev = priv->pci_dev; 1329 struct resource tco_res[3], *res; 1330 struct platform_device *pdev; 1331 unsigned int devfn; 1332 u32 tco_base, tco_ctl; 1333 u32 base_addr, ctrl_val; 1334 u64 base64_addr; 1335 u8 hidden; 1336 1337 if (!(priv->features & FEATURE_TCO)) 1338 return; 1339 1340 pci_read_config_dword(pci_dev, TCOBASE, &tco_base); 1341 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl); 1342 if (!(tco_ctl & TCOCTL_EN)) 1343 return; 1344 1345 memset(tco_res, 0, sizeof(tco_res)); 1346 1347 res = &tco_res[ICH_RES_IO_TCO]; 1348 res->start = tco_base & ~1; 1349 res->end = res->start + 32 - 1; 1350 res->flags = IORESOURCE_IO; 1351 1352 /* 1353 * Power Management registers. 1354 */ 1355 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 2); 1356 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPIBASE, &base_addr); 1357 1358 res = &tco_res[ICH_RES_IO_SMI]; 1359 res->start = (base_addr & ~1) + ACPIBASE_SMI_OFF; 1360 res->end = res->start + 3; 1361 res->flags = IORESOURCE_IO; 1362 1363 /* 1364 * Enable the ACPI I/O space. 1365 */ 1366 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPICTRL, &ctrl_val); 1367 ctrl_val |= ACPICTRL_EN; 1368 pci_bus_write_config_dword(pci_dev->bus, devfn, ACPICTRL, ctrl_val); 1369 1370 /* 1371 * We must access the NO_REBOOT bit over the Primary to Sideband 1372 * bridge (P2SB). The BIOS prevents the P2SB device from being 1373 * enumerated by the PCI subsystem, so we need to unhide/hide it 1374 * to lookup the P2SB BAR. 1375 */ 1376 spin_lock(&p2sb_spinlock); 1377 1378 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1); 1379 1380 /* Unhide the P2SB device, if it is hidden */ 1381 pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden); 1382 if (hidden) 1383 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0); 1384 1385 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr); 1386 base64_addr = base_addr & 0xfffffff0; 1387 1388 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr); 1389 base64_addr |= (u64)base_addr << 32; 1390 1391 /* Hide the P2SB device, if it was hidden before */ 1392 if (hidden) 1393 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden); 1394 spin_unlock(&p2sb_spinlock); 1395 1396 res = &tco_res[ICH_RES_MEM_OFF]; 1397 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL; 1398 res->end = res->start + 3; 1399 res->flags = IORESOURCE_MEM; 1400 1401 pdev = platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1, 1402 tco_res, 3, &tco_platform_data, 1403 sizeof(tco_platform_data)); 1404 if (IS_ERR(pdev)) { 1405 dev_warn(&pci_dev->dev, "failed to create iTCO device\n"); 1406 return; 1407 } 1408 1409 priv->tco_pdev = pdev; 1410 } 1411 1412 #ifdef CONFIG_ACPI 1413 static acpi_status 1414 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits, 1415 u64 *value, void *handler_context, void *region_context) 1416 { 1417 struct i801_priv *priv = handler_context; 1418 struct pci_dev *pdev = priv->pci_dev; 1419 acpi_status status; 1420 1421 /* 1422 * Once BIOS AML code touches the OpRegion we warn and inhibit any 1423 * further access from the driver itself. This device is now owned 1424 * by the system firmware. 1425 */ 1426 mutex_lock(&priv->acpi_lock); 1427 1428 if (!priv->acpi_reserved) { 1429 priv->acpi_reserved = true; 1430 1431 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n"); 1432 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n"); 1433 1434 /* 1435 * BIOS is accessing the host controller so prevent it from 1436 * suspending automatically from now on. 1437 */ 1438 pm_runtime_get_sync(&pdev->dev); 1439 } 1440 1441 if ((function & ACPI_IO_MASK) == ACPI_READ) 1442 status = acpi_os_read_port(address, (u32 *)value, bits); 1443 else 1444 status = acpi_os_write_port(address, (u32)*value, bits); 1445 1446 mutex_unlock(&priv->acpi_lock); 1447 1448 return status; 1449 } 1450 1451 static int i801_acpi_probe(struct i801_priv *priv) 1452 { 1453 struct acpi_device *adev; 1454 acpi_status status; 1455 1456 adev = ACPI_COMPANION(&priv->pci_dev->dev); 1457 if (adev) { 1458 status = acpi_install_address_space_handler(adev->handle, 1459 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler, 1460 NULL, priv); 1461 if (ACPI_SUCCESS(status)) 1462 return 0; 1463 } 1464 1465 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]); 1466 } 1467 1468 static void i801_acpi_remove(struct i801_priv *priv) 1469 { 1470 struct acpi_device *adev; 1471 1472 adev = ACPI_COMPANION(&priv->pci_dev->dev); 1473 if (!adev) 1474 return; 1475 1476 acpi_remove_address_space_handler(adev->handle, 1477 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler); 1478 1479 mutex_lock(&priv->acpi_lock); 1480 if (priv->acpi_reserved) 1481 pm_runtime_put(&priv->pci_dev->dev); 1482 mutex_unlock(&priv->acpi_lock); 1483 } 1484 #else 1485 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; } 1486 static inline void i801_acpi_remove(struct i801_priv *priv) { } 1487 #endif 1488 1489 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id) 1490 { 1491 unsigned char temp; 1492 int err, i; 1493 struct i801_priv *priv; 1494 1495 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL); 1496 if (!priv) 1497 return -ENOMEM; 1498 1499 i2c_set_adapdata(&priv->adapter, priv); 1500 priv->adapter.owner = THIS_MODULE; 1501 priv->adapter.class = i801_get_adapter_class(priv); 1502 priv->adapter.algo = &smbus_algorithm; 1503 priv->adapter.dev.parent = &dev->dev; 1504 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev)); 1505 priv->adapter.retries = 3; 1506 mutex_init(&priv->acpi_lock); 1507 1508 priv->pci_dev = dev; 1509 switch (dev->device) { 1510 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS: 1511 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS: 1512 case PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS: 1513 case PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS: 1514 case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS: 1515 case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS: 1516 case PCI_DEVICE_ID_INTEL_DNV_SMBUS: 1517 case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS: 1518 priv->features |= FEATURE_I2C_BLOCK_READ; 1519 priv->features |= FEATURE_IRQ; 1520 priv->features |= FEATURE_SMBUS_PEC; 1521 priv->features |= FEATURE_BLOCK_BUFFER; 1522 /* If we have ACPI based watchdog use that instead */ 1523 if (!acpi_has_watchdog()) 1524 priv->features |= FEATURE_TCO; 1525 priv->features |= FEATURE_HOST_NOTIFY; 1526 break; 1527 1528 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0: 1529 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1: 1530 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2: 1531 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0: 1532 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1: 1533 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2: 1534 priv->features |= FEATURE_IDF; 1535 /* fall through */ 1536 default: 1537 priv->features |= FEATURE_I2C_BLOCK_READ; 1538 priv->features |= FEATURE_IRQ; 1539 /* fall through */ 1540 case PCI_DEVICE_ID_INTEL_82801DB_3: 1541 priv->features |= FEATURE_SMBUS_PEC; 1542 priv->features |= FEATURE_BLOCK_BUFFER; 1543 /* fall through */ 1544 case PCI_DEVICE_ID_INTEL_82801CA_3: 1545 priv->features |= FEATURE_HOST_NOTIFY; 1546 /* fall through */ 1547 case PCI_DEVICE_ID_INTEL_82801BA_2: 1548 case PCI_DEVICE_ID_INTEL_82801AB_3: 1549 case PCI_DEVICE_ID_INTEL_82801AA_3: 1550 break; 1551 } 1552 1553 /* Disable features on user request */ 1554 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) { 1555 if (priv->features & disable_features & (1 << i)) 1556 dev_notice(&dev->dev, "%s disabled by user\n", 1557 i801_feature_names[i]); 1558 } 1559 priv->features &= ~disable_features; 1560 1561 err = pcim_enable_device(dev); 1562 if (err) { 1563 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", 1564 err); 1565 return err; 1566 } 1567 pcim_pin_device(dev); 1568 1569 /* Determine the address of the SMBus area */ 1570 priv->smba = pci_resource_start(dev, SMBBAR); 1571 if (!priv->smba) { 1572 dev_err(&dev->dev, 1573 "SMBus base address uninitialized, upgrade BIOS\n"); 1574 return -ENODEV; 1575 } 1576 1577 if (i801_acpi_probe(priv)) 1578 return -ENODEV; 1579 1580 err = pcim_iomap_regions(dev, 1 << SMBBAR, 1581 dev_driver_string(&dev->dev)); 1582 if (err) { 1583 dev_err(&dev->dev, 1584 "Failed to request SMBus region 0x%lx-0x%Lx\n", 1585 priv->smba, 1586 (unsigned long long)pci_resource_end(dev, SMBBAR)); 1587 i801_acpi_remove(priv); 1588 return err; 1589 } 1590 1591 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp); 1592 priv->original_hstcfg = temp; 1593 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ 1594 if (!(temp & SMBHSTCFG_HST_EN)) { 1595 dev_info(&dev->dev, "Enabling SMBus device\n"); 1596 temp |= SMBHSTCFG_HST_EN; 1597 } 1598 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp); 1599 1600 if (temp & SMBHSTCFG_SMB_SMI_EN) { 1601 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); 1602 /* Disable SMBus interrupt feature if SMBus using SMI# */ 1603 priv->features &= ~FEATURE_IRQ; 1604 } 1605 if (temp & SMBHSTCFG_SPD_WD) 1606 dev_info(&dev->dev, "SPD Write Disable is set\n"); 1607 1608 /* Clear special mode bits */ 1609 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) 1610 outb_p(inb_p(SMBAUXCTL(priv)) & 1611 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 1612 1613 /* Default timeout in interrupt mode: 200 ms */ 1614 priv->adapter.timeout = HZ / 5; 1615 1616 if (priv->features & FEATURE_IRQ) { 1617 u16 pcictl, pcists; 1618 1619 /* Complain if an interrupt is already pending */ 1620 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); 1621 if (pcists & SMBPCISTS_INTS) 1622 dev_warn(&dev->dev, "An interrupt is pending!\n"); 1623 1624 /* Check if interrupts have been disabled */ 1625 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl); 1626 if (pcictl & SMBPCICTL_INTDIS) { 1627 dev_info(&dev->dev, "Interrupts are disabled\n"); 1628 priv->features &= ~FEATURE_IRQ; 1629 } 1630 } 1631 1632 if (priv->features & FEATURE_IRQ) { 1633 init_waitqueue_head(&priv->waitq); 1634 1635 err = devm_request_irq(&dev->dev, dev->irq, i801_isr, 1636 IRQF_SHARED, 1637 dev_driver_string(&dev->dev), priv); 1638 if (err) { 1639 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n", 1640 dev->irq, err); 1641 priv->features &= ~FEATURE_IRQ; 1642 } 1643 } 1644 dev_info(&dev->dev, "SMBus using %s\n", 1645 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling"); 1646 1647 i801_add_tco(priv); 1648 1649 snprintf(priv->adapter.name, sizeof(priv->adapter.name), 1650 "SMBus I801 adapter at %04lx", priv->smba); 1651 err = i2c_add_adapter(&priv->adapter); 1652 if (err) { 1653 i801_acpi_remove(priv); 1654 return err; 1655 } 1656 1657 i801_enable_host_notify(&priv->adapter); 1658 1659 i801_probe_optional_slaves(priv); 1660 /* We ignore errors - multiplexing is optional */ 1661 i801_add_mux(priv); 1662 1663 pci_set_drvdata(dev, priv); 1664 1665 pm_runtime_set_autosuspend_delay(&dev->dev, 1000); 1666 pm_runtime_use_autosuspend(&dev->dev); 1667 pm_runtime_put_autosuspend(&dev->dev); 1668 pm_runtime_allow(&dev->dev); 1669 1670 return 0; 1671 } 1672 1673 static void i801_remove(struct pci_dev *dev) 1674 { 1675 struct i801_priv *priv = pci_get_drvdata(dev); 1676 1677 pm_runtime_forbid(&dev->dev); 1678 pm_runtime_get_noresume(&dev->dev); 1679 1680 i801_disable_host_notify(priv); 1681 i801_del_mux(priv); 1682 i2c_del_adapter(&priv->adapter); 1683 i801_acpi_remove(priv); 1684 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); 1685 1686 platform_device_unregister(priv->tco_pdev); 1687 1688 /* 1689 * do not call pci_disable_device(dev) since it can cause hard hangs on 1690 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) 1691 */ 1692 } 1693 1694 #ifdef CONFIG_PM 1695 static int i801_suspend(struct device *dev) 1696 { 1697 struct pci_dev *pci_dev = to_pci_dev(dev); 1698 struct i801_priv *priv = pci_get_drvdata(pci_dev); 1699 1700 pci_write_config_byte(pci_dev, SMBHSTCFG, priv->original_hstcfg); 1701 return 0; 1702 } 1703 1704 static int i801_resume(struct device *dev) 1705 { 1706 struct pci_dev *pci_dev = to_pci_dev(dev); 1707 struct i801_priv *priv = pci_get_drvdata(pci_dev); 1708 1709 i801_enable_host_notify(&priv->adapter); 1710 1711 return 0; 1712 } 1713 #endif 1714 1715 static UNIVERSAL_DEV_PM_OPS(i801_pm_ops, i801_suspend, 1716 i801_resume, NULL); 1717 1718 static struct pci_driver i801_driver = { 1719 .name = "i801_smbus", 1720 .id_table = i801_ids, 1721 .probe = i801_probe, 1722 .remove = i801_remove, 1723 .driver = { 1724 .pm = &i801_pm_ops, 1725 }, 1726 }; 1727 1728 static int __init i2c_i801_init(void) 1729 { 1730 if (dmi_name_in_vendors("FUJITSU")) 1731 input_apanel_init(); 1732 return pci_register_driver(&i801_driver); 1733 } 1734 1735 static void __exit i2c_i801_exit(void) 1736 { 1737 pci_unregister_driver(&i801_driver); 1738 } 1739 1740 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>"); 1741 MODULE_DESCRIPTION("I801 SMBus driver"); 1742 MODULE_LICENSE("GPL"); 1743 1744 module_init(i2c_i801_init); 1745 module_exit(i2c_i801_exit); 1746