1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, 4 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker 5 <mdsxyz123@yahoo.com> 6 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de> 7 Copyright (C) 2010 Intel Corporation, 8 David Woodhouse <dwmw2@infradead.org> 9 10 */ 11 12 /* 13 * Supports the following Intel I/O Controller Hubs (ICH): 14 * 15 * I/O Block I2C 16 * region SMBus Block proc. block 17 * Chip name PCI ID size PEC buffer call read 18 * --------------------------------------------------------------------------- 19 * 82801AA (ICH) 0x2413 16 no no no no 20 * 82801AB (ICH0) 0x2423 16 no no no no 21 * 82801BA (ICH2) 0x2443 16 no no no no 22 * 82801CA (ICH3) 0x2483 32 soft no no no 23 * 82801DB (ICH4) 0x24c3 32 hard yes no no 24 * 82801E (ICH5) 0x24d3 32 hard yes yes yes 25 * 6300ESB 0x25a4 32 hard yes yes yes 26 * 82801F (ICH6) 0x266a 32 hard yes yes yes 27 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes 28 * 82801G (ICH7) 0x27da 32 hard yes yes yes 29 * 82801H (ICH8) 0x283e 32 hard yes yes yes 30 * 82801I (ICH9) 0x2930 32 hard yes yes yes 31 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes 32 * ICH10 0x3a30 32 hard yes yes yes 33 * ICH10 0x3a60 32 hard yes yes yes 34 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes 35 * 6 Series (PCH) 0x1c22 32 hard yes yes yes 36 * Patsburg (PCH) 0x1d22 32 hard yes yes yes 37 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes 38 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes 39 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes 40 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes 41 * Panther Point (PCH) 0x1e22 32 hard yes yes yes 42 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes 43 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes 44 * Avoton (SOC) 0x1f3c 32 hard yes yes yes 45 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes 46 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes 47 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes 48 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes 49 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes 50 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes 51 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes 52 * BayTrail (SOC) 0x0f12 32 hard yes yes yes 53 * Braswell (SOC) 0x2292 32 hard yes yes yes 54 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes 55 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes 56 * DNV (SOC) 0x19df 32 hard yes yes yes 57 * Emmitsburg (PCH) 0x1bc9 32 hard yes yes yes 58 * Broxton (SOC) 0x5ad4 32 hard yes yes yes 59 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes 60 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes 61 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes 62 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes 63 * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes 64 * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes 65 * Cedar Fork (PCH) 0x18df 32 hard yes yes yes 66 * Ice Lake-LP (PCH) 0x34a3 32 hard yes yes yes 67 * Comet Lake (PCH) 0x02a3 32 hard yes yes yes 68 * Comet Lake-H (PCH) 0x06a3 32 hard yes yes yes 69 * Elkhart Lake (PCH) 0x4b23 32 hard yes yes yes 70 * Tiger Lake-LP (PCH) 0xa0a3 32 hard yes yes yes 71 * Tiger Lake-H (PCH) 0x43a3 32 hard yes yes yes 72 * Jasper Lake (SOC) 0x4da3 32 hard yes yes yes 73 * Comet Lake-V (PCH) 0xa3a3 32 hard yes yes yes 74 * 75 * Features supported by this driver: 76 * Software PEC no 77 * Hardware PEC yes 78 * Block buffer yes 79 * Block process call transaction yes 80 * I2C block read transaction yes (doesn't use the block buffer) 81 * Slave mode no 82 * SMBus Host Notify yes 83 * Interrupt processing yes 84 * 85 * See the file Documentation/i2c/busses/i2c-i801.rst for details. 86 */ 87 88 #include <linux/interrupt.h> 89 #include <linux/module.h> 90 #include <linux/pci.h> 91 #include <linux/kernel.h> 92 #include <linux/stddef.h> 93 #include <linux/delay.h> 94 #include <linux/ioport.h> 95 #include <linux/init.h> 96 #include <linux/i2c.h> 97 #include <linux/i2c-smbus.h> 98 #include <linux/acpi.h> 99 #include <linux/io.h> 100 #include <linux/dmi.h> 101 #include <linux/slab.h> 102 #include <linux/string.h> 103 #include <linux/wait.h> 104 #include <linux/err.h> 105 #include <linux/platform_device.h> 106 #include <linux/platform_data/itco_wdt.h> 107 #include <linux/pm_runtime.h> 108 109 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 110 #include <linux/gpio/machine.h> 111 #include <linux/platform_data/i2c-mux-gpio.h> 112 #endif 113 114 /* I801 SMBus address offsets */ 115 #define SMBHSTSTS(p) (0 + (p)->smba) 116 #define SMBHSTCNT(p) (2 + (p)->smba) 117 #define SMBHSTCMD(p) (3 + (p)->smba) 118 #define SMBHSTADD(p) (4 + (p)->smba) 119 #define SMBHSTDAT0(p) (5 + (p)->smba) 120 #define SMBHSTDAT1(p) (6 + (p)->smba) 121 #define SMBBLKDAT(p) (7 + (p)->smba) 122 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */ 123 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */ 124 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */ 125 #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */ 126 #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */ 127 #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */ 128 129 /* PCI Address Constants */ 130 #define SMBBAR 4 131 #define SMBPCICTL 0x004 132 #define SMBPCISTS 0x006 133 #define SMBHSTCFG 0x040 134 #define TCOBASE 0x050 135 #define TCOCTL 0x054 136 137 #define SBREG_BAR 0x10 138 #define SBREG_SMBCTRL 0xc6000c 139 #define SBREG_SMBCTRL_DNV 0xcf000c 140 141 /* Host status bits for SMBPCISTS */ 142 #define SMBPCISTS_INTS BIT(3) 143 144 /* Control bits for SMBPCICTL */ 145 #define SMBPCICTL_INTDIS BIT(10) 146 147 /* Host configuration bits for SMBHSTCFG */ 148 #define SMBHSTCFG_HST_EN BIT(0) 149 #define SMBHSTCFG_SMB_SMI_EN BIT(1) 150 #define SMBHSTCFG_I2C_EN BIT(2) 151 #define SMBHSTCFG_SPD_WD BIT(4) 152 153 /* TCO configuration bits for TCOCTL */ 154 #define TCOCTL_EN BIT(8) 155 156 /* Auxiliary status register bits, ICH4+ only */ 157 #define SMBAUXSTS_CRCE BIT(0) 158 #define SMBAUXSTS_STCO BIT(1) 159 160 /* Auxiliary control register bits, ICH4+ only */ 161 #define SMBAUXCTL_CRC BIT(0) 162 #define SMBAUXCTL_E32B BIT(1) 163 164 /* Other settings */ 165 #define MAX_RETRIES 400 166 167 /* I801 command constants */ 168 #define I801_QUICK 0x00 169 #define I801_BYTE 0x04 170 #define I801_BYTE_DATA 0x08 171 #define I801_WORD_DATA 0x0C 172 #define I801_PROC_CALL 0x10 /* unimplemented */ 173 #define I801_BLOCK_DATA 0x14 174 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ 175 #define I801_BLOCK_PROC_CALL 0x1C 176 177 /* I801 Host Control register bits */ 178 #define SMBHSTCNT_INTREN BIT(0) 179 #define SMBHSTCNT_KILL BIT(1) 180 #define SMBHSTCNT_LAST_BYTE BIT(5) 181 #define SMBHSTCNT_START BIT(6) 182 #define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */ 183 184 /* I801 Hosts Status register bits */ 185 #define SMBHSTSTS_BYTE_DONE BIT(7) 186 #define SMBHSTSTS_INUSE_STS BIT(6) 187 #define SMBHSTSTS_SMBALERT_STS BIT(5) 188 #define SMBHSTSTS_FAILED BIT(4) 189 #define SMBHSTSTS_BUS_ERR BIT(3) 190 #define SMBHSTSTS_DEV_ERR BIT(2) 191 #define SMBHSTSTS_INTR BIT(1) 192 #define SMBHSTSTS_HOST_BUSY BIT(0) 193 194 /* Host Notify Status register bits */ 195 #define SMBSLVSTS_HST_NTFY_STS BIT(0) 196 197 /* Host Notify Command register bits */ 198 #define SMBSLVCMD_HST_NTFY_INTREN BIT(0) 199 200 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \ 201 SMBHSTSTS_DEV_ERR) 202 203 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \ 204 STATUS_ERROR_FLAGS) 205 206 /* Older devices have their ID defined in <linux/pci_ids.h> */ 207 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS 0x02a3 208 #define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS 0x06a3 209 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12 210 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df 211 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df 212 #define PCI_DEVICE_ID_INTEL_EBG_SMBUS 0x1bc9 213 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 214 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 215 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */ 216 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70 217 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71 218 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72 219 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 220 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c 221 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292 222 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 223 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0 224 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4 225 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS 0x34a3 226 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 227 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS 0x43a3 228 #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS 0x4b23 229 #define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS 0x4da3 230 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4 231 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 232 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2 233 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22 234 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d 235 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e 236 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f 237 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22 238 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2 239 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23 240 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3 241 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS 0xa0a3 242 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123 243 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3 244 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223 245 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3 246 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323 247 #define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS 0xa3a3 248 249 struct i801_mux_config { 250 char *gpio_chip; 251 unsigned values[3]; 252 int n_values; 253 unsigned classes[3]; 254 unsigned gpios[2]; /* Relative to gpio_chip->base */ 255 int n_gpios; 256 }; 257 258 struct i801_priv { 259 struct i2c_adapter adapter; 260 unsigned long smba; 261 unsigned char original_hstcfg; 262 unsigned char original_slvcmd; 263 struct pci_dev *pci_dev; 264 unsigned int features; 265 266 /* isr processing */ 267 wait_queue_head_t waitq; 268 u8 status; 269 270 /* Command state used by isr for byte-by-byte block transactions */ 271 u8 cmd; 272 bool is_read; 273 int count; 274 int len; 275 u8 *data; 276 277 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 278 const struct i801_mux_config *mux_drvdata; 279 struct platform_device *mux_pdev; 280 struct gpiod_lookup_table *lookup; 281 #endif 282 struct platform_device *tco_pdev; 283 284 /* 285 * If set to true the host controller registers are reserved for 286 * ACPI AML use. Protected by acpi_lock. 287 */ 288 bool acpi_reserved; 289 struct mutex acpi_lock; 290 }; 291 292 #define FEATURE_SMBUS_PEC BIT(0) 293 #define FEATURE_BLOCK_BUFFER BIT(1) 294 #define FEATURE_BLOCK_PROC BIT(2) 295 #define FEATURE_I2C_BLOCK_READ BIT(3) 296 #define FEATURE_IRQ BIT(4) 297 #define FEATURE_HOST_NOTIFY BIT(5) 298 /* Not really a feature, but it's convenient to handle it as such */ 299 #define FEATURE_IDF BIT(15) 300 #define FEATURE_TCO_SPT BIT(16) 301 #define FEATURE_TCO_CNL BIT(17) 302 303 static const char *i801_feature_names[] = { 304 "SMBus PEC", 305 "Block buffer", 306 "Block process call", 307 "I2C block read", 308 "Interrupt", 309 "SMBus Host Notify", 310 }; 311 312 static unsigned int disable_features; 313 module_param(disable_features, uint, S_IRUGO | S_IWUSR); 314 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n" 315 "\t\t 0x01 disable SMBus PEC\n" 316 "\t\t 0x02 disable the block buffer\n" 317 "\t\t 0x08 disable the I2C block read functionality\n" 318 "\t\t 0x10 don't use interrupts\n" 319 "\t\t 0x20 disable SMBus Host Notify "); 320 321 /* Make sure the SMBus host is ready to start transmitting. 322 Return 0 if it is, -EBUSY if it is not. */ 323 static int i801_check_pre(struct i801_priv *priv) 324 { 325 int status; 326 327 status = inb_p(SMBHSTSTS(priv)); 328 if (status & SMBHSTSTS_HOST_BUSY) { 329 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n"); 330 return -EBUSY; 331 } 332 333 status &= STATUS_FLAGS; 334 if (status) { 335 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n", 336 status); 337 outb_p(status, SMBHSTSTS(priv)); 338 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS; 339 if (status) { 340 dev_err(&priv->pci_dev->dev, 341 "Failed clearing status flags (%02x)\n", 342 status); 343 return -EBUSY; 344 } 345 } 346 347 /* 348 * Clear CRC status if needed. 349 * During normal operation, i801_check_post() takes care 350 * of it after every operation. We do it here only in case 351 * the hardware was already in this state when the driver 352 * started. 353 */ 354 if (priv->features & FEATURE_SMBUS_PEC) { 355 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE; 356 if (status) { 357 dev_dbg(&priv->pci_dev->dev, 358 "Clearing aux status flags (%02x)\n", status); 359 outb_p(status, SMBAUXSTS(priv)); 360 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE; 361 if (status) { 362 dev_err(&priv->pci_dev->dev, 363 "Failed clearing aux status flags (%02x)\n", 364 status); 365 return -EBUSY; 366 } 367 } 368 } 369 370 return 0; 371 } 372 373 /* 374 * Convert the status register to an error code, and clear it. 375 * Note that status only contains the bits we want to clear, not the 376 * actual register value. 377 */ 378 static int i801_check_post(struct i801_priv *priv, int status) 379 { 380 int result = 0; 381 382 /* 383 * If the SMBus is still busy, we give up 384 * Note: This timeout condition only happens when using polling 385 * transactions. For interrupt operation, NAK/timeout is indicated by 386 * DEV_ERR. 387 */ 388 if (unlikely(status < 0)) { 389 dev_err(&priv->pci_dev->dev, "Transaction timeout\n"); 390 /* try to stop the current command */ 391 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n"); 392 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL, 393 SMBHSTCNT(priv)); 394 usleep_range(1000, 2000); 395 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL), 396 SMBHSTCNT(priv)); 397 398 /* Check if it worked */ 399 status = inb_p(SMBHSTSTS(priv)); 400 if ((status & SMBHSTSTS_HOST_BUSY) || 401 !(status & SMBHSTSTS_FAILED)) 402 dev_err(&priv->pci_dev->dev, 403 "Failed terminating the transaction\n"); 404 outb_p(STATUS_FLAGS, SMBHSTSTS(priv)); 405 return -ETIMEDOUT; 406 } 407 408 if (status & SMBHSTSTS_FAILED) { 409 result = -EIO; 410 dev_err(&priv->pci_dev->dev, "Transaction failed\n"); 411 } 412 if (status & SMBHSTSTS_DEV_ERR) { 413 /* 414 * This may be a PEC error, check and clear it. 415 * 416 * AUXSTS is handled differently from HSTSTS. 417 * For HSTSTS, i801_isr() or i801_wait_intr() 418 * has already cleared the error bits in hardware, 419 * and we are passed a copy of the original value 420 * in "status". 421 * For AUXSTS, the hardware register is left 422 * for us to handle here. 423 * This is asymmetric, slightly iffy, but safe, 424 * since all this code is serialized and the CRCE 425 * bit is harmless as long as it's cleared before 426 * the next operation. 427 */ 428 if ((priv->features & FEATURE_SMBUS_PEC) && 429 (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) { 430 outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv)); 431 result = -EBADMSG; 432 dev_dbg(&priv->pci_dev->dev, "PEC error\n"); 433 } else { 434 result = -ENXIO; 435 dev_dbg(&priv->pci_dev->dev, "No response\n"); 436 } 437 } 438 if (status & SMBHSTSTS_BUS_ERR) { 439 result = -EAGAIN; 440 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n"); 441 } 442 443 /* Clear status flags except BYTE_DONE, to be cleared by caller */ 444 outb_p(status, SMBHSTSTS(priv)); 445 446 return result; 447 } 448 449 /* Wait for BUSY being cleared and either INTR or an error flag being set */ 450 static int i801_wait_intr(struct i801_priv *priv) 451 { 452 int timeout = 0; 453 int status; 454 455 /* We will always wait for a fraction of a second! */ 456 do { 457 usleep_range(250, 500); 458 status = inb_p(SMBHSTSTS(priv)); 459 } while (((status & SMBHSTSTS_HOST_BUSY) || 460 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) && 461 (timeout++ < MAX_RETRIES)); 462 463 if (timeout > MAX_RETRIES) { 464 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n"); 465 return -ETIMEDOUT; 466 } 467 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR); 468 } 469 470 /* Wait for either BYTE_DONE or an error flag being set */ 471 static int i801_wait_byte_done(struct i801_priv *priv) 472 { 473 int timeout = 0; 474 int status; 475 476 /* We will always wait for a fraction of a second! */ 477 do { 478 usleep_range(250, 500); 479 status = inb_p(SMBHSTSTS(priv)); 480 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) && 481 (timeout++ < MAX_RETRIES)); 482 483 if (timeout > MAX_RETRIES) { 484 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n"); 485 return -ETIMEDOUT; 486 } 487 return status & STATUS_ERROR_FLAGS; 488 } 489 490 static int i801_transaction(struct i801_priv *priv, int xact) 491 { 492 int status; 493 int result; 494 const struct i2c_adapter *adap = &priv->adapter; 495 496 result = i801_check_pre(priv); 497 if (result < 0) 498 return result; 499 500 if (priv->features & FEATURE_IRQ) { 501 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START, 502 SMBHSTCNT(priv)); 503 result = wait_event_timeout(priv->waitq, 504 (status = priv->status), 505 adap->timeout); 506 if (!result) { 507 status = -ETIMEDOUT; 508 dev_warn(&priv->pci_dev->dev, 509 "Timeout waiting for interrupt!\n"); 510 } 511 priv->status = 0; 512 return i801_check_post(priv, status); 513 } 514 515 /* the current contents of SMBHSTCNT can be overwritten, since PEC, 516 * SMBSCMD are passed in xact */ 517 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv)); 518 519 status = i801_wait_intr(priv); 520 return i801_check_post(priv, status); 521 } 522 523 static int i801_block_transaction_by_block(struct i801_priv *priv, 524 union i2c_smbus_data *data, 525 char read_write, int command, 526 int hwpec) 527 { 528 int i, len; 529 int status; 530 int xact = hwpec ? SMBHSTCNT_PEC_EN : 0; 531 532 switch (command) { 533 case I2C_SMBUS_BLOCK_PROC_CALL: 534 xact |= I801_BLOCK_PROC_CALL; 535 break; 536 case I2C_SMBUS_BLOCK_DATA: 537 xact |= I801_BLOCK_DATA; 538 break; 539 default: 540 return -EOPNOTSUPP; 541 } 542 543 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ 544 545 /* Use 32-byte buffer to process this transaction */ 546 if (read_write == I2C_SMBUS_WRITE) { 547 len = data->block[0]; 548 outb_p(len, SMBHSTDAT0(priv)); 549 for (i = 0; i < len; i++) 550 outb_p(data->block[i+1], SMBBLKDAT(priv)); 551 } 552 553 status = i801_transaction(priv, xact); 554 if (status) 555 return status; 556 557 if (read_write == I2C_SMBUS_READ || 558 command == I2C_SMBUS_BLOCK_PROC_CALL) { 559 len = inb_p(SMBHSTDAT0(priv)); 560 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) 561 return -EPROTO; 562 563 data->block[0] = len; 564 for (i = 0; i < len; i++) 565 data->block[i + 1] = inb_p(SMBBLKDAT(priv)); 566 } 567 return 0; 568 } 569 570 static void i801_isr_byte_done(struct i801_priv *priv) 571 { 572 if (priv->is_read) { 573 /* For SMBus block reads, length is received with first byte */ 574 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) && 575 (priv->count == 0)) { 576 priv->len = inb_p(SMBHSTDAT0(priv)); 577 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) { 578 dev_err(&priv->pci_dev->dev, 579 "Illegal SMBus block read size %d\n", 580 priv->len); 581 /* FIXME: Recover */ 582 priv->len = I2C_SMBUS_BLOCK_MAX; 583 } else { 584 dev_dbg(&priv->pci_dev->dev, 585 "SMBus block read size is %d\n", 586 priv->len); 587 } 588 priv->data[-1] = priv->len; 589 } 590 591 /* Read next byte */ 592 if (priv->count < priv->len) 593 priv->data[priv->count++] = inb(SMBBLKDAT(priv)); 594 else 595 dev_dbg(&priv->pci_dev->dev, 596 "Discarding extra byte on block read\n"); 597 598 /* Set LAST_BYTE for last byte of read transaction */ 599 if (priv->count == priv->len - 1) 600 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE, 601 SMBHSTCNT(priv)); 602 } else if (priv->count < priv->len - 1) { 603 /* Write next byte, except for IRQ after last byte */ 604 outb_p(priv->data[++priv->count], SMBBLKDAT(priv)); 605 } 606 607 /* Clear BYTE_DONE to continue with next byte */ 608 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 609 } 610 611 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv) 612 { 613 unsigned short addr; 614 615 addr = inb_p(SMBNTFDADD(priv)) >> 1; 616 617 /* 618 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba) 619 * always returns 0. Our current implementation doesn't provide 620 * data, so we just ignore it. 621 */ 622 i2c_handle_smbus_host_notify(&priv->adapter, addr); 623 624 /* clear Host Notify bit and return */ 625 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 626 return IRQ_HANDLED; 627 } 628 629 /* 630 * There are three kinds of interrupts: 631 * 632 * 1) i801 signals transaction completion with one of these interrupts: 633 * INTR - Success 634 * DEV_ERR - Invalid command, NAK or communication timeout 635 * BUS_ERR - SMI# transaction collision 636 * FAILED - transaction was canceled due to a KILL request 637 * When any of these occur, update ->status and wake up the waitq. 638 * ->status must be cleared before kicking off the next transaction. 639 * 640 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt 641 * occurs for each byte of a byte-by-byte to prepare the next byte. 642 * 643 * 3) Host Notify interrupts 644 */ 645 static irqreturn_t i801_isr(int irq, void *dev_id) 646 { 647 struct i801_priv *priv = dev_id; 648 u16 pcists; 649 u8 status; 650 651 /* Confirm this is our interrupt */ 652 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); 653 if (!(pcists & SMBPCISTS_INTS)) 654 return IRQ_NONE; 655 656 if (priv->features & FEATURE_HOST_NOTIFY) { 657 status = inb_p(SMBSLVSTS(priv)); 658 if (status & SMBSLVSTS_HST_NTFY_STS) 659 return i801_host_notify_isr(priv); 660 } 661 662 status = inb_p(SMBHSTSTS(priv)); 663 if (status & SMBHSTSTS_BYTE_DONE) 664 i801_isr_byte_done(priv); 665 666 /* 667 * Clear irq sources and report transaction result. 668 * ->status must be cleared before the next transaction is started. 669 */ 670 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS; 671 if (status) { 672 outb_p(status, SMBHSTSTS(priv)); 673 priv->status = status; 674 wake_up(&priv->waitq); 675 } 676 677 return IRQ_HANDLED; 678 } 679 680 /* 681 * For "byte-by-byte" block transactions: 682 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1 683 * I2C read uses cmd=I801_I2C_BLOCK_DATA 684 */ 685 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, 686 union i2c_smbus_data *data, 687 char read_write, int command, 688 int hwpec) 689 { 690 int i, len; 691 int smbcmd; 692 int status; 693 int result; 694 const struct i2c_adapter *adap = &priv->adapter; 695 696 if (command == I2C_SMBUS_BLOCK_PROC_CALL) 697 return -EOPNOTSUPP; 698 699 result = i801_check_pre(priv); 700 if (result < 0) 701 return result; 702 703 len = data->block[0]; 704 705 if (read_write == I2C_SMBUS_WRITE) { 706 outb_p(len, SMBHSTDAT0(priv)); 707 outb_p(data->block[1], SMBBLKDAT(priv)); 708 } 709 710 if (command == I2C_SMBUS_I2C_BLOCK_DATA && 711 read_write == I2C_SMBUS_READ) 712 smbcmd = I801_I2C_BLOCK_DATA; 713 else 714 smbcmd = I801_BLOCK_DATA; 715 716 if (priv->features & FEATURE_IRQ) { 717 priv->is_read = (read_write == I2C_SMBUS_READ); 718 if (len == 1 && priv->is_read) 719 smbcmd |= SMBHSTCNT_LAST_BYTE; 720 priv->cmd = smbcmd | SMBHSTCNT_INTREN; 721 priv->len = len; 722 priv->count = 0; 723 priv->data = &data->block[1]; 724 725 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv)); 726 result = wait_event_timeout(priv->waitq, 727 (status = priv->status), 728 adap->timeout); 729 if (!result) { 730 status = -ETIMEDOUT; 731 dev_warn(&priv->pci_dev->dev, 732 "Timeout waiting for interrupt!\n"); 733 } 734 priv->status = 0; 735 return i801_check_post(priv, status); 736 } 737 738 for (i = 1; i <= len; i++) { 739 if (i == len && read_write == I2C_SMBUS_READ) 740 smbcmd |= SMBHSTCNT_LAST_BYTE; 741 outb_p(smbcmd, SMBHSTCNT(priv)); 742 743 if (i == 1) 744 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START, 745 SMBHSTCNT(priv)); 746 747 status = i801_wait_byte_done(priv); 748 if (status) 749 goto exit; 750 751 if (i == 1 && read_write == I2C_SMBUS_READ 752 && command != I2C_SMBUS_I2C_BLOCK_DATA) { 753 len = inb_p(SMBHSTDAT0(priv)); 754 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { 755 dev_err(&priv->pci_dev->dev, 756 "Illegal SMBus block read size %d\n", 757 len); 758 /* Recover */ 759 while (inb_p(SMBHSTSTS(priv)) & 760 SMBHSTSTS_HOST_BUSY) 761 outb_p(SMBHSTSTS_BYTE_DONE, 762 SMBHSTSTS(priv)); 763 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); 764 return -EPROTO; 765 } 766 data->block[0] = len; 767 } 768 769 /* Retrieve/store value in SMBBLKDAT */ 770 if (read_write == I2C_SMBUS_READ) 771 data->block[i] = inb_p(SMBBLKDAT(priv)); 772 if (read_write == I2C_SMBUS_WRITE && i+1 <= len) 773 outb_p(data->block[i+1], SMBBLKDAT(priv)); 774 775 /* signals SMBBLKDAT ready */ 776 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 777 } 778 779 status = i801_wait_intr(priv); 780 exit: 781 return i801_check_post(priv, status); 782 } 783 784 static int i801_set_block_buffer_mode(struct i801_priv *priv) 785 { 786 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv)); 787 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0) 788 return -EIO; 789 return 0; 790 } 791 792 /* Block transaction function */ 793 static int i801_block_transaction(struct i801_priv *priv, 794 union i2c_smbus_data *data, char read_write, 795 int command, int hwpec) 796 { 797 int result = 0; 798 unsigned char hostc; 799 800 if (command == I2C_SMBUS_I2C_BLOCK_DATA) { 801 if (read_write == I2C_SMBUS_WRITE) { 802 /* set I2C_EN bit in configuration register */ 803 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc); 804 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, 805 hostc | SMBHSTCFG_I2C_EN); 806 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) { 807 dev_err(&priv->pci_dev->dev, 808 "I2C block read is unsupported!\n"); 809 return -EOPNOTSUPP; 810 } 811 } 812 813 if (read_write == I2C_SMBUS_WRITE 814 || command == I2C_SMBUS_I2C_BLOCK_DATA) { 815 if (data->block[0] < 1) 816 data->block[0] = 1; 817 if (data->block[0] > I2C_SMBUS_BLOCK_MAX) 818 data->block[0] = I2C_SMBUS_BLOCK_MAX; 819 } else { 820 data->block[0] = 32; /* max for SMBus block reads */ 821 } 822 823 /* Experience has shown that the block buffer can only be used for 824 SMBus (not I2C) block transactions, even though the datasheet 825 doesn't mention this limitation. */ 826 if ((priv->features & FEATURE_BLOCK_BUFFER) 827 && command != I2C_SMBUS_I2C_BLOCK_DATA 828 && i801_set_block_buffer_mode(priv) == 0) 829 result = i801_block_transaction_by_block(priv, data, 830 read_write, 831 command, hwpec); 832 else 833 result = i801_block_transaction_byte_by_byte(priv, data, 834 read_write, 835 command, hwpec); 836 837 if (command == I2C_SMBUS_I2C_BLOCK_DATA 838 && read_write == I2C_SMBUS_WRITE) { 839 /* restore saved configuration register value */ 840 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc); 841 } 842 return result; 843 } 844 845 /* Return negative errno on error. */ 846 static s32 i801_access(struct i2c_adapter *adap, u16 addr, 847 unsigned short flags, char read_write, u8 command, 848 int size, union i2c_smbus_data *data) 849 { 850 int hwpec; 851 int block = 0; 852 int ret = 0, xact = 0; 853 struct i801_priv *priv = i2c_get_adapdata(adap); 854 855 mutex_lock(&priv->acpi_lock); 856 if (priv->acpi_reserved) { 857 mutex_unlock(&priv->acpi_lock); 858 return -EBUSY; 859 } 860 861 pm_runtime_get_sync(&priv->pci_dev->dev); 862 863 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) 864 && size != I2C_SMBUS_QUICK 865 && size != I2C_SMBUS_I2C_BLOCK_DATA; 866 867 switch (size) { 868 case I2C_SMBUS_QUICK: 869 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 870 SMBHSTADD(priv)); 871 xact = I801_QUICK; 872 break; 873 case I2C_SMBUS_BYTE: 874 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 875 SMBHSTADD(priv)); 876 if (read_write == I2C_SMBUS_WRITE) 877 outb_p(command, SMBHSTCMD(priv)); 878 xact = I801_BYTE; 879 break; 880 case I2C_SMBUS_BYTE_DATA: 881 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 882 SMBHSTADD(priv)); 883 outb_p(command, SMBHSTCMD(priv)); 884 if (read_write == I2C_SMBUS_WRITE) 885 outb_p(data->byte, SMBHSTDAT0(priv)); 886 xact = I801_BYTE_DATA; 887 break; 888 case I2C_SMBUS_WORD_DATA: 889 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 890 SMBHSTADD(priv)); 891 outb_p(command, SMBHSTCMD(priv)); 892 if (read_write == I2C_SMBUS_WRITE) { 893 outb_p(data->word & 0xff, SMBHSTDAT0(priv)); 894 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); 895 } 896 xact = I801_WORD_DATA; 897 break; 898 case I2C_SMBUS_BLOCK_DATA: 899 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 900 SMBHSTADD(priv)); 901 outb_p(command, SMBHSTCMD(priv)); 902 block = 1; 903 break; 904 case I2C_SMBUS_I2C_BLOCK_DATA: 905 /* 906 * NB: page 240 of ICH5 datasheet shows that the R/#W 907 * bit should be cleared here, even when reading. 908 * However if SPD Write Disable is set (Lynx Point and later), 909 * the read will fail if we don't set the R/#W bit. 910 */ 911 outb_p(((addr & 0x7f) << 1) | 912 ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ? 913 (read_write & 0x01) : 0), 914 SMBHSTADD(priv)); 915 if (read_write == I2C_SMBUS_READ) { 916 /* NB: page 240 of ICH5 datasheet also shows 917 * that DATA1 is the cmd field when reading */ 918 outb_p(command, SMBHSTDAT1(priv)); 919 } else 920 outb_p(command, SMBHSTCMD(priv)); 921 block = 1; 922 break; 923 case I2C_SMBUS_BLOCK_PROC_CALL: 924 /* 925 * Bit 0 of the slave address register always indicate a write 926 * command. 927 */ 928 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv)); 929 outb_p(command, SMBHSTCMD(priv)); 930 block = 1; 931 break; 932 default: 933 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n", 934 size); 935 ret = -EOPNOTSUPP; 936 goto out; 937 } 938 939 if (hwpec) /* enable/disable hardware PEC */ 940 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv)); 941 else 942 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC), 943 SMBAUXCTL(priv)); 944 945 if (block) 946 ret = i801_block_transaction(priv, data, read_write, size, 947 hwpec); 948 else 949 ret = i801_transaction(priv, xact); 950 951 /* Some BIOSes don't like it when PEC is enabled at reboot or resume 952 time, so we forcibly disable it after every transaction. Turn off 953 E32B for the same reason. */ 954 if (hwpec || block) 955 outb_p(inb_p(SMBAUXCTL(priv)) & 956 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 957 958 if (block) 959 goto out; 960 if (ret) 961 goto out; 962 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK)) 963 goto out; 964 965 switch (xact & 0x7f) { 966 case I801_BYTE: /* Result put in SMBHSTDAT0 */ 967 case I801_BYTE_DATA: 968 data->byte = inb_p(SMBHSTDAT0(priv)); 969 break; 970 case I801_WORD_DATA: 971 data->word = inb_p(SMBHSTDAT0(priv)) + 972 (inb_p(SMBHSTDAT1(priv)) << 8); 973 break; 974 } 975 976 out: 977 pm_runtime_mark_last_busy(&priv->pci_dev->dev); 978 pm_runtime_put_autosuspend(&priv->pci_dev->dev); 979 mutex_unlock(&priv->acpi_lock); 980 return ret; 981 } 982 983 984 static u32 i801_func(struct i2c_adapter *adapter) 985 { 986 struct i801_priv *priv = i2c_get_adapdata(adapter); 987 988 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 989 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 990 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | 991 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | 992 ((priv->features & FEATURE_BLOCK_PROC) ? 993 I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) | 994 ((priv->features & FEATURE_I2C_BLOCK_READ) ? 995 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) | 996 ((priv->features & FEATURE_HOST_NOTIFY) ? 997 I2C_FUNC_SMBUS_HOST_NOTIFY : 0); 998 } 999 1000 static void i801_enable_host_notify(struct i2c_adapter *adapter) 1001 { 1002 struct i801_priv *priv = i2c_get_adapdata(adapter); 1003 1004 if (!(priv->features & FEATURE_HOST_NOTIFY)) 1005 return; 1006 1007 if (!(SMBSLVCMD_HST_NTFY_INTREN & priv->original_slvcmd)) 1008 outb_p(SMBSLVCMD_HST_NTFY_INTREN | priv->original_slvcmd, 1009 SMBSLVCMD(priv)); 1010 1011 /* clear Host Notify bit to allow a new notification */ 1012 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 1013 } 1014 1015 static void i801_disable_host_notify(struct i801_priv *priv) 1016 { 1017 if (!(priv->features & FEATURE_HOST_NOTIFY)) 1018 return; 1019 1020 outb_p(priv->original_slvcmd, SMBSLVCMD(priv)); 1021 } 1022 1023 static const struct i2c_algorithm smbus_algorithm = { 1024 .smbus_xfer = i801_access, 1025 .functionality = i801_func, 1026 }; 1027 1028 static const struct pci_device_id i801_ids[] = { 1029 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) }, 1030 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) }, 1031 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) }, 1032 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) }, 1033 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) }, 1034 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) }, 1035 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) }, 1036 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) }, 1037 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) }, 1038 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) }, 1039 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) }, 1040 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) }, 1041 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) }, 1042 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) }, 1043 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) }, 1044 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) }, 1045 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) }, 1046 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) }, 1047 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) }, 1048 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) }, 1049 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) }, 1050 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) }, 1051 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) }, 1052 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) }, 1053 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) }, 1054 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) }, 1055 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) }, 1056 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) }, 1057 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) }, 1058 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) }, 1059 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) }, 1060 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS) }, 1061 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) }, 1062 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) }, 1063 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) }, 1064 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) }, 1065 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) }, 1066 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) }, 1067 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMBUS) }, 1068 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) }, 1069 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EBG_SMBUS) }, 1070 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) }, 1071 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) }, 1072 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) }, 1073 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) }, 1074 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS) }, 1075 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS) }, 1076 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS) }, 1077 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS) }, 1078 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS) }, 1079 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS) }, 1080 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS) }, 1081 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS) }, 1082 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS) }, 1083 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS) }, 1084 { 0, } 1085 }; 1086 1087 MODULE_DEVICE_TABLE(pci, i801_ids); 1088 1089 #if defined CONFIG_X86 && defined CONFIG_DMI 1090 static unsigned char apanel_addr; 1091 1092 /* Scan the system ROM for the signature "FJKEYINF" */ 1093 static __init const void __iomem *bios_signature(const void __iomem *bios) 1094 { 1095 ssize_t offset; 1096 const unsigned char signature[] = "FJKEYINF"; 1097 1098 for (offset = 0; offset < 0x10000; offset += 0x10) { 1099 if (check_signature(bios + offset, signature, 1100 sizeof(signature)-1)) 1101 return bios + offset; 1102 } 1103 return NULL; 1104 } 1105 1106 static void __init input_apanel_init(void) 1107 { 1108 void __iomem *bios; 1109 const void __iomem *p; 1110 1111 bios = ioremap(0xF0000, 0x10000); /* Can't fail */ 1112 p = bios_signature(bios); 1113 if (p) { 1114 /* just use the first address */ 1115 apanel_addr = readb(p + 8 + 3) >> 1; 1116 } 1117 iounmap(bios); 1118 } 1119 1120 struct dmi_onboard_device_info { 1121 const char *name; 1122 u8 type; 1123 unsigned short i2c_addr; 1124 const char *i2c_type; 1125 }; 1126 1127 static const struct dmi_onboard_device_info dmi_devices[] = { 1128 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" }, 1129 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" }, 1130 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" }, 1131 }; 1132 1133 static void dmi_check_onboard_device(u8 type, const char *name, 1134 struct i2c_adapter *adap) 1135 { 1136 int i; 1137 struct i2c_board_info info; 1138 1139 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) { 1140 /* & ~0x80, ignore enabled/disabled bit */ 1141 if ((type & ~0x80) != dmi_devices[i].type) 1142 continue; 1143 if (strcasecmp(name, dmi_devices[i].name)) 1144 continue; 1145 1146 memset(&info, 0, sizeof(struct i2c_board_info)); 1147 info.addr = dmi_devices[i].i2c_addr; 1148 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); 1149 i2c_new_client_device(adap, &info); 1150 break; 1151 } 1152 } 1153 1154 /* We use our own function to check for onboard devices instead of 1155 dmi_find_device() as some buggy BIOS's have the devices we are interested 1156 in marked as disabled */ 1157 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap) 1158 { 1159 int i, count; 1160 1161 if (dm->type != 10) 1162 return; 1163 1164 count = (dm->length - sizeof(struct dmi_header)) / 2; 1165 for (i = 0; i < count; i++) { 1166 const u8 *d = (char *)(dm + 1) + (i * 2); 1167 const char *name = ((char *) dm) + dm->length; 1168 u8 type = d[0]; 1169 u8 s = d[1]; 1170 1171 if (!s) 1172 continue; 1173 s--; 1174 while (s > 0 && name[0]) { 1175 name += strlen(name) + 1; 1176 s--; 1177 } 1178 if (name[0] == 0) /* Bogus string reference */ 1179 continue; 1180 1181 dmi_check_onboard_device(type, name, adap); 1182 } 1183 } 1184 1185 /* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */ 1186 static const char *const acpi_smo8800_ids[] = { 1187 "SMO8800", 1188 "SMO8801", 1189 "SMO8810", 1190 "SMO8811", 1191 "SMO8820", 1192 "SMO8821", 1193 "SMO8830", 1194 "SMO8831", 1195 }; 1196 1197 static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle, 1198 u32 nesting_level, 1199 void *context, 1200 void **return_value) 1201 { 1202 struct acpi_device_info *info; 1203 acpi_status status; 1204 char *hid; 1205 int i; 1206 1207 status = acpi_get_object_info(obj_handle, &info); 1208 if (ACPI_FAILURE(status)) 1209 return AE_OK; 1210 1211 if (!(info->valid & ACPI_VALID_HID)) 1212 goto smo88xx_not_found; 1213 1214 hid = info->hardware_id.string; 1215 if (!hid) 1216 goto smo88xx_not_found; 1217 1218 i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid); 1219 if (i < 0) 1220 goto smo88xx_not_found; 1221 1222 kfree(info); 1223 1224 *((bool *)return_value) = true; 1225 return AE_CTRL_TERMINATE; 1226 1227 smo88xx_not_found: 1228 kfree(info); 1229 return AE_OK; 1230 } 1231 1232 static bool is_dell_system_with_lis3lv02d(void) 1233 { 1234 bool found; 1235 const char *vendor; 1236 1237 vendor = dmi_get_system_info(DMI_SYS_VENDOR); 1238 if (!vendor || strcmp(vendor, "Dell Inc.")) 1239 return false; 1240 1241 /* 1242 * Check that ACPI device SMO88xx is present and is functioning. 1243 * Function acpi_get_devices() already filters all ACPI devices 1244 * which are not present or are not functioning. 1245 * ACPI device SMO88xx represents our ST microelectronics lis3lv02d 1246 * accelerometer but unfortunately ACPI does not provide any other 1247 * information (like I2C address). 1248 */ 1249 found = false; 1250 acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL, 1251 (void **)&found); 1252 1253 return found; 1254 } 1255 1256 /* 1257 * Accelerometer's I2C address is not specified in DMI nor ACPI, 1258 * so it is needed to define mapping table based on DMI product names. 1259 */ 1260 static const struct { 1261 const char *dmi_product_name; 1262 unsigned short i2c_addr; 1263 } dell_lis3lv02d_devices[] = { 1264 /* 1265 * Dell platform team told us that these Latitude devices have 1266 * ST microelectronics accelerometer at I2C address 0x29. 1267 */ 1268 { "Latitude E5250", 0x29 }, 1269 { "Latitude E5450", 0x29 }, 1270 { "Latitude E5550", 0x29 }, 1271 { "Latitude E6440", 0x29 }, 1272 { "Latitude E6440 ATG", 0x29 }, 1273 { "Latitude E6540", 0x29 }, 1274 /* 1275 * Additional individual entries were added after verification. 1276 */ 1277 { "Vostro V131", 0x1d }, 1278 }; 1279 1280 static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv) 1281 { 1282 struct i2c_board_info info; 1283 const char *dmi_product_name; 1284 int i; 1285 1286 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME); 1287 for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) { 1288 if (strcmp(dmi_product_name, 1289 dell_lis3lv02d_devices[i].dmi_product_name) == 0) 1290 break; 1291 } 1292 1293 if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) { 1294 dev_warn(&priv->pci_dev->dev, 1295 "Accelerometer lis3lv02d is present on SMBus but its" 1296 " address is unknown, skipping registration\n"); 1297 return; 1298 } 1299 1300 memset(&info, 0, sizeof(struct i2c_board_info)); 1301 info.addr = dell_lis3lv02d_devices[i].i2c_addr; 1302 strlcpy(info.type, "lis3lv02d", I2C_NAME_SIZE); 1303 i2c_new_client_device(&priv->adapter, &info); 1304 } 1305 1306 /* Register optional slaves */ 1307 static void i801_probe_optional_slaves(struct i801_priv *priv) 1308 { 1309 /* Only register slaves on main SMBus channel */ 1310 if (priv->features & FEATURE_IDF) 1311 return; 1312 1313 if (apanel_addr) { 1314 struct i2c_board_info info; 1315 1316 memset(&info, 0, sizeof(struct i2c_board_info)); 1317 info.addr = apanel_addr; 1318 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE); 1319 i2c_new_client_device(&priv->adapter, &info); 1320 } 1321 1322 if (dmi_name_in_vendors("FUJITSU")) 1323 dmi_walk(dmi_check_onboard_devices, &priv->adapter); 1324 1325 if (is_dell_system_with_lis3lv02d()) 1326 register_dell_lis3lv02d_i2c_device(priv); 1327 1328 /* Instantiate SPD EEPROMs unless the SMBus is multiplexed */ 1329 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) 1330 if (!priv->mux_drvdata) 1331 #endif 1332 i2c_register_spd(&priv->adapter); 1333 } 1334 #else 1335 static void __init input_apanel_init(void) {} 1336 static void i801_probe_optional_slaves(struct i801_priv *priv) {} 1337 #endif /* CONFIG_X86 && CONFIG_DMI */ 1338 1339 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 1340 static struct i801_mux_config i801_mux_config_asus_z8_d12 = { 1341 .gpio_chip = "gpio_ich", 1342 .values = { 0x02, 0x03 }, 1343 .n_values = 2, 1344 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD }, 1345 .gpios = { 52, 53 }, 1346 .n_gpios = 2, 1347 }; 1348 1349 static struct i801_mux_config i801_mux_config_asus_z8_d18 = { 1350 .gpio_chip = "gpio_ich", 1351 .values = { 0x02, 0x03, 0x01 }, 1352 .n_values = 3, 1353 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD }, 1354 .gpios = { 52, 53 }, 1355 .n_gpios = 2, 1356 }; 1357 1358 static const struct dmi_system_id mux_dmi_table[] = { 1359 { 1360 .matches = { 1361 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1362 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"), 1363 }, 1364 .driver_data = &i801_mux_config_asus_z8_d12, 1365 }, 1366 { 1367 .matches = { 1368 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1369 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"), 1370 }, 1371 .driver_data = &i801_mux_config_asus_z8_d12, 1372 }, 1373 { 1374 .matches = { 1375 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1376 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"), 1377 }, 1378 .driver_data = &i801_mux_config_asus_z8_d12, 1379 }, 1380 { 1381 .matches = { 1382 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1383 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"), 1384 }, 1385 .driver_data = &i801_mux_config_asus_z8_d12, 1386 }, 1387 { 1388 .matches = { 1389 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1390 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"), 1391 }, 1392 .driver_data = &i801_mux_config_asus_z8_d12, 1393 }, 1394 { 1395 .matches = { 1396 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1397 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"), 1398 }, 1399 .driver_data = &i801_mux_config_asus_z8_d12, 1400 }, 1401 { 1402 .matches = { 1403 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1404 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"), 1405 }, 1406 .driver_data = &i801_mux_config_asus_z8_d18, 1407 }, 1408 { 1409 .matches = { 1410 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1411 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"), 1412 }, 1413 .driver_data = &i801_mux_config_asus_z8_d18, 1414 }, 1415 { 1416 .matches = { 1417 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1418 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"), 1419 }, 1420 .driver_data = &i801_mux_config_asus_z8_d12, 1421 }, 1422 { } 1423 }; 1424 1425 /* Setup multiplexing if needed */ 1426 static int i801_add_mux(struct i801_priv *priv) 1427 { 1428 struct device *dev = &priv->adapter.dev; 1429 const struct i801_mux_config *mux_config; 1430 struct i2c_mux_gpio_platform_data gpio_data; 1431 struct gpiod_lookup_table *lookup; 1432 int err, i; 1433 1434 if (!priv->mux_drvdata) 1435 return 0; 1436 mux_config = priv->mux_drvdata; 1437 1438 /* Prepare the platform data */ 1439 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data)); 1440 gpio_data.parent = priv->adapter.nr; 1441 gpio_data.values = mux_config->values; 1442 gpio_data.n_values = mux_config->n_values; 1443 gpio_data.classes = mux_config->classes; 1444 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE; 1445 1446 /* Register GPIO descriptor lookup table */ 1447 lookup = devm_kzalloc(dev, 1448 struct_size(lookup, table, mux_config->n_gpios), 1449 GFP_KERNEL); 1450 if (!lookup) 1451 return -ENOMEM; 1452 lookup->dev_id = "i2c-mux-gpio"; 1453 for (i = 0; i < mux_config->n_gpios; i++) { 1454 lookup->table[i] = (struct gpiod_lookup) 1455 GPIO_LOOKUP(mux_config->gpio_chip, 1456 mux_config->gpios[i], "mux", 0); 1457 } 1458 gpiod_add_lookup_table(lookup); 1459 priv->lookup = lookup; 1460 1461 /* 1462 * Register the mux device, we use PLATFORM_DEVID_NONE here 1463 * because since we are referring to the GPIO chip by name we are 1464 * anyways in deep trouble if there is more than one of these 1465 * devices, and there should likely only be one platform controller 1466 * hub. 1467 */ 1468 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio", 1469 PLATFORM_DEVID_NONE, &gpio_data, 1470 sizeof(struct i2c_mux_gpio_platform_data)); 1471 if (IS_ERR(priv->mux_pdev)) { 1472 err = PTR_ERR(priv->mux_pdev); 1473 gpiod_remove_lookup_table(lookup); 1474 priv->mux_pdev = NULL; 1475 dev_err(dev, "Failed to register i2c-mux-gpio device\n"); 1476 return err; 1477 } 1478 1479 return 0; 1480 } 1481 1482 static void i801_del_mux(struct i801_priv *priv) 1483 { 1484 if (priv->mux_pdev) 1485 platform_device_unregister(priv->mux_pdev); 1486 if (priv->lookup) 1487 gpiod_remove_lookup_table(priv->lookup); 1488 } 1489 1490 static unsigned int i801_get_adapter_class(struct i801_priv *priv) 1491 { 1492 const struct dmi_system_id *id; 1493 const struct i801_mux_config *mux_config; 1494 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 1495 int i; 1496 1497 id = dmi_first_match(mux_dmi_table); 1498 if (id) { 1499 /* Remove branch classes from trunk */ 1500 mux_config = id->driver_data; 1501 for (i = 0; i < mux_config->n_values; i++) 1502 class &= ~mux_config->classes[i]; 1503 1504 /* Remember for later */ 1505 priv->mux_drvdata = mux_config; 1506 } 1507 1508 return class; 1509 } 1510 #else 1511 static inline int i801_add_mux(struct i801_priv *priv) { return 0; } 1512 static inline void i801_del_mux(struct i801_priv *priv) { } 1513 1514 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv) 1515 { 1516 return I2C_CLASS_HWMON | I2C_CLASS_SPD; 1517 } 1518 #endif 1519 1520 static const struct itco_wdt_platform_data spt_tco_platform_data = { 1521 .name = "Intel PCH", 1522 .version = 4, 1523 }; 1524 1525 static DEFINE_SPINLOCK(p2sb_spinlock); 1526 1527 static struct platform_device * 1528 i801_add_tco_spt(struct i801_priv *priv, struct pci_dev *pci_dev, 1529 struct resource *tco_res) 1530 { 1531 struct resource *res; 1532 unsigned int devfn; 1533 u64 base64_addr; 1534 u32 base_addr; 1535 u8 hidden; 1536 1537 /* 1538 * We must access the NO_REBOOT bit over the Primary to Sideband 1539 * bridge (P2SB). The BIOS prevents the P2SB device from being 1540 * enumerated by the PCI subsystem, so we need to unhide/hide it 1541 * to lookup the P2SB BAR. 1542 */ 1543 spin_lock(&p2sb_spinlock); 1544 1545 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1); 1546 1547 /* Unhide the P2SB device, if it is hidden */ 1548 pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden); 1549 if (hidden) 1550 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0); 1551 1552 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr); 1553 base64_addr = base_addr & 0xfffffff0; 1554 1555 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr); 1556 base64_addr |= (u64)base_addr << 32; 1557 1558 /* Hide the P2SB device, if it was hidden before */ 1559 if (hidden) 1560 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden); 1561 spin_unlock(&p2sb_spinlock); 1562 1563 res = &tco_res[1]; 1564 if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS) 1565 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV; 1566 else 1567 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL; 1568 1569 res->end = res->start + 3; 1570 res->flags = IORESOURCE_MEM; 1571 1572 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1, 1573 tco_res, 2, &spt_tco_platform_data, 1574 sizeof(spt_tco_platform_data)); 1575 } 1576 1577 static const struct itco_wdt_platform_data cnl_tco_platform_data = { 1578 .name = "Intel PCH", 1579 .version = 6, 1580 }; 1581 1582 static struct platform_device * 1583 i801_add_tco_cnl(struct i801_priv *priv, struct pci_dev *pci_dev, 1584 struct resource *tco_res) 1585 { 1586 return platform_device_register_resndata(&pci_dev->dev, 1587 "iTCO_wdt", -1, tco_res, 1, &cnl_tco_platform_data, 1588 sizeof(cnl_tco_platform_data)); 1589 } 1590 1591 static void i801_add_tco(struct i801_priv *priv) 1592 { 1593 struct pci_dev *pci_dev = priv->pci_dev; 1594 struct resource tco_res[2], *res; 1595 u32 tco_base, tco_ctl; 1596 1597 /* If we have ACPI based watchdog use that instead */ 1598 if (acpi_has_watchdog()) 1599 return; 1600 1601 if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL))) 1602 return; 1603 1604 pci_read_config_dword(pci_dev, TCOBASE, &tco_base); 1605 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl); 1606 if (!(tco_ctl & TCOCTL_EN)) 1607 return; 1608 1609 memset(tco_res, 0, sizeof(tco_res)); 1610 /* 1611 * Always populate the main iTCO IO resource here. The second entry 1612 * for NO_REBOOT MMIO is filled by the SPT specific function. 1613 */ 1614 res = &tco_res[0]; 1615 res->start = tco_base & ~1; 1616 res->end = res->start + 32 - 1; 1617 res->flags = IORESOURCE_IO; 1618 1619 if (priv->features & FEATURE_TCO_CNL) 1620 priv->tco_pdev = i801_add_tco_cnl(priv, pci_dev, tco_res); 1621 else 1622 priv->tco_pdev = i801_add_tco_spt(priv, pci_dev, tco_res); 1623 1624 if (IS_ERR(priv->tco_pdev)) 1625 dev_warn(&pci_dev->dev, "failed to create iTCO device\n"); 1626 } 1627 1628 #ifdef CONFIG_ACPI 1629 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv, 1630 acpi_physical_address address) 1631 { 1632 return address >= priv->smba && 1633 address <= pci_resource_end(priv->pci_dev, SMBBAR); 1634 } 1635 1636 static acpi_status 1637 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits, 1638 u64 *value, void *handler_context, void *region_context) 1639 { 1640 struct i801_priv *priv = handler_context; 1641 struct pci_dev *pdev = priv->pci_dev; 1642 acpi_status status; 1643 1644 /* 1645 * Once BIOS AML code touches the OpRegion we warn and inhibit any 1646 * further access from the driver itself. This device is now owned 1647 * by the system firmware. 1648 */ 1649 mutex_lock(&priv->acpi_lock); 1650 1651 if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) { 1652 priv->acpi_reserved = true; 1653 1654 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n"); 1655 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n"); 1656 1657 /* 1658 * BIOS is accessing the host controller so prevent it from 1659 * suspending automatically from now on. 1660 */ 1661 pm_runtime_get_sync(&pdev->dev); 1662 } 1663 1664 if ((function & ACPI_IO_MASK) == ACPI_READ) 1665 status = acpi_os_read_port(address, (u32 *)value, bits); 1666 else 1667 status = acpi_os_write_port(address, (u32)*value, bits); 1668 1669 mutex_unlock(&priv->acpi_lock); 1670 1671 return status; 1672 } 1673 1674 static int i801_acpi_probe(struct i801_priv *priv) 1675 { 1676 struct acpi_device *adev; 1677 acpi_status status; 1678 1679 adev = ACPI_COMPANION(&priv->pci_dev->dev); 1680 if (adev) { 1681 status = acpi_install_address_space_handler(adev->handle, 1682 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler, 1683 NULL, priv); 1684 if (ACPI_SUCCESS(status)) 1685 return 0; 1686 } 1687 1688 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]); 1689 } 1690 1691 static void i801_acpi_remove(struct i801_priv *priv) 1692 { 1693 struct acpi_device *adev; 1694 1695 adev = ACPI_COMPANION(&priv->pci_dev->dev); 1696 if (!adev) 1697 return; 1698 1699 acpi_remove_address_space_handler(adev->handle, 1700 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler); 1701 1702 mutex_lock(&priv->acpi_lock); 1703 if (priv->acpi_reserved) 1704 pm_runtime_put(&priv->pci_dev->dev); 1705 mutex_unlock(&priv->acpi_lock); 1706 } 1707 #else 1708 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; } 1709 static inline void i801_acpi_remove(struct i801_priv *priv) { } 1710 #endif 1711 1712 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id) 1713 { 1714 unsigned char temp; 1715 int err, i; 1716 struct i801_priv *priv; 1717 1718 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL); 1719 if (!priv) 1720 return -ENOMEM; 1721 1722 i2c_set_adapdata(&priv->adapter, priv); 1723 priv->adapter.owner = THIS_MODULE; 1724 priv->adapter.class = i801_get_adapter_class(priv); 1725 priv->adapter.algo = &smbus_algorithm; 1726 priv->adapter.dev.parent = &dev->dev; 1727 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev)); 1728 priv->adapter.retries = 3; 1729 mutex_init(&priv->acpi_lock); 1730 1731 priv->pci_dev = dev; 1732 switch (dev->device) { 1733 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS: 1734 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS: 1735 case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS: 1736 case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS: 1737 case PCI_DEVICE_ID_INTEL_DNV_SMBUS: 1738 case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS: 1739 case PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS: 1740 priv->features |= FEATURE_BLOCK_PROC; 1741 priv->features |= FEATURE_I2C_BLOCK_READ; 1742 priv->features |= FEATURE_IRQ; 1743 priv->features |= FEATURE_SMBUS_PEC; 1744 priv->features |= FEATURE_BLOCK_BUFFER; 1745 priv->features |= FEATURE_TCO_SPT; 1746 priv->features |= FEATURE_HOST_NOTIFY; 1747 break; 1748 1749 case PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS: 1750 case PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS: 1751 case PCI_DEVICE_ID_INTEL_CDF_SMBUS: 1752 case PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS: 1753 case PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS: 1754 case PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS: 1755 case PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS: 1756 case PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS: 1757 case PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS: 1758 case PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS: 1759 case PCI_DEVICE_ID_INTEL_EBG_SMBUS: 1760 priv->features |= FEATURE_BLOCK_PROC; 1761 priv->features |= FEATURE_I2C_BLOCK_READ; 1762 priv->features |= FEATURE_IRQ; 1763 priv->features |= FEATURE_SMBUS_PEC; 1764 priv->features |= FEATURE_BLOCK_BUFFER; 1765 priv->features |= FEATURE_TCO_CNL; 1766 priv->features |= FEATURE_HOST_NOTIFY; 1767 break; 1768 1769 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0: 1770 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1: 1771 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2: 1772 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0: 1773 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1: 1774 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2: 1775 priv->features |= FEATURE_IDF; 1776 fallthrough; 1777 default: 1778 priv->features |= FEATURE_BLOCK_PROC; 1779 priv->features |= FEATURE_I2C_BLOCK_READ; 1780 priv->features |= FEATURE_IRQ; 1781 fallthrough; 1782 case PCI_DEVICE_ID_INTEL_82801DB_3: 1783 priv->features |= FEATURE_SMBUS_PEC; 1784 priv->features |= FEATURE_BLOCK_BUFFER; 1785 fallthrough; 1786 case PCI_DEVICE_ID_INTEL_82801CA_3: 1787 priv->features |= FEATURE_HOST_NOTIFY; 1788 fallthrough; 1789 case PCI_DEVICE_ID_INTEL_82801BA_2: 1790 case PCI_DEVICE_ID_INTEL_82801AB_3: 1791 case PCI_DEVICE_ID_INTEL_82801AA_3: 1792 break; 1793 } 1794 1795 /* Disable features on user request */ 1796 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) { 1797 if (priv->features & disable_features & (1 << i)) 1798 dev_notice(&dev->dev, "%s disabled by user\n", 1799 i801_feature_names[i]); 1800 } 1801 priv->features &= ~disable_features; 1802 1803 err = pcim_enable_device(dev); 1804 if (err) { 1805 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", 1806 err); 1807 return err; 1808 } 1809 pcim_pin_device(dev); 1810 1811 /* Determine the address of the SMBus area */ 1812 priv->smba = pci_resource_start(dev, SMBBAR); 1813 if (!priv->smba) { 1814 dev_err(&dev->dev, 1815 "SMBus base address uninitialized, upgrade BIOS\n"); 1816 return -ENODEV; 1817 } 1818 1819 if (i801_acpi_probe(priv)) 1820 return -ENODEV; 1821 1822 err = pcim_iomap_regions(dev, 1 << SMBBAR, 1823 dev_driver_string(&dev->dev)); 1824 if (err) { 1825 dev_err(&dev->dev, 1826 "Failed to request SMBus region 0x%lx-0x%Lx\n", 1827 priv->smba, 1828 (unsigned long long)pci_resource_end(dev, SMBBAR)); 1829 i801_acpi_remove(priv); 1830 return err; 1831 } 1832 1833 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp); 1834 priv->original_hstcfg = temp; 1835 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ 1836 if (!(temp & SMBHSTCFG_HST_EN)) { 1837 dev_info(&dev->dev, "Enabling SMBus device\n"); 1838 temp |= SMBHSTCFG_HST_EN; 1839 } 1840 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp); 1841 1842 if (temp & SMBHSTCFG_SMB_SMI_EN) { 1843 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); 1844 /* Disable SMBus interrupt feature if SMBus using SMI# */ 1845 priv->features &= ~FEATURE_IRQ; 1846 } 1847 if (temp & SMBHSTCFG_SPD_WD) 1848 dev_info(&dev->dev, "SPD Write Disable is set\n"); 1849 1850 /* Clear special mode bits */ 1851 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) 1852 outb_p(inb_p(SMBAUXCTL(priv)) & 1853 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 1854 1855 /* Remember original Host Notify setting */ 1856 if (priv->features & FEATURE_HOST_NOTIFY) 1857 priv->original_slvcmd = inb_p(SMBSLVCMD(priv)); 1858 1859 /* Default timeout in interrupt mode: 200 ms */ 1860 priv->adapter.timeout = HZ / 5; 1861 1862 if (dev->irq == IRQ_NOTCONNECTED) 1863 priv->features &= ~FEATURE_IRQ; 1864 1865 if (priv->features & FEATURE_IRQ) { 1866 u16 pcictl, pcists; 1867 1868 /* Complain if an interrupt is already pending */ 1869 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); 1870 if (pcists & SMBPCISTS_INTS) 1871 dev_warn(&dev->dev, "An interrupt is pending!\n"); 1872 1873 /* Check if interrupts have been disabled */ 1874 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl); 1875 if (pcictl & SMBPCICTL_INTDIS) { 1876 dev_info(&dev->dev, "Interrupts are disabled\n"); 1877 priv->features &= ~FEATURE_IRQ; 1878 } 1879 } 1880 1881 if (priv->features & FEATURE_IRQ) { 1882 init_waitqueue_head(&priv->waitq); 1883 1884 err = devm_request_irq(&dev->dev, dev->irq, i801_isr, 1885 IRQF_SHARED, 1886 dev_driver_string(&dev->dev), priv); 1887 if (err) { 1888 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n", 1889 dev->irq, err); 1890 priv->features &= ~FEATURE_IRQ; 1891 } 1892 } 1893 dev_info(&dev->dev, "SMBus using %s\n", 1894 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling"); 1895 1896 i801_add_tco(priv); 1897 1898 snprintf(priv->adapter.name, sizeof(priv->adapter.name), 1899 "SMBus I801 adapter at %04lx", priv->smba); 1900 err = i2c_add_adapter(&priv->adapter); 1901 if (err) { 1902 i801_acpi_remove(priv); 1903 return err; 1904 } 1905 1906 i801_enable_host_notify(&priv->adapter); 1907 1908 i801_probe_optional_slaves(priv); 1909 /* We ignore errors - multiplexing is optional */ 1910 i801_add_mux(priv); 1911 1912 pci_set_drvdata(dev, priv); 1913 1914 pm_runtime_set_autosuspend_delay(&dev->dev, 1000); 1915 pm_runtime_use_autosuspend(&dev->dev); 1916 pm_runtime_put_autosuspend(&dev->dev); 1917 pm_runtime_allow(&dev->dev); 1918 1919 return 0; 1920 } 1921 1922 static void i801_remove(struct pci_dev *dev) 1923 { 1924 struct i801_priv *priv = pci_get_drvdata(dev); 1925 1926 pm_runtime_forbid(&dev->dev); 1927 pm_runtime_get_noresume(&dev->dev); 1928 1929 i801_disable_host_notify(priv); 1930 i801_del_mux(priv); 1931 i2c_del_adapter(&priv->adapter); 1932 i801_acpi_remove(priv); 1933 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); 1934 1935 platform_device_unregister(priv->tco_pdev); 1936 1937 /* 1938 * do not call pci_disable_device(dev) since it can cause hard hangs on 1939 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) 1940 */ 1941 } 1942 1943 static void i801_shutdown(struct pci_dev *dev) 1944 { 1945 struct i801_priv *priv = pci_get_drvdata(dev); 1946 1947 /* Restore config registers to avoid hard hang on some systems */ 1948 i801_disable_host_notify(priv); 1949 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); 1950 } 1951 1952 #ifdef CONFIG_PM_SLEEP 1953 static int i801_suspend(struct device *dev) 1954 { 1955 struct pci_dev *pci_dev = to_pci_dev(dev); 1956 struct i801_priv *priv = pci_get_drvdata(pci_dev); 1957 1958 pci_write_config_byte(pci_dev, SMBHSTCFG, priv->original_hstcfg); 1959 return 0; 1960 } 1961 1962 static int i801_resume(struct device *dev) 1963 { 1964 struct i801_priv *priv = dev_get_drvdata(dev); 1965 1966 i801_enable_host_notify(&priv->adapter); 1967 1968 return 0; 1969 } 1970 #endif 1971 1972 static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume); 1973 1974 static struct pci_driver i801_driver = { 1975 .name = "i801_smbus", 1976 .id_table = i801_ids, 1977 .probe = i801_probe, 1978 .remove = i801_remove, 1979 .shutdown = i801_shutdown, 1980 .driver = { 1981 .pm = &i801_pm_ops, 1982 }, 1983 }; 1984 1985 static int __init i2c_i801_init(void) 1986 { 1987 if (dmi_name_in_vendors("FUJITSU")) 1988 input_apanel_init(); 1989 return pci_register_driver(&i801_driver); 1990 } 1991 1992 static void __exit i2c_i801_exit(void) 1993 { 1994 pci_unregister_driver(&i801_driver); 1995 } 1996 1997 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>"); 1998 MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>"); 1999 MODULE_DESCRIPTION("I801 SMBus driver"); 2000 MODULE_LICENSE("GPL"); 2001 2002 module_init(i2c_i801_init); 2003 module_exit(i2c_i801_exit); 2004