1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, 4 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker 5 <mdsxyz123@yahoo.com> 6 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de> 7 Copyright (C) 2010 Intel Corporation, 8 David Woodhouse <dwmw2@infradead.org> 9 10 */ 11 12 /* 13 * Supports the following Intel I/O Controller Hubs (ICH): 14 * 15 * I/O Block I2C 16 * region SMBus Block proc. block 17 * Chip name PCI ID size PEC buffer call read 18 * --------------------------------------------------------------------------- 19 * 82801AA (ICH) 0x2413 16 no no no no 20 * 82801AB (ICH0) 0x2423 16 no no no no 21 * 82801BA (ICH2) 0x2443 16 no no no no 22 * 82801CA (ICH3) 0x2483 32 soft no no no 23 * 82801DB (ICH4) 0x24c3 32 hard yes no no 24 * 82801E (ICH5) 0x24d3 32 hard yes yes yes 25 * 6300ESB 0x25a4 32 hard yes yes yes 26 * 82801F (ICH6) 0x266a 32 hard yes yes yes 27 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes 28 * 82801G (ICH7) 0x27da 32 hard yes yes yes 29 * 82801H (ICH8) 0x283e 32 hard yes yes yes 30 * 82801I (ICH9) 0x2930 32 hard yes yes yes 31 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes 32 * ICH10 0x3a30 32 hard yes yes yes 33 * ICH10 0x3a60 32 hard yes yes yes 34 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes 35 * 6 Series (PCH) 0x1c22 32 hard yes yes yes 36 * Patsburg (PCH) 0x1d22 32 hard yes yes yes 37 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes 38 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes 39 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes 40 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes 41 * Panther Point (PCH) 0x1e22 32 hard yes yes yes 42 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes 43 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes 44 * Avoton (SOC) 0x1f3c 32 hard yes yes yes 45 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes 46 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes 47 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes 48 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes 49 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes 50 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes 51 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes 52 * BayTrail (SOC) 0x0f12 32 hard yes yes yes 53 * Braswell (SOC) 0x2292 32 hard yes yes yes 54 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes 55 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes 56 * DNV (SOC) 0x19df 32 hard yes yes yes 57 * Broxton (SOC) 0x5ad4 32 hard yes yes yes 58 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes 59 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes 60 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes 61 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes 62 * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes 63 * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes 64 * Cedar Fork (PCH) 0x18df 32 hard yes yes yes 65 * Ice Lake-LP (PCH) 0x34a3 32 hard yes yes yes 66 * Comet Lake (PCH) 0x02a3 32 hard yes yes yes 67 * Elkhart Lake (PCH) 0x4b23 32 hard yes yes yes 68 * Tiger Lake-LP (PCH) 0xa0a3 32 hard yes yes yes 69 * 70 * Features supported by this driver: 71 * Software PEC no 72 * Hardware PEC yes 73 * Block buffer yes 74 * Block process call transaction yes 75 * I2C block read transaction yes (doesn't use the block buffer) 76 * Slave mode no 77 * SMBus Host Notify yes 78 * Interrupt processing yes 79 * 80 * See the file Documentation/i2c/busses/i2c-i801 for details. 81 */ 82 83 #include <linux/interrupt.h> 84 #include <linux/module.h> 85 #include <linux/pci.h> 86 #include <linux/kernel.h> 87 #include <linux/stddef.h> 88 #include <linux/delay.h> 89 #include <linux/ioport.h> 90 #include <linux/init.h> 91 #include <linux/i2c.h> 92 #include <linux/i2c-smbus.h> 93 #include <linux/acpi.h> 94 #include <linux/io.h> 95 #include <linux/dmi.h> 96 #include <linux/slab.h> 97 #include <linux/string.h> 98 #include <linux/wait.h> 99 #include <linux/err.h> 100 #include <linux/platform_device.h> 101 #include <linux/platform_data/itco_wdt.h> 102 #include <linux/pm_runtime.h> 103 104 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 105 #include <linux/gpio/machine.h> 106 #include <linux/platform_data/i2c-mux-gpio.h> 107 #endif 108 109 /* I801 SMBus address offsets */ 110 #define SMBHSTSTS(p) (0 + (p)->smba) 111 #define SMBHSTCNT(p) (2 + (p)->smba) 112 #define SMBHSTCMD(p) (3 + (p)->smba) 113 #define SMBHSTADD(p) (4 + (p)->smba) 114 #define SMBHSTDAT0(p) (5 + (p)->smba) 115 #define SMBHSTDAT1(p) (6 + (p)->smba) 116 #define SMBBLKDAT(p) (7 + (p)->smba) 117 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */ 118 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */ 119 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */ 120 #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */ 121 #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */ 122 #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */ 123 124 /* PCI Address Constants */ 125 #define SMBBAR 4 126 #define SMBPCICTL 0x004 127 #define SMBPCISTS 0x006 128 #define SMBHSTCFG 0x040 129 #define TCOBASE 0x050 130 #define TCOCTL 0x054 131 132 #define ACPIBASE 0x040 133 #define ACPIBASE_SMI_OFF 0x030 134 #define ACPICTRL 0x044 135 #define ACPICTRL_EN 0x080 136 137 #define SBREG_BAR 0x10 138 #define SBREG_SMBCTRL 0xc6000c 139 #define SBREG_SMBCTRL_DNV 0xcf000c 140 141 /* Host status bits for SMBPCISTS */ 142 #define SMBPCISTS_INTS BIT(3) 143 144 /* Control bits for SMBPCICTL */ 145 #define SMBPCICTL_INTDIS BIT(10) 146 147 /* Host configuration bits for SMBHSTCFG */ 148 #define SMBHSTCFG_HST_EN BIT(0) 149 #define SMBHSTCFG_SMB_SMI_EN BIT(1) 150 #define SMBHSTCFG_I2C_EN BIT(2) 151 #define SMBHSTCFG_SPD_WD BIT(4) 152 153 /* TCO configuration bits for TCOCTL */ 154 #define TCOCTL_EN BIT(8) 155 156 /* Auxiliary status register bits, ICH4+ only */ 157 #define SMBAUXSTS_CRCE BIT(0) 158 #define SMBAUXSTS_STCO BIT(1) 159 160 /* Auxiliary control register bits, ICH4+ only */ 161 #define SMBAUXCTL_CRC BIT(0) 162 #define SMBAUXCTL_E32B BIT(1) 163 164 /* Other settings */ 165 #define MAX_RETRIES 400 166 167 /* I801 command constants */ 168 #define I801_QUICK 0x00 169 #define I801_BYTE 0x04 170 #define I801_BYTE_DATA 0x08 171 #define I801_WORD_DATA 0x0C 172 #define I801_PROC_CALL 0x10 /* unimplemented */ 173 #define I801_BLOCK_DATA 0x14 174 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ 175 #define I801_BLOCK_PROC_CALL 0x1C 176 177 /* I801 Host Control register bits */ 178 #define SMBHSTCNT_INTREN BIT(0) 179 #define SMBHSTCNT_KILL BIT(1) 180 #define SMBHSTCNT_LAST_BYTE BIT(5) 181 #define SMBHSTCNT_START BIT(6) 182 #define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */ 183 184 /* I801 Hosts Status register bits */ 185 #define SMBHSTSTS_BYTE_DONE BIT(7) 186 #define SMBHSTSTS_INUSE_STS BIT(6) 187 #define SMBHSTSTS_SMBALERT_STS BIT(5) 188 #define SMBHSTSTS_FAILED BIT(4) 189 #define SMBHSTSTS_BUS_ERR BIT(3) 190 #define SMBHSTSTS_DEV_ERR BIT(2) 191 #define SMBHSTSTS_INTR BIT(1) 192 #define SMBHSTSTS_HOST_BUSY BIT(0) 193 194 /* Host Notify Status register bits */ 195 #define SMBSLVSTS_HST_NTFY_STS BIT(0) 196 197 /* Host Notify Command register bits */ 198 #define SMBSLVCMD_HST_NTFY_INTREN BIT(0) 199 200 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \ 201 SMBHSTSTS_DEV_ERR) 202 203 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \ 204 STATUS_ERROR_FLAGS) 205 206 /* Older devices have their ID defined in <linux/pci_ids.h> */ 207 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS 0x02a3 208 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12 209 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df 210 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df 211 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 212 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 213 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */ 214 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70 215 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71 216 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72 217 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 218 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c 219 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292 220 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 221 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0 222 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4 223 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS 0x34a3 224 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 225 #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS 0x4b23 226 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4 227 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 228 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2 229 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22 230 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d 231 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e 232 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f 233 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22 234 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2 235 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23 236 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3 237 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS 0xa0a3 238 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123 239 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3 240 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223 241 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3 242 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323 243 244 struct i801_mux_config { 245 char *gpio_chip; 246 unsigned values[3]; 247 int n_values; 248 unsigned classes[3]; 249 unsigned gpios[2]; /* Relative to gpio_chip->base */ 250 int n_gpios; 251 }; 252 253 struct i801_priv { 254 struct i2c_adapter adapter; 255 unsigned long smba; 256 unsigned char original_hstcfg; 257 unsigned char original_slvcmd; 258 struct pci_dev *pci_dev; 259 unsigned int features; 260 261 /* isr processing */ 262 wait_queue_head_t waitq; 263 u8 status; 264 265 /* Command state used by isr for byte-by-byte block transactions */ 266 u8 cmd; 267 bool is_read; 268 int count; 269 int len; 270 u8 *data; 271 272 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 273 const struct i801_mux_config *mux_drvdata; 274 struct platform_device *mux_pdev; 275 struct gpiod_lookup_table *lookup; 276 #endif 277 struct platform_device *tco_pdev; 278 279 /* 280 * If set to true the host controller registers are reserved for 281 * ACPI AML use. Protected by acpi_lock. 282 */ 283 bool acpi_reserved; 284 struct mutex acpi_lock; 285 }; 286 287 #define FEATURE_SMBUS_PEC BIT(0) 288 #define FEATURE_BLOCK_BUFFER BIT(1) 289 #define FEATURE_BLOCK_PROC BIT(2) 290 #define FEATURE_I2C_BLOCK_READ BIT(3) 291 #define FEATURE_IRQ BIT(4) 292 #define FEATURE_HOST_NOTIFY BIT(5) 293 /* Not really a feature, but it's convenient to handle it as such */ 294 #define FEATURE_IDF BIT(15) 295 #define FEATURE_TCO BIT(16) 296 297 static const char *i801_feature_names[] = { 298 "SMBus PEC", 299 "Block buffer", 300 "Block process call", 301 "I2C block read", 302 "Interrupt", 303 "SMBus Host Notify", 304 }; 305 306 static unsigned int disable_features; 307 module_param(disable_features, uint, S_IRUGO | S_IWUSR); 308 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n" 309 "\t\t 0x01 disable SMBus PEC\n" 310 "\t\t 0x02 disable the block buffer\n" 311 "\t\t 0x08 disable the I2C block read functionality\n" 312 "\t\t 0x10 don't use interrupts\n" 313 "\t\t 0x20 disable SMBus Host Notify "); 314 315 /* Make sure the SMBus host is ready to start transmitting. 316 Return 0 if it is, -EBUSY if it is not. */ 317 static int i801_check_pre(struct i801_priv *priv) 318 { 319 int status; 320 321 status = inb_p(SMBHSTSTS(priv)); 322 if (status & SMBHSTSTS_HOST_BUSY) { 323 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n"); 324 return -EBUSY; 325 } 326 327 status &= STATUS_FLAGS; 328 if (status) { 329 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n", 330 status); 331 outb_p(status, SMBHSTSTS(priv)); 332 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS; 333 if (status) { 334 dev_err(&priv->pci_dev->dev, 335 "Failed clearing status flags (%02x)\n", 336 status); 337 return -EBUSY; 338 } 339 } 340 341 /* 342 * Clear CRC status if needed. 343 * During normal operation, i801_check_post() takes care 344 * of it after every operation. We do it here only in case 345 * the hardware was already in this state when the driver 346 * started. 347 */ 348 if (priv->features & FEATURE_SMBUS_PEC) { 349 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE; 350 if (status) { 351 dev_dbg(&priv->pci_dev->dev, 352 "Clearing aux status flags (%02x)\n", status); 353 outb_p(status, SMBAUXSTS(priv)); 354 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE; 355 if (status) { 356 dev_err(&priv->pci_dev->dev, 357 "Failed clearing aux status flags (%02x)\n", 358 status); 359 return -EBUSY; 360 } 361 } 362 } 363 364 return 0; 365 } 366 367 /* 368 * Convert the status register to an error code, and clear it. 369 * Note that status only contains the bits we want to clear, not the 370 * actual register value. 371 */ 372 static int i801_check_post(struct i801_priv *priv, int status) 373 { 374 int result = 0; 375 376 /* 377 * If the SMBus is still busy, we give up 378 * Note: This timeout condition only happens when using polling 379 * transactions. For interrupt operation, NAK/timeout is indicated by 380 * DEV_ERR. 381 */ 382 if (unlikely(status < 0)) { 383 dev_err(&priv->pci_dev->dev, "Transaction timeout\n"); 384 /* try to stop the current command */ 385 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n"); 386 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL, 387 SMBHSTCNT(priv)); 388 usleep_range(1000, 2000); 389 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL), 390 SMBHSTCNT(priv)); 391 392 /* Check if it worked */ 393 status = inb_p(SMBHSTSTS(priv)); 394 if ((status & SMBHSTSTS_HOST_BUSY) || 395 !(status & SMBHSTSTS_FAILED)) 396 dev_err(&priv->pci_dev->dev, 397 "Failed terminating the transaction\n"); 398 outb_p(STATUS_FLAGS, SMBHSTSTS(priv)); 399 return -ETIMEDOUT; 400 } 401 402 if (status & SMBHSTSTS_FAILED) { 403 result = -EIO; 404 dev_err(&priv->pci_dev->dev, "Transaction failed\n"); 405 } 406 if (status & SMBHSTSTS_DEV_ERR) { 407 /* 408 * This may be a PEC error, check and clear it. 409 * 410 * AUXSTS is handled differently from HSTSTS. 411 * For HSTSTS, i801_isr() or i801_wait_intr() 412 * has already cleared the error bits in hardware, 413 * and we are passed a copy of the original value 414 * in "status". 415 * For AUXSTS, the hardware register is left 416 * for us to handle here. 417 * This is asymmetric, slightly iffy, but safe, 418 * since all this code is serialized and the CRCE 419 * bit is harmless as long as it's cleared before 420 * the next operation. 421 */ 422 if ((priv->features & FEATURE_SMBUS_PEC) && 423 (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) { 424 outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv)); 425 result = -EBADMSG; 426 dev_dbg(&priv->pci_dev->dev, "PEC error\n"); 427 } else { 428 result = -ENXIO; 429 dev_dbg(&priv->pci_dev->dev, "No response\n"); 430 } 431 } 432 if (status & SMBHSTSTS_BUS_ERR) { 433 result = -EAGAIN; 434 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n"); 435 } 436 437 /* Clear status flags except BYTE_DONE, to be cleared by caller */ 438 outb_p(status, SMBHSTSTS(priv)); 439 440 return result; 441 } 442 443 /* Wait for BUSY being cleared and either INTR or an error flag being set */ 444 static int i801_wait_intr(struct i801_priv *priv) 445 { 446 int timeout = 0; 447 int status; 448 449 /* We will always wait for a fraction of a second! */ 450 do { 451 usleep_range(250, 500); 452 status = inb_p(SMBHSTSTS(priv)); 453 } while (((status & SMBHSTSTS_HOST_BUSY) || 454 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) && 455 (timeout++ < MAX_RETRIES)); 456 457 if (timeout > MAX_RETRIES) { 458 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n"); 459 return -ETIMEDOUT; 460 } 461 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR); 462 } 463 464 /* Wait for either BYTE_DONE or an error flag being set */ 465 static int i801_wait_byte_done(struct i801_priv *priv) 466 { 467 int timeout = 0; 468 int status; 469 470 /* We will always wait for a fraction of a second! */ 471 do { 472 usleep_range(250, 500); 473 status = inb_p(SMBHSTSTS(priv)); 474 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) && 475 (timeout++ < MAX_RETRIES)); 476 477 if (timeout > MAX_RETRIES) { 478 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n"); 479 return -ETIMEDOUT; 480 } 481 return status & STATUS_ERROR_FLAGS; 482 } 483 484 static int i801_transaction(struct i801_priv *priv, int xact) 485 { 486 int status; 487 int result; 488 const struct i2c_adapter *adap = &priv->adapter; 489 490 result = i801_check_pre(priv); 491 if (result < 0) 492 return result; 493 494 if (priv->features & FEATURE_IRQ) { 495 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START, 496 SMBHSTCNT(priv)); 497 result = wait_event_timeout(priv->waitq, 498 (status = priv->status), 499 adap->timeout); 500 if (!result) { 501 status = -ETIMEDOUT; 502 dev_warn(&priv->pci_dev->dev, 503 "Timeout waiting for interrupt!\n"); 504 } 505 priv->status = 0; 506 return i801_check_post(priv, status); 507 } 508 509 /* the current contents of SMBHSTCNT can be overwritten, since PEC, 510 * SMBSCMD are passed in xact */ 511 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv)); 512 513 status = i801_wait_intr(priv); 514 return i801_check_post(priv, status); 515 } 516 517 static int i801_block_transaction_by_block(struct i801_priv *priv, 518 union i2c_smbus_data *data, 519 char read_write, int command, 520 int hwpec) 521 { 522 int i, len; 523 int status; 524 int xact = hwpec ? SMBHSTCNT_PEC_EN : 0; 525 526 switch (command) { 527 case I2C_SMBUS_BLOCK_PROC_CALL: 528 xact |= I801_BLOCK_PROC_CALL; 529 break; 530 case I2C_SMBUS_BLOCK_DATA: 531 xact |= I801_BLOCK_DATA; 532 break; 533 default: 534 return -EOPNOTSUPP; 535 } 536 537 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ 538 539 /* Use 32-byte buffer to process this transaction */ 540 if (read_write == I2C_SMBUS_WRITE) { 541 len = data->block[0]; 542 outb_p(len, SMBHSTDAT0(priv)); 543 for (i = 0; i < len; i++) 544 outb_p(data->block[i+1], SMBBLKDAT(priv)); 545 } 546 547 status = i801_transaction(priv, xact); 548 if (status) 549 return status; 550 551 if (read_write == I2C_SMBUS_READ || 552 command == I2C_SMBUS_BLOCK_PROC_CALL) { 553 len = inb_p(SMBHSTDAT0(priv)); 554 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) 555 return -EPROTO; 556 557 data->block[0] = len; 558 for (i = 0; i < len; i++) 559 data->block[i + 1] = inb_p(SMBBLKDAT(priv)); 560 } 561 return 0; 562 } 563 564 static void i801_isr_byte_done(struct i801_priv *priv) 565 { 566 if (priv->is_read) { 567 /* For SMBus block reads, length is received with first byte */ 568 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) && 569 (priv->count == 0)) { 570 priv->len = inb_p(SMBHSTDAT0(priv)); 571 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) { 572 dev_err(&priv->pci_dev->dev, 573 "Illegal SMBus block read size %d\n", 574 priv->len); 575 /* FIXME: Recover */ 576 priv->len = I2C_SMBUS_BLOCK_MAX; 577 } else { 578 dev_dbg(&priv->pci_dev->dev, 579 "SMBus block read size is %d\n", 580 priv->len); 581 } 582 priv->data[-1] = priv->len; 583 } 584 585 /* Read next byte */ 586 if (priv->count < priv->len) 587 priv->data[priv->count++] = inb(SMBBLKDAT(priv)); 588 else 589 dev_dbg(&priv->pci_dev->dev, 590 "Discarding extra byte on block read\n"); 591 592 /* Set LAST_BYTE for last byte of read transaction */ 593 if (priv->count == priv->len - 1) 594 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE, 595 SMBHSTCNT(priv)); 596 } else if (priv->count < priv->len - 1) { 597 /* Write next byte, except for IRQ after last byte */ 598 outb_p(priv->data[++priv->count], SMBBLKDAT(priv)); 599 } 600 601 /* Clear BYTE_DONE to continue with next byte */ 602 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 603 } 604 605 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv) 606 { 607 unsigned short addr; 608 609 addr = inb_p(SMBNTFDADD(priv)) >> 1; 610 611 /* 612 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba) 613 * always returns 0. Our current implementation doesn't provide 614 * data, so we just ignore it. 615 */ 616 i2c_handle_smbus_host_notify(&priv->adapter, addr); 617 618 /* clear Host Notify bit and return */ 619 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 620 return IRQ_HANDLED; 621 } 622 623 /* 624 * There are three kinds of interrupts: 625 * 626 * 1) i801 signals transaction completion with one of these interrupts: 627 * INTR - Success 628 * DEV_ERR - Invalid command, NAK or communication timeout 629 * BUS_ERR - SMI# transaction collision 630 * FAILED - transaction was canceled due to a KILL request 631 * When any of these occur, update ->status and wake up the waitq. 632 * ->status must be cleared before kicking off the next transaction. 633 * 634 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt 635 * occurs for each byte of a byte-by-byte to prepare the next byte. 636 * 637 * 3) Host Notify interrupts 638 */ 639 static irqreturn_t i801_isr(int irq, void *dev_id) 640 { 641 struct i801_priv *priv = dev_id; 642 u16 pcists; 643 u8 status; 644 645 /* Confirm this is our interrupt */ 646 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); 647 if (!(pcists & SMBPCISTS_INTS)) 648 return IRQ_NONE; 649 650 if (priv->features & FEATURE_HOST_NOTIFY) { 651 status = inb_p(SMBSLVSTS(priv)); 652 if (status & SMBSLVSTS_HST_NTFY_STS) 653 return i801_host_notify_isr(priv); 654 } 655 656 status = inb_p(SMBHSTSTS(priv)); 657 if (status & SMBHSTSTS_BYTE_DONE) 658 i801_isr_byte_done(priv); 659 660 /* 661 * Clear irq sources and report transaction result. 662 * ->status must be cleared before the next transaction is started. 663 */ 664 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS; 665 if (status) { 666 outb_p(status, SMBHSTSTS(priv)); 667 priv->status = status; 668 wake_up(&priv->waitq); 669 } 670 671 return IRQ_HANDLED; 672 } 673 674 /* 675 * For "byte-by-byte" block transactions: 676 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1 677 * I2C read uses cmd=I801_I2C_BLOCK_DATA 678 */ 679 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, 680 union i2c_smbus_data *data, 681 char read_write, int command, 682 int hwpec) 683 { 684 int i, len; 685 int smbcmd; 686 int status; 687 int result; 688 const struct i2c_adapter *adap = &priv->adapter; 689 690 if (command == I2C_SMBUS_BLOCK_PROC_CALL) 691 return -EOPNOTSUPP; 692 693 result = i801_check_pre(priv); 694 if (result < 0) 695 return result; 696 697 len = data->block[0]; 698 699 if (read_write == I2C_SMBUS_WRITE) { 700 outb_p(len, SMBHSTDAT0(priv)); 701 outb_p(data->block[1], SMBBLKDAT(priv)); 702 } 703 704 if (command == I2C_SMBUS_I2C_BLOCK_DATA && 705 read_write == I2C_SMBUS_READ) 706 smbcmd = I801_I2C_BLOCK_DATA; 707 else 708 smbcmd = I801_BLOCK_DATA; 709 710 if (priv->features & FEATURE_IRQ) { 711 priv->is_read = (read_write == I2C_SMBUS_READ); 712 if (len == 1 && priv->is_read) 713 smbcmd |= SMBHSTCNT_LAST_BYTE; 714 priv->cmd = smbcmd | SMBHSTCNT_INTREN; 715 priv->len = len; 716 priv->count = 0; 717 priv->data = &data->block[1]; 718 719 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv)); 720 result = wait_event_timeout(priv->waitq, 721 (status = priv->status), 722 adap->timeout); 723 if (!result) { 724 status = -ETIMEDOUT; 725 dev_warn(&priv->pci_dev->dev, 726 "Timeout waiting for interrupt!\n"); 727 } 728 priv->status = 0; 729 return i801_check_post(priv, status); 730 } 731 732 for (i = 1; i <= len; i++) { 733 if (i == len && read_write == I2C_SMBUS_READ) 734 smbcmd |= SMBHSTCNT_LAST_BYTE; 735 outb_p(smbcmd, SMBHSTCNT(priv)); 736 737 if (i == 1) 738 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START, 739 SMBHSTCNT(priv)); 740 741 status = i801_wait_byte_done(priv); 742 if (status) 743 goto exit; 744 745 if (i == 1 && read_write == I2C_SMBUS_READ 746 && command != I2C_SMBUS_I2C_BLOCK_DATA) { 747 len = inb_p(SMBHSTDAT0(priv)); 748 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { 749 dev_err(&priv->pci_dev->dev, 750 "Illegal SMBus block read size %d\n", 751 len); 752 /* Recover */ 753 while (inb_p(SMBHSTSTS(priv)) & 754 SMBHSTSTS_HOST_BUSY) 755 outb_p(SMBHSTSTS_BYTE_DONE, 756 SMBHSTSTS(priv)); 757 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); 758 return -EPROTO; 759 } 760 data->block[0] = len; 761 } 762 763 /* Retrieve/store value in SMBBLKDAT */ 764 if (read_write == I2C_SMBUS_READ) 765 data->block[i] = inb_p(SMBBLKDAT(priv)); 766 if (read_write == I2C_SMBUS_WRITE && i+1 <= len) 767 outb_p(data->block[i+1], SMBBLKDAT(priv)); 768 769 /* signals SMBBLKDAT ready */ 770 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 771 } 772 773 status = i801_wait_intr(priv); 774 exit: 775 return i801_check_post(priv, status); 776 } 777 778 static int i801_set_block_buffer_mode(struct i801_priv *priv) 779 { 780 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv)); 781 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0) 782 return -EIO; 783 return 0; 784 } 785 786 /* Block transaction function */ 787 static int i801_block_transaction(struct i801_priv *priv, 788 union i2c_smbus_data *data, char read_write, 789 int command, int hwpec) 790 { 791 int result = 0; 792 unsigned char hostc; 793 794 if (command == I2C_SMBUS_I2C_BLOCK_DATA) { 795 if (read_write == I2C_SMBUS_WRITE) { 796 /* set I2C_EN bit in configuration register */ 797 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc); 798 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, 799 hostc | SMBHSTCFG_I2C_EN); 800 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) { 801 dev_err(&priv->pci_dev->dev, 802 "I2C block read is unsupported!\n"); 803 return -EOPNOTSUPP; 804 } 805 } 806 807 if (read_write == I2C_SMBUS_WRITE 808 || command == I2C_SMBUS_I2C_BLOCK_DATA) { 809 if (data->block[0] < 1) 810 data->block[0] = 1; 811 if (data->block[0] > I2C_SMBUS_BLOCK_MAX) 812 data->block[0] = I2C_SMBUS_BLOCK_MAX; 813 } else { 814 data->block[0] = 32; /* max for SMBus block reads */ 815 } 816 817 /* Experience has shown that the block buffer can only be used for 818 SMBus (not I2C) block transactions, even though the datasheet 819 doesn't mention this limitation. */ 820 if ((priv->features & FEATURE_BLOCK_BUFFER) 821 && command != I2C_SMBUS_I2C_BLOCK_DATA 822 && i801_set_block_buffer_mode(priv) == 0) 823 result = i801_block_transaction_by_block(priv, data, 824 read_write, 825 command, hwpec); 826 else 827 result = i801_block_transaction_byte_by_byte(priv, data, 828 read_write, 829 command, hwpec); 830 831 if (command == I2C_SMBUS_I2C_BLOCK_DATA 832 && read_write == I2C_SMBUS_WRITE) { 833 /* restore saved configuration register value */ 834 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc); 835 } 836 return result; 837 } 838 839 /* Return negative errno on error. */ 840 static s32 i801_access(struct i2c_adapter *adap, u16 addr, 841 unsigned short flags, char read_write, u8 command, 842 int size, union i2c_smbus_data *data) 843 { 844 int hwpec; 845 int block = 0; 846 int ret = 0, xact = 0; 847 struct i801_priv *priv = i2c_get_adapdata(adap); 848 849 mutex_lock(&priv->acpi_lock); 850 if (priv->acpi_reserved) { 851 mutex_unlock(&priv->acpi_lock); 852 return -EBUSY; 853 } 854 855 pm_runtime_get_sync(&priv->pci_dev->dev); 856 857 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) 858 && size != I2C_SMBUS_QUICK 859 && size != I2C_SMBUS_I2C_BLOCK_DATA; 860 861 switch (size) { 862 case I2C_SMBUS_QUICK: 863 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 864 SMBHSTADD(priv)); 865 xact = I801_QUICK; 866 break; 867 case I2C_SMBUS_BYTE: 868 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 869 SMBHSTADD(priv)); 870 if (read_write == I2C_SMBUS_WRITE) 871 outb_p(command, SMBHSTCMD(priv)); 872 xact = I801_BYTE; 873 break; 874 case I2C_SMBUS_BYTE_DATA: 875 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 876 SMBHSTADD(priv)); 877 outb_p(command, SMBHSTCMD(priv)); 878 if (read_write == I2C_SMBUS_WRITE) 879 outb_p(data->byte, SMBHSTDAT0(priv)); 880 xact = I801_BYTE_DATA; 881 break; 882 case I2C_SMBUS_WORD_DATA: 883 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 884 SMBHSTADD(priv)); 885 outb_p(command, SMBHSTCMD(priv)); 886 if (read_write == I2C_SMBUS_WRITE) { 887 outb_p(data->word & 0xff, SMBHSTDAT0(priv)); 888 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); 889 } 890 xact = I801_WORD_DATA; 891 break; 892 case I2C_SMBUS_BLOCK_DATA: 893 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 894 SMBHSTADD(priv)); 895 outb_p(command, SMBHSTCMD(priv)); 896 block = 1; 897 break; 898 case I2C_SMBUS_I2C_BLOCK_DATA: 899 /* 900 * NB: page 240 of ICH5 datasheet shows that the R/#W 901 * bit should be cleared here, even when reading. 902 * However if SPD Write Disable is set (Lynx Point and later), 903 * the read will fail if we don't set the R/#W bit. 904 */ 905 outb_p(((addr & 0x7f) << 1) | 906 ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ? 907 (read_write & 0x01) : 0), 908 SMBHSTADD(priv)); 909 if (read_write == I2C_SMBUS_READ) { 910 /* NB: page 240 of ICH5 datasheet also shows 911 * that DATA1 is the cmd field when reading */ 912 outb_p(command, SMBHSTDAT1(priv)); 913 } else 914 outb_p(command, SMBHSTCMD(priv)); 915 block = 1; 916 break; 917 case I2C_SMBUS_BLOCK_PROC_CALL: 918 /* 919 * Bit 0 of the slave address register always indicate a write 920 * command. 921 */ 922 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv)); 923 outb_p(command, SMBHSTCMD(priv)); 924 block = 1; 925 break; 926 default: 927 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n", 928 size); 929 ret = -EOPNOTSUPP; 930 goto out; 931 } 932 933 if (hwpec) /* enable/disable hardware PEC */ 934 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv)); 935 else 936 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC), 937 SMBAUXCTL(priv)); 938 939 if (block) 940 ret = i801_block_transaction(priv, data, read_write, size, 941 hwpec); 942 else 943 ret = i801_transaction(priv, xact); 944 945 /* Some BIOSes don't like it when PEC is enabled at reboot or resume 946 time, so we forcibly disable it after every transaction. Turn off 947 E32B for the same reason. */ 948 if (hwpec || block) 949 outb_p(inb_p(SMBAUXCTL(priv)) & 950 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 951 952 if (block) 953 goto out; 954 if (ret) 955 goto out; 956 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK)) 957 goto out; 958 959 switch (xact & 0x7f) { 960 case I801_BYTE: /* Result put in SMBHSTDAT0 */ 961 case I801_BYTE_DATA: 962 data->byte = inb_p(SMBHSTDAT0(priv)); 963 break; 964 case I801_WORD_DATA: 965 data->word = inb_p(SMBHSTDAT0(priv)) + 966 (inb_p(SMBHSTDAT1(priv)) << 8); 967 break; 968 } 969 970 out: 971 pm_runtime_mark_last_busy(&priv->pci_dev->dev); 972 pm_runtime_put_autosuspend(&priv->pci_dev->dev); 973 mutex_unlock(&priv->acpi_lock); 974 return ret; 975 } 976 977 978 static u32 i801_func(struct i2c_adapter *adapter) 979 { 980 struct i801_priv *priv = i2c_get_adapdata(adapter); 981 982 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 983 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 984 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | 985 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | 986 ((priv->features & FEATURE_BLOCK_PROC) ? 987 I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) | 988 ((priv->features & FEATURE_I2C_BLOCK_READ) ? 989 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) | 990 ((priv->features & FEATURE_HOST_NOTIFY) ? 991 I2C_FUNC_SMBUS_HOST_NOTIFY : 0); 992 } 993 994 static void i801_enable_host_notify(struct i2c_adapter *adapter) 995 { 996 struct i801_priv *priv = i2c_get_adapdata(adapter); 997 998 if (!(priv->features & FEATURE_HOST_NOTIFY)) 999 return; 1000 1001 if (!(SMBSLVCMD_HST_NTFY_INTREN & priv->original_slvcmd)) 1002 outb_p(SMBSLVCMD_HST_NTFY_INTREN | priv->original_slvcmd, 1003 SMBSLVCMD(priv)); 1004 1005 /* clear Host Notify bit to allow a new notification */ 1006 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 1007 } 1008 1009 static void i801_disable_host_notify(struct i801_priv *priv) 1010 { 1011 if (!(priv->features & FEATURE_HOST_NOTIFY)) 1012 return; 1013 1014 outb_p(priv->original_slvcmd, SMBSLVCMD(priv)); 1015 } 1016 1017 static const struct i2c_algorithm smbus_algorithm = { 1018 .smbus_xfer = i801_access, 1019 .functionality = i801_func, 1020 }; 1021 1022 static const struct pci_device_id i801_ids[] = { 1023 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) }, 1024 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) }, 1025 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) }, 1026 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) }, 1027 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) }, 1028 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) }, 1029 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) }, 1030 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) }, 1031 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) }, 1032 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) }, 1033 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) }, 1034 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) }, 1035 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) }, 1036 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) }, 1037 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) }, 1038 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) }, 1039 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) }, 1040 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) }, 1041 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) }, 1042 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) }, 1043 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) }, 1044 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) }, 1045 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) }, 1046 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) }, 1047 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) }, 1048 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) }, 1049 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) }, 1050 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) }, 1051 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) }, 1052 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) }, 1053 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) }, 1054 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS) }, 1055 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) }, 1056 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) }, 1057 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) }, 1058 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) }, 1059 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) }, 1060 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) }, 1061 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMBUS) }, 1062 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) }, 1063 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) }, 1064 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) }, 1065 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) }, 1066 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) }, 1067 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS) }, 1068 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS) }, 1069 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS) }, 1070 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS) }, 1071 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS) }, 1072 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS) }, 1073 { 0, } 1074 }; 1075 1076 MODULE_DEVICE_TABLE(pci, i801_ids); 1077 1078 #if defined CONFIG_X86 && defined CONFIG_DMI 1079 static unsigned char apanel_addr; 1080 1081 /* Scan the system ROM for the signature "FJKEYINF" */ 1082 static __init const void __iomem *bios_signature(const void __iomem *bios) 1083 { 1084 ssize_t offset; 1085 const unsigned char signature[] = "FJKEYINF"; 1086 1087 for (offset = 0; offset < 0x10000; offset += 0x10) { 1088 if (check_signature(bios + offset, signature, 1089 sizeof(signature)-1)) 1090 return bios + offset; 1091 } 1092 return NULL; 1093 } 1094 1095 static void __init input_apanel_init(void) 1096 { 1097 void __iomem *bios; 1098 const void __iomem *p; 1099 1100 bios = ioremap(0xF0000, 0x10000); /* Can't fail */ 1101 p = bios_signature(bios); 1102 if (p) { 1103 /* just use the first address */ 1104 apanel_addr = readb(p + 8 + 3) >> 1; 1105 } 1106 iounmap(bios); 1107 } 1108 1109 struct dmi_onboard_device_info { 1110 const char *name; 1111 u8 type; 1112 unsigned short i2c_addr; 1113 const char *i2c_type; 1114 }; 1115 1116 static const struct dmi_onboard_device_info dmi_devices[] = { 1117 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" }, 1118 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" }, 1119 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" }, 1120 }; 1121 1122 static void dmi_check_onboard_device(u8 type, const char *name, 1123 struct i2c_adapter *adap) 1124 { 1125 int i; 1126 struct i2c_board_info info; 1127 1128 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) { 1129 /* & ~0x80, ignore enabled/disabled bit */ 1130 if ((type & ~0x80) != dmi_devices[i].type) 1131 continue; 1132 if (strcasecmp(name, dmi_devices[i].name)) 1133 continue; 1134 1135 memset(&info, 0, sizeof(struct i2c_board_info)); 1136 info.addr = dmi_devices[i].i2c_addr; 1137 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); 1138 i2c_new_device(adap, &info); 1139 break; 1140 } 1141 } 1142 1143 /* We use our own function to check for onboard devices instead of 1144 dmi_find_device() as some buggy BIOS's have the devices we are interested 1145 in marked as disabled */ 1146 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap) 1147 { 1148 int i, count; 1149 1150 if (dm->type != 10) 1151 return; 1152 1153 count = (dm->length - sizeof(struct dmi_header)) / 2; 1154 for (i = 0; i < count; i++) { 1155 const u8 *d = (char *)(dm + 1) + (i * 2); 1156 const char *name = ((char *) dm) + dm->length; 1157 u8 type = d[0]; 1158 u8 s = d[1]; 1159 1160 if (!s) 1161 continue; 1162 s--; 1163 while (s > 0 && name[0]) { 1164 name += strlen(name) + 1; 1165 s--; 1166 } 1167 if (name[0] == 0) /* Bogus string reference */ 1168 continue; 1169 1170 dmi_check_onboard_device(type, name, adap); 1171 } 1172 } 1173 1174 /* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */ 1175 static const char *const acpi_smo8800_ids[] = { 1176 "SMO8800", 1177 "SMO8801", 1178 "SMO8810", 1179 "SMO8811", 1180 "SMO8820", 1181 "SMO8821", 1182 "SMO8830", 1183 "SMO8831", 1184 }; 1185 1186 static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle, 1187 u32 nesting_level, 1188 void *context, 1189 void **return_value) 1190 { 1191 struct acpi_device_info *info; 1192 acpi_status status; 1193 char *hid; 1194 int i; 1195 1196 status = acpi_get_object_info(obj_handle, &info); 1197 if (!ACPI_SUCCESS(status) || !(info->valid & ACPI_VALID_HID)) 1198 return AE_OK; 1199 1200 hid = info->hardware_id.string; 1201 if (!hid) 1202 return AE_OK; 1203 1204 i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid); 1205 if (i < 0) 1206 return AE_OK; 1207 1208 *((bool *)return_value) = true; 1209 return AE_CTRL_TERMINATE; 1210 } 1211 1212 static bool is_dell_system_with_lis3lv02d(void) 1213 { 1214 bool found; 1215 const char *vendor; 1216 1217 vendor = dmi_get_system_info(DMI_SYS_VENDOR); 1218 if (!vendor || strcmp(vendor, "Dell Inc.")) 1219 return false; 1220 1221 /* 1222 * Check that ACPI device SMO88xx is present and is functioning. 1223 * Function acpi_get_devices() already filters all ACPI devices 1224 * which are not present or are not functioning. 1225 * ACPI device SMO88xx represents our ST microelectronics lis3lv02d 1226 * accelerometer but unfortunately ACPI does not provide any other 1227 * information (like I2C address). 1228 */ 1229 found = false; 1230 acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL, 1231 (void **)&found); 1232 1233 return found; 1234 } 1235 1236 /* 1237 * Accelerometer's I2C address is not specified in DMI nor ACPI, 1238 * so it is needed to define mapping table based on DMI product names. 1239 */ 1240 static const struct { 1241 const char *dmi_product_name; 1242 unsigned short i2c_addr; 1243 } dell_lis3lv02d_devices[] = { 1244 /* 1245 * Dell platform team told us that these Latitude devices have 1246 * ST microelectronics accelerometer at I2C address 0x29. 1247 */ 1248 { "Latitude E5250", 0x29 }, 1249 { "Latitude E5450", 0x29 }, 1250 { "Latitude E5550", 0x29 }, 1251 { "Latitude E6440", 0x29 }, 1252 { "Latitude E6440 ATG", 0x29 }, 1253 { "Latitude E6540", 0x29 }, 1254 /* 1255 * Additional individual entries were added after verification. 1256 */ 1257 { "Vostro V131", 0x1d }, 1258 }; 1259 1260 static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv) 1261 { 1262 struct i2c_board_info info; 1263 const char *dmi_product_name; 1264 int i; 1265 1266 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME); 1267 for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) { 1268 if (strcmp(dmi_product_name, 1269 dell_lis3lv02d_devices[i].dmi_product_name) == 0) 1270 break; 1271 } 1272 1273 if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) { 1274 dev_warn(&priv->pci_dev->dev, 1275 "Accelerometer lis3lv02d is present on SMBus but its" 1276 " address is unknown, skipping registration\n"); 1277 return; 1278 } 1279 1280 memset(&info, 0, sizeof(struct i2c_board_info)); 1281 info.addr = dell_lis3lv02d_devices[i].i2c_addr; 1282 strlcpy(info.type, "lis3lv02d", I2C_NAME_SIZE); 1283 i2c_new_device(&priv->adapter, &info); 1284 } 1285 1286 /* Register optional slaves */ 1287 static void i801_probe_optional_slaves(struct i801_priv *priv) 1288 { 1289 /* Only register slaves on main SMBus channel */ 1290 if (priv->features & FEATURE_IDF) 1291 return; 1292 1293 if (apanel_addr) { 1294 struct i2c_board_info info; 1295 1296 memset(&info, 0, sizeof(struct i2c_board_info)); 1297 info.addr = apanel_addr; 1298 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE); 1299 i2c_new_device(&priv->adapter, &info); 1300 } 1301 1302 if (dmi_name_in_vendors("FUJITSU")) 1303 dmi_walk(dmi_check_onboard_devices, &priv->adapter); 1304 1305 if (is_dell_system_with_lis3lv02d()) 1306 register_dell_lis3lv02d_i2c_device(priv); 1307 } 1308 #else 1309 static void __init input_apanel_init(void) {} 1310 static void i801_probe_optional_slaves(struct i801_priv *priv) {} 1311 #endif /* CONFIG_X86 && CONFIG_DMI */ 1312 1313 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 1314 static struct i801_mux_config i801_mux_config_asus_z8_d12 = { 1315 .gpio_chip = "gpio_ich", 1316 .values = { 0x02, 0x03 }, 1317 .n_values = 2, 1318 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD }, 1319 .gpios = { 52, 53 }, 1320 .n_gpios = 2, 1321 }; 1322 1323 static struct i801_mux_config i801_mux_config_asus_z8_d18 = { 1324 .gpio_chip = "gpio_ich", 1325 .values = { 0x02, 0x03, 0x01 }, 1326 .n_values = 3, 1327 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD }, 1328 .gpios = { 52, 53 }, 1329 .n_gpios = 2, 1330 }; 1331 1332 static const struct dmi_system_id mux_dmi_table[] = { 1333 { 1334 .matches = { 1335 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1336 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"), 1337 }, 1338 .driver_data = &i801_mux_config_asus_z8_d12, 1339 }, 1340 { 1341 .matches = { 1342 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1343 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"), 1344 }, 1345 .driver_data = &i801_mux_config_asus_z8_d12, 1346 }, 1347 { 1348 .matches = { 1349 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1350 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"), 1351 }, 1352 .driver_data = &i801_mux_config_asus_z8_d12, 1353 }, 1354 { 1355 .matches = { 1356 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1357 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"), 1358 }, 1359 .driver_data = &i801_mux_config_asus_z8_d12, 1360 }, 1361 { 1362 .matches = { 1363 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1364 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"), 1365 }, 1366 .driver_data = &i801_mux_config_asus_z8_d12, 1367 }, 1368 { 1369 .matches = { 1370 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1371 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"), 1372 }, 1373 .driver_data = &i801_mux_config_asus_z8_d12, 1374 }, 1375 { 1376 .matches = { 1377 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1378 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"), 1379 }, 1380 .driver_data = &i801_mux_config_asus_z8_d18, 1381 }, 1382 { 1383 .matches = { 1384 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1385 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"), 1386 }, 1387 .driver_data = &i801_mux_config_asus_z8_d18, 1388 }, 1389 { 1390 .matches = { 1391 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1392 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"), 1393 }, 1394 .driver_data = &i801_mux_config_asus_z8_d12, 1395 }, 1396 { } 1397 }; 1398 1399 /* Setup multiplexing if needed */ 1400 static int i801_add_mux(struct i801_priv *priv) 1401 { 1402 struct device *dev = &priv->adapter.dev; 1403 const struct i801_mux_config *mux_config; 1404 struct i2c_mux_gpio_platform_data gpio_data; 1405 struct gpiod_lookup_table *lookup; 1406 int err, i; 1407 1408 if (!priv->mux_drvdata) 1409 return 0; 1410 mux_config = priv->mux_drvdata; 1411 1412 /* Prepare the platform data */ 1413 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data)); 1414 gpio_data.parent = priv->adapter.nr; 1415 gpio_data.values = mux_config->values; 1416 gpio_data.n_values = mux_config->n_values; 1417 gpio_data.classes = mux_config->classes; 1418 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE; 1419 1420 /* Register GPIO descriptor lookup table */ 1421 lookup = devm_kzalloc(dev, 1422 struct_size(lookup, table, mux_config->n_gpios), 1423 GFP_KERNEL); 1424 if (!lookup) 1425 return -ENOMEM; 1426 lookup->dev_id = "i2c-mux-gpio"; 1427 for (i = 0; i < mux_config->n_gpios; i++) { 1428 lookup->table[i].chip_label = mux_config->gpio_chip; 1429 lookup->table[i].chip_hwnum = mux_config->gpios[i]; 1430 lookup->table[i].con_id = "mux"; 1431 } 1432 gpiod_add_lookup_table(lookup); 1433 priv->lookup = lookup; 1434 1435 /* 1436 * Register the mux device, we use PLATFORM_DEVID_NONE here 1437 * because since we are referring to the GPIO chip by name we are 1438 * anyways in deep trouble if there is more than one of these 1439 * devices, and there should likely only be one platform controller 1440 * hub. 1441 */ 1442 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio", 1443 PLATFORM_DEVID_NONE, &gpio_data, 1444 sizeof(struct i2c_mux_gpio_platform_data)); 1445 if (IS_ERR(priv->mux_pdev)) { 1446 err = PTR_ERR(priv->mux_pdev); 1447 gpiod_remove_lookup_table(lookup); 1448 priv->mux_pdev = NULL; 1449 dev_err(dev, "Failed to register i2c-mux-gpio device\n"); 1450 return err; 1451 } 1452 1453 return 0; 1454 } 1455 1456 static void i801_del_mux(struct i801_priv *priv) 1457 { 1458 if (priv->mux_pdev) 1459 platform_device_unregister(priv->mux_pdev); 1460 if (priv->lookup) 1461 gpiod_remove_lookup_table(priv->lookup); 1462 } 1463 1464 static unsigned int i801_get_adapter_class(struct i801_priv *priv) 1465 { 1466 const struct dmi_system_id *id; 1467 const struct i801_mux_config *mux_config; 1468 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 1469 int i; 1470 1471 id = dmi_first_match(mux_dmi_table); 1472 if (id) { 1473 /* Remove branch classes from trunk */ 1474 mux_config = id->driver_data; 1475 for (i = 0; i < mux_config->n_values; i++) 1476 class &= ~mux_config->classes[i]; 1477 1478 /* Remember for later */ 1479 priv->mux_drvdata = mux_config; 1480 } 1481 1482 return class; 1483 } 1484 #else 1485 static inline int i801_add_mux(struct i801_priv *priv) { return 0; } 1486 static inline void i801_del_mux(struct i801_priv *priv) { } 1487 1488 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv) 1489 { 1490 return I2C_CLASS_HWMON | I2C_CLASS_SPD; 1491 } 1492 #endif 1493 1494 static const struct itco_wdt_platform_data tco_platform_data = { 1495 .name = "Intel PCH", 1496 .version = 4, 1497 }; 1498 1499 static DEFINE_SPINLOCK(p2sb_spinlock); 1500 1501 static void i801_add_tco(struct i801_priv *priv) 1502 { 1503 struct pci_dev *pci_dev = priv->pci_dev; 1504 struct resource tco_res[3], *res; 1505 struct platform_device *pdev; 1506 unsigned int devfn; 1507 u32 tco_base, tco_ctl; 1508 u32 base_addr, ctrl_val; 1509 u64 base64_addr; 1510 u8 hidden; 1511 1512 if (!(priv->features & FEATURE_TCO)) 1513 return; 1514 1515 pci_read_config_dword(pci_dev, TCOBASE, &tco_base); 1516 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl); 1517 if (!(tco_ctl & TCOCTL_EN)) 1518 return; 1519 1520 memset(tco_res, 0, sizeof(tco_res)); 1521 1522 res = &tco_res[ICH_RES_IO_TCO]; 1523 res->start = tco_base & ~1; 1524 res->end = res->start + 32 - 1; 1525 res->flags = IORESOURCE_IO; 1526 1527 /* 1528 * Power Management registers. 1529 */ 1530 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 2); 1531 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPIBASE, &base_addr); 1532 1533 res = &tco_res[ICH_RES_IO_SMI]; 1534 res->start = (base_addr & ~1) + ACPIBASE_SMI_OFF; 1535 res->end = res->start + 3; 1536 res->flags = IORESOURCE_IO; 1537 1538 /* 1539 * Enable the ACPI I/O space. 1540 */ 1541 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPICTRL, &ctrl_val); 1542 ctrl_val |= ACPICTRL_EN; 1543 pci_bus_write_config_dword(pci_dev->bus, devfn, ACPICTRL, ctrl_val); 1544 1545 /* 1546 * We must access the NO_REBOOT bit over the Primary to Sideband 1547 * bridge (P2SB). The BIOS prevents the P2SB device from being 1548 * enumerated by the PCI subsystem, so we need to unhide/hide it 1549 * to lookup the P2SB BAR. 1550 */ 1551 spin_lock(&p2sb_spinlock); 1552 1553 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1); 1554 1555 /* Unhide the P2SB device, if it is hidden */ 1556 pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden); 1557 if (hidden) 1558 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0); 1559 1560 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr); 1561 base64_addr = base_addr & 0xfffffff0; 1562 1563 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr); 1564 base64_addr |= (u64)base_addr << 32; 1565 1566 /* Hide the P2SB device, if it was hidden before */ 1567 if (hidden) 1568 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden); 1569 spin_unlock(&p2sb_spinlock); 1570 1571 res = &tco_res[ICH_RES_MEM_OFF]; 1572 if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS) 1573 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV; 1574 else 1575 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL; 1576 1577 res->end = res->start + 3; 1578 res->flags = IORESOURCE_MEM; 1579 1580 pdev = platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1, 1581 tco_res, 3, &tco_platform_data, 1582 sizeof(tco_platform_data)); 1583 if (IS_ERR(pdev)) { 1584 dev_warn(&pci_dev->dev, "failed to create iTCO device\n"); 1585 return; 1586 } 1587 1588 priv->tco_pdev = pdev; 1589 } 1590 1591 #ifdef CONFIG_ACPI 1592 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv, 1593 acpi_physical_address address) 1594 { 1595 return address >= priv->smba && 1596 address <= pci_resource_end(priv->pci_dev, SMBBAR); 1597 } 1598 1599 static acpi_status 1600 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits, 1601 u64 *value, void *handler_context, void *region_context) 1602 { 1603 struct i801_priv *priv = handler_context; 1604 struct pci_dev *pdev = priv->pci_dev; 1605 acpi_status status; 1606 1607 /* 1608 * Once BIOS AML code touches the OpRegion we warn and inhibit any 1609 * further access from the driver itself. This device is now owned 1610 * by the system firmware. 1611 */ 1612 mutex_lock(&priv->acpi_lock); 1613 1614 if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) { 1615 priv->acpi_reserved = true; 1616 1617 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n"); 1618 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n"); 1619 1620 /* 1621 * BIOS is accessing the host controller so prevent it from 1622 * suspending automatically from now on. 1623 */ 1624 pm_runtime_get_sync(&pdev->dev); 1625 } 1626 1627 if ((function & ACPI_IO_MASK) == ACPI_READ) 1628 status = acpi_os_read_port(address, (u32 *)value, bits); 1629 else 1630 status = acpi_os_write_port(address, (u32)*value, bits); 1631 1632 mutex_unlock(&priv->acpi_lock); 1633 1634 return status; 1635 } 1636 1637 static int i801_acpi_probe(struct i801_priv *priv) 1638 { 1639 struct acpi_device *adev; 1640 acpi_status status; 1641 1642 adev = ACPI_COMPANION(&priv->pci_dev->dev); 1643 if (adev) { 1644 status = acpi_install_address_space_handler(adev->handle, 1645 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler, 1646 NULL, priv); 1647 if (ACPI_SUCCESS(status)) 1648 return 0; 1649 } 1650 1651 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]); 1652 } 1653 1654 static void i801_acpi_remove(struct i801_priv *priv) 1655 { 1656 struct acpi_device *adev; 1657 1658 adev = ACPI_COMPANION(&priv->pci_dev->dev); 1659 if (!adev) 1660 return; 1661 1662 acpi_remove_address_space_handler(adev->handle, 1663 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler); 1664 1665 mutex_lock(&priv->acpi_lock); 1666 if (priv->acpi_reserved) 1667 pm_runtime_put(&priv->pci_dev->dev); 1668 mutex_unlock(&priv->acpi_lock); 1669 } 1670 #else 1671 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; } 1672 static inline void i801_acpi_remove(struct i801_priv *priv) { } 1673 #endif 1674 1675 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id) 1676 { 1677 unsigned char temp; 1678 int err, i; 1679 struct i801_priv *priv; 1680 1681 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL); 1682 if (!priv) 1683 return -ENOMEM; 1684 1685 i2c_set_adapdata(&priv->adapter, priv); 1686 priv->adapter.owner = THIS_MODULE; 1687 priv->adapter.class = i801_get_adapter_class(priv); 1688 priv->adapter.algo = &smbus_algorithm; 1689 priv->adapter.dev.parent = &dev->dev; 1690 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev)); 1691 priv->adapter.retries = 3; 1692 mutex_init(&priv->acpi_lock); 1693 1694 priv->pci_dev = dev; 1695 switch (dev->device) { 1696 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS: 1697 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS: 1698 case PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS: 1699 case PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS: 1700 case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS: 1701 case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS: 1702 case PCI_DEVICE_ID_INTEL_CDF_SMBUS: 1703 case PCI_DEVICE_ID_INTEL_DNV_SMBUS: 1704 case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS: 1705 case PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS: 1706 case PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS: 1707 case PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS: 1708 case PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS: 1709 priv->features |= FEATURE_BLOCK_PROC; 1710 priv->features |= FEATURE_I2C_BLOCK_READ; 1711 priv->features |= FEATURE_IRQ; 1712 priv->features |= FEATURE_SMBUS_PEC; 1713 priv->features |= FEATURE_BLOCK_BUFFER; 1714 /* If we have ACPI based watchdog use that instead */ 1715 if (!acpi_has_watchdog()) 1716 priv->features |= FEATURE_TCO; 1717 priv->features |= FEATURE_HOST_NOTIFY; 1718 break; 1719 1720 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0: 1721 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1: 1722 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2: 1723 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0: 1724 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1: 1725 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2: 1726 priv->features |= FEATURE_IDF; 1727 /* fall through */ 1728 default: 1729 priv->features |= FEATURE_BLOCK_PROC; 1730 priv->features |= FEATURE_I2C_BLOCK_READ; 1731 priv->features |= FEATURE_IRQ; 1732 /* fall through */ 1733 case PCI_DEVICE_ID_INTEL_82801DB_3: 1734 priv->features |= FEATURE_SMBUS_PEC; 1735 priv->features |= FEATURE_BLOCK_BUFFER; 1736 /* fall through */ 1737 case PCI_DEVICE_ID_INTEL_82801CA_3: 1738 priv->features |= FEATURE_HOST_NOTIFY; 1739 /* fall through */ 1740 case PCI_DEVICE_ID_INTEL_82801BA_2: 1741 case PCI_DEVICE_ID_INTEL_82801AB_3: 1742 case PCI_DEVICE_ID_INTEL_82801AA_3: 1743 break; 1744 } 1745 1746 /* Disable features on user request */ 1747 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) { 1748 if (priv->features & disable_features & (1 << i)) 1749 dev_notice(&dev->dev, "%s disabled by user\n", 1750 i801_feature_names[i]); 1751 } 1752 priv->features &= ~disable_features; 1753 1754 err = pcim_enable_device(dev); 1755 if (err) { 1756 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", 1757 err); 1758 return err; 1759 } 1760 pcim_pin_device(dev); 1761 1762 /* Determine the address of the SMBus area */ 1763 priv->smba = pci_resource_start(dev, SMBBAR); 1764 if (!priv->smba) { 1765 dev_err(&dev->dev, 1766 "SMBus base address uninitialized, upgrade BIOS\n"); 1767 return -ENODEV; 1768 } 1769 1770 if (i801_acpi_probe(priv)) 1771 return -ENODEV; 1772 1773 err = pcim_iomap_regions(dev, 1 << SMBBAR, 1774 dev_driver_string(&dev->dev)); 1775 if (err) { 1776 dev_err(&dev->dev, 1777 "Failed to request SMBus region 0x%lx-0x%Lx\n", 1778 priv->smba, 1779 (unsigned long long)pci_resource_end(dev, SMBBAR)); 1780 i801_acpi_remove(priv); 1781 return err; 1782 } 1783 1784 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp); 1785 priv->original_hstcfg = temp; 1786 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ 1787 if (!(temp & SMBHSTCFG_HST_EN)) { 1788 dev_info(&dev->dev, "Enabling SMBus device\n"); 1789 temp |= SMBHSTCFG_HST_EN; 1790 } 1791 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp); 1792 1793 if (temp & SMBHSTCFG_SMB_SMI_EN) { 1794 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); 1795 /* Disable SMBus interrupt feature if SMBus using SMI# */ 1796 priv->features &= ~FEATURE_IRQ; 1797 } 1798 if (temp & SMBHSTCFG_SPD_WD) 1799 dev_info(&dev->dev, "SPD Write Disable is set\n"); 1800 1801 /* Clear special mode bits */ 1802 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) 1803 outb_p(inb_p(SMBAUXCTL(priv)) & 1804 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 1805 1806 /* Remember original Host Notify setting */ 1807 if (priv->features & FEATURE_HOST_NOTIFY) 1808 priv->original_slvcmd = inb_p(SMBSLVCMD(priv)); 1809 1810 /* Default timeout in interrupt mode: 200 ms */ 1811 priv->adapter.timeout = HZ / 5; 1812 1813 if (dev->irq == IRQ_NOTCONNECTED) 1814 priv->features &= ~FEATURE_IRQ; 1815 1816 if (priv->features & FEATURE_IRQ) { 1817 u16 pcictl, pcists; 1818 1819 /* Complain if an interrupt is already pending */ 1820 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); 1821 if (pcists & SMBPCISTS_INTS) 1822 dev_warn(&dev->dev, "An interrupt is pending!\n"); 1823 1824 /* Check if interrupts have been disabled */ 1825 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl); 1826 if (pcictl & SMBPCICTL_INTDIS) { 1827 dev_info(&dev->dev, "Interrupts are disabled\n"); 1828 priv->features &= ~FEATURE_IRQ; 1829 } 1830 } 1831 1832 if (priv->features & FEATURE_IRQ) { 1833 init_waitqueue_head(&priv->waitq); 1834 1835 err = devm_request_irq(&dev->dev, dev->irq, i801_isr, 1836 IRQF_SHARED, 1837 dev_driver_string(&dev->dev), priv); 1838 if (err) { 1839 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n", 1840 dev->irq, err); 1841 priv->features &= ~FEATURE_IRQ; 1842 } 1843 } 1844 dev_info(&dev->dev, "SMBus using %s\n", 1845 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling"); 1846 1847 i801_add_tco(priv); 1848 1849 snprintf(priv->adapter.name, sizeof(priv->adapter.name), 1850 "SMBus I801 adapter at %04lx", priv->smba); 1851 err = i2c_add_adapter(&priv->adapter); 1852 if (err) { 1853 i801_acpi_remove(priv); 1854 return err; 1855 } 1856 1857 i801_enable_host_notify(&priv->adapter); 1858 1859 i801_probe_optional_slaves(priv); 1860 /* We ignore errors - multiplexing is optional */ 1861 i801_add_mux(priv); 1862 1863 pci_set_drvdata(dev, priv); 1864 1865 pm_runtime_set_autosuspend_delay(&dev->dev, 1000); 1866 pm_runtime_use_autosuspend(&dev->dev); 1867 pm_runtime_put_autosuspend(&dev->dev); 1868 pm_runtime_allow(&dev->dev); 1869 1870 return 0; 1871 } 1872 1873 static void i801_remove(struct pci_dev *dev) 1874 { 1875 struct i801_priv *priv = pci_get_drvdata(dev); 1876 1877 pm_runtime_forbid(&dev->dev); 1878 pm_runtime_get_noresume(&dev->dev); 1879 1880 i801_disable_host_notify(priv); 1881 i801_del_mux(priv); 1882 i2c_del_adapter(&priv->adapter); 1883 i801_acpi_remove(priv); 1884 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); 1885 1886 platform_device_unregister(priv->tco_pdev); 1887 1888 /* 1889 * do not call pci_disable_device(dev) since it can cause hard hangs on 1890 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) 1891 */ 1892 } 1893 1894 static void i801_shutdown(struct pci_dev *dev) 1895 { 1896 struct i801_priv *priv = pci_get_drvdata(dev); 1897 1898 /* Restore config registers to avoid hard hang on some systems */ 1899 i801_disable_host_notify(priv); 1900 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); 1901 } 1902 1903 #ifdef CONFIG_PM_SLEEP 1904 static int i801_suspend(struct device *dev) 1905 { 1906 struct pci_dev *pci_dev = to_pci_dev(dev); 1907 struct i801_priv *priv = pci_get_drvdata(pci_dev); 1908 1909 pci_write_config_byte(pci_dev, SMBHSTCFG, priv->original_hstcfg); 1910 return 0; 1911 } 1912 1913 static int i801_resume(struct device *dev) 1914 { 1915 struct pci_dev *pci_dev = to_pci_dev(dev); 1916 struct i801_priv *priv = pci_get_drvdata(pci_dev); 1917 1918 i801_enable_host_notify(&priv->adapter); 1919 1920 return 0; 1921 } 1922 #endif 1923 1924 static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume); 1925 1926 static struct pci_driver i801_driver = { 1927 .name = "i801_smbus", 1928 .id_table = i801_ids, 1929 .probe = i801_probe, 1930 .remove = i801_remove, 1931 .shutdown = i801_shutdown, 1932 .driver = { 1933 .pm = &i801_pm_ops, 1934 }, 1935 }; 1936 1937 static int __init i2c_i801_init(void) 1938 { 1939 if (dmi_name_in_vendors("FUJITSU")) 1940 input_apanel_init(); 1941 return pci_register_driver(&i801_driver); 1942 } 1943 1944 static void __exit i2c_i801_exit(void) 1945 { 1946 pci_unregister_driver(&i801_driver); 1947 } 1948 1949 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>"); 1950 MODULE_DESCRIPTION("I801 SMBus driver"); 1951 MODULE_LICENSE("GPL"); 1952 1953 module_init(i2c_i801_init); 1954 module_exit(i2c_i801_exit); 1955