1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (c) 2014 Linaro Ltd. 4 * Copyright (c) 2014 Hisilicon Limited. 5 * 6 * Now only support 7 bit address. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/i2c.h> 12 #include <linux/io.h> 13 #include <linux/interrupt.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 19 /* Register Map */ 20 #define HIX5I2C_CTRL 0x00 21 #define HIX5I2C_COM 0x04 22 #define HIX5I2C_ICR 0x08 23 #define HIX5I2C_SR 0x0c 24 #define HIX5I2C_SCL_H 0x10 25 #define HIX5I2C_SCL_L 0x14 26 #define HIX5I2C_TXR 0x18 27 #define HIX5I2C_RXR 0x1c 28 29 /* I2C_CTRL_REG */ 30 #define I2C_ENABLE BIT(8) 31 #define I2C_UNMASK_TOTAL BIT(7) 32 #define I2C_UNMASK_START BIT(6) 33 #define I2C_UNMASK_END BIT(5) 34 #define I2C_UNMASK_SEND BIT(4) 35 #define I2C_UNMASK_RECEIVE BIT(3) 36 #define I2C_UNMASK_ACK BIT(2) 37 #define I2C_UNMASK_ARBITRATE BIT(1) 38 #define I2C_UNMASK_OVER BIT(0) 39 #define I2C_UNMASK_ALL (I2C_UNMASK_ACK | I2C_UNMASK_OVER) 40 41 /* I2C_COM_REG */ 42 #define I2C_NO_ACK BIT(4) 43 #define I2C_START BIT(3) 44 #define I2C_READ BIT(2) 45 #define I2C_WRITE BIT(1) 46 #define I2C_STOP BIT(0) 47 48 /* I2C_ICR_REG */ 49 #define I2C_CLEAR_START BIT(6) 50 #define I2C_CLEAR_END BIT(5) 51 #define I2C_CLEAR_SEND BIT(4) 52 #define I2C_CLEAR_RECEIVE BIT(3) 53 #define I2C_CLEAR_ACK BIT(2) 54 #define I2C_CLEAR_ARBITRATE BIT(1) 55 #define I2C_CLEAR_OVER BIT(0) 56 #define I2C_CLEAR_ALL (I2C_CLEAR_START | I2C_CLEAR_END | \ 57 I2C_CLEAR_SEND | I2C_CLEAR_RECEIVE | \ 58 I2C_CLEAR_ACK | I2C_CLEAR_ARBITRATE | \ 59 I2C_CLEAR_OVER) 60 61 /* I2C_SR_REG */ 62 #define I2C_BUSY BIT(7) 63 #define I2C_START_INTR BIT(6) 64 #define I2C_END_INTR BIT(5) 65 #define I2C_SEND_INTR BIT(4) 66 #define I2C_RECEIVE_INTR BIT(3) 67 #define I2C_ACK_INTR BIT(2) 68 #define I2C_ARBITRATE_INTR BIT(1) 69 #define I2C_OVER_INTR BIT(0) 70 71 #define HIX5I2C_MAX_FREQ 400000 /* 400k */ 72 73 enum hix5hd2_i2c_state { 74 HIX5I2C_STAT_RW_ERR = -1, 75 HIX5I2C_STAT_INIT, 76 HIX5I2C_STAT_RW, 77 HIX5I2C_STAT_SND_STOP, 78 HIX5I2C_STAT_RW_SUCCESS, 79 }; 80 81 struct hix5hd2_i2c_priv { 82 struct i2c_adapter adap; 83 struct i2c_msg *msg; 84 struct completion msg_complete; 85 unsigned int msg_idx; 86 unsigned int msg_len; 87 int stop; 88 void __iomem *regs; 89 struct clk *clk; 90 struct device *dev; 91 spinlock_t lock; /* IRQ synchronization */ 92 int err; 93 unsigned int freq; 94 enum hix5hd2_i2c_state state; 95 }; 96 97 static u32 hix5hd2_i2c_clr_pend_irq(struct hix5hd2_i2c_priv *priv) 98 { 99 u32 val = readl_relaxed(priv->regs + HIX5I2C_SR); 100 101 writel_relaxed(val, priv->regs + HIX5I2C_ICR); 102 103 return val; 104 } 105 106 static void hix5hd2_i2c_clr_all_irq(struct hix5hd2_i2c_priv *priv) 107 { 108 writel_relaxed(I2C_CLEAR_ALL, priv->regs + HIX5I2C_ICR); 109 } 110 111 static void hix5hd2_i2c_disable_irq(struct hix5hd2_i2c_priv *priv) 112 { 113 writel_relaxed(0, priv->regs + HIX5I2C_CTRL); 114 } 115 116 static void hix5hd2_i2c_enable_irq(struct hix5hd2_i2c_priv *priv) 117 { 118 writel_relaxed(I2C_ENABLE | I2C_UNMASK_TOTAL | I2C_UNMASK_ALL, 119 priv->regs + HIX5I2C_CTRL); 120 } 121 122 static void hix5hd2_i2c_drv_setrate(struct hix5hd2_i2c_priv *priv) 123 { 124 u32 rate, val; 125 u32 scl, sysclock; 126 127 /* close all i2c interrupt */ 128 val = readl_relaxed(priv->regs + HIX5I2C_CTRL); 129 writel_relaxed(val & (~I2C_UNMASK_TOTAL), priv->regs + HIX5I2C_CTRL); 130 131 rate = priv->freq; 132 sysclock = clk_get_rate(priv->clk); 133 scl = (sysclock / (rate * 2)) / 2 - 1; 134 writel_relaxed(scl, priv->regs + HIX5I2C_SCL_H); 135 writel_relaxed(scl, priv->regs + HIX5I2C_SCL_L); 136 137 /* restore original interrupt*/ 138 writel_relaxed(val, priv->regs + HIX5I2C_CTRL); 139 140 dev_dbg(priv->dev, "%s: sysclock=%d, rate=%d, scl=%d\n", 141 __func__, sysclock, rate, scl); 142 } 143 144 static void hix5hd2_i2c_init(struct hix5hd2_i2c_priv *priv) 145 { 146 hix5hd2_i2c_disable_irq(priv); 147 hix5hd2_i2c_drv_setrate(priv); 148 hix5hd2_i2c_clr_all_irq(priv); 149 hix5hd2_i2c_enable_irq(priv); 150 } 151 152 static void hix5hd2_i2c_reset(struct hix5hd2_i2c_priv *priv) 153 { 154 clk_disable_unprepare(priv->clk); 155 msleep(20); 156 clk_prepare_enable(priv->clk); 157 hix5hd2_i2c_init(priv); 158 } 159 160 static int hix5hd2_i2c_wait_bus_idle(struct hix5hd2_i2c_priv *priv) 161 { 162 unsigned long stop_time; 163 u32 int_status; 164 165 /* wait for 100 milli seconds for the bus to be idle */ 166 stop_time = jiffies + msecs_to_jiffies(100); 167 do { 168 int_status = hix5hd2_i2c_clr_pend_irq(priv); 169 if (!(int_status & I2C_BUSY)) 170 return 0; 171 172 usleep_range(50, 200); 173 } while (time_before(jiffies, stop_time)); 174 175 return -EBUSY; 176 } 177 178 static void hix5hd2_rw_over(struct hix5hd2_i2c_priv *priv) 179 { 180 if (priv->state == HIX5I2C_STAT_SND_STOP) 181 dev_dbg(priv->dev, "%s: rw and send stop over\n", __func__); 182 else 183 dev_dbg(priv->dev, "%s: have not data to send\n", __func__); 184 185 priv->state = HIX5I2C_STAT_RW_SUCCESS; 186 priv->err = 0; 187 } 188 189 static void hix5hd2_rw_handle_stop(struct hix5hd2_i2c_priv *priv) 190 { 191 if (priv->stop) { 192 priv->state = HIX5I2C_STAT_SND_STOP; 193 writel_relaxed(I2C_STOP, priv->regs + HIX5I2C_COM); 194 } else { 195 hix5hd2_rw_over(priv); 196 } 197 } 198 199 static void hix5hd2_read_handle(struct hix5hd2_i2c_priv *priv) 200 { 201 if (priv->msg_len == 1) { 202 /* the last byte don't need send ACK */ 203 writel_relaxed(I2C_READ | I2C_NO_ACK, priv->regs + HIX5I2C_COM); 204 } else if (priv->msg_len > 1) { 205 /* if i2c master receive data will send ACK */ 206 writel_relaxed(I2C_READ, priv->regs + HIX5I2C_COM); 207 } else { 208 hix5hd2_rw_handle_stop(priv); 209 } 210 } 211 212 static void hix5hd2_write_handle(struct hix5hd2_i2c_priv *priv) 213 { 214 u8 data; 215 216 if (priv->msg_len > 0) { 217 data = priv->msg->buf[priv->msg_idx++]; 218 writel_relaxed(data, priv->regs + HIX5I2C_TXR); 219 writel_relaxed(I2C_WRITE, priv->regs + HIX5I2C_COM); 220 } else { 221 hix5hd2_rw_handle_stop(priv); 222 } 223 } 224 225 static int hix5hd2_rw_preprocess(struct hix5hd2_i2c_priv *priv) 226 { 227 u8 data; 228 229 if (priv->state == HIX5I2C_STAT_INIT) { 230 priv->state = HIX5I2C_STAT_RW; 231 } else if (priv->state == HIX5I2C_STAT_RW) { 232 if (priv->msg->flags & I2C_M_RD) { 233 data = readl_relaxed(priv->regs + HIX5I2C_RXR); 234 priv->msg->buf[priv->msg_idx++] = data; 235 } 236 priv->msg_len--; 237 } else { 238 dev_dbg(priv->dev, "%s: error: priv->state = %d, msg_len = %d\n", 239 __func__, priv->state, priv->msg_len); 240 return -EAGAIN; 241 } 242 return 0; 243 } 244 245 static irqreturn_t hix5hd2_i2c_irq(int irqno, void *dev_id) 246 { 247 struct hix5hd2_i2c_priv *priv = dev_id; 248 u32 int_status; 249 int ret; 250 251 spin_lock(&priv->lock); 252 253 int_status = hix5hd2_i2c_clr_pend_irq(priv); 254 255 /* handle error */ 256 if (int_status & I2C_ARBITRATE_INTR) { 257 /* bus error */ 258 dev_dbg(priv->dev, "ARB bus loss\n"); 259 priv->err = -EAGAIN; 260 priv->state = HIX5I2C_STAT_RW_ERR; 261 goto stop; 262 } else if (int_status & I2C_ACK_INTR) { 263 /* ack error */ 264 dev_dbg(priv->dev, "No ACK from device\n"); 265 priv->err = -ENXIO; 266 priv->state = HIX5I2C_STAT_RW_ERR; 267 goto stop; 268 } 269 270 if (int_status & I2C_OVER_INTR) { 271 if (priv->msg_len > 0) { 272 ret = hix5hd2_rw_preprocess(priv); 273 if (ret) { 274 priv->err = ret; 275 priv->state = HIX5I2C_STAT_RW_ERR; 276 goto stop; 277 } 278 if (priv->msg->flags & I2C_M_RD) 279 hix5hd2_read_handle(priv); 280 else 281 hix5hd2_write_handle(priv); 282 } else { 283 hix5hd2_rw_over(priv); 284 } 285 } 286 287 stop: 288 if ((priv->state == HIX5I2C_STAT_RW_SUCCESS && 289 priv->msg->len == priv->msg_idx) || 290 (priv->state == HIX5I2C_STAT_RW_ERR)) { 291 hix5hd2_i2c_disable_irq(priv); 292 hix5hd2_i2c_clr_pend_irq(priv); 293 complete(&priv->msg_complete); 294 } 295 296 spin_unlock(&priv->lock); 297 298 return IRQ_HANDLED; 299 } 300 301 static void hix5hd2_i2c_message_start(struct hix5hd2_i2c_priv *priv, int stop) 302 { 303 unsigned long flags; 304 305 spin_lock_irqsave(&priv->lock, flags); 306 hix5hd2_i2c_clr_all_irq(priv); 307 hix5hd2_i2c_enable_irq(priv); 308 309 writel_relaxed(i2c_8bit_addr_from_msg(priv->msg), 310 priv->regs + HIX5I2C_TXR); 311 312 writel_relaxed(I2C_WRITE | I2C_START, priv->regs + HIX5I2C_COM); 313 spin_unlock_irqrestore(&priv->lock, flags); 314 } 315 316 static int hix5hd2_i2c_xfer_msg(struct hix5hd2_i2c_priv *priv, 317 struct i2c_msg *msgs, int stop) 318 { 319 unsigned long timeout; 320 int ret; 321 322 priv->msg = msgs; 323 priv->msg_idx = 0; 324 priv->msg_len = priv->msg->len; 325 priv->stop = stop; 326 priv->err = 0; 327 priv->state = HIX5I2C_STAT_INIT; 328 329 reinit_completion(&priv->msg_complete); 330 hix5hd2_i2c_message_start(priv, stop); 331 332 timeout = wait_for_completion_timeout(&priv->msg_complete, 333 priv->adap.timeout); 334 if (timeout == 0) { 335 priv->state = HIX5I2C_STAT_RW_ERR; 336 priv->err = -ETIMEDOUT; 337 dev_warn(priv->dev, "%s timeout=%d\n", 338 msgs->flags & I2C_M_RD ? "rx" : "tx", 339 priv->adap.timeout); 340 } 341 ret = priv->state; 342 343 /* 344 * If this is the last message to be transfered (stop == 1) 345 * Then check if the bus can be brought back to idle. 346 */ 347 if (priv->state == HIX5I2C_STAT_RW_SUCCESS && stop) 348 ret = hix5hd2_i2c_wait_bus_idle(priv); 349 350 if (ret < 0) 351 hix5hd2_i2c_reset(priv); 352 353 return priv->err; 354 } 355 356 static int hix5hd2_i2c_xfer(struct i2c_adapter *adap, 357 struct i2c_msg *msgs, int num) 358 { 359 struct hix5hd2_i2c_priv *priv = i2c_get_adapdata(adap); 360 int i, ret, stop; 361 362 pm_runtime_get_sync(priv->dev); 363 364 for (i = 0; i < num; i++, msgs++) { 365 stop = (i == num - 1); 366 ret = hix5hd2_i2c_xfer_msg(priv, msgs, stop); 367 if (ret < 0) 368 goto out; 369 } 370 371 ret = num; 372 373 out: 374 pm_runtime_mark_last_busy(priv->dev); 375 pm_runtime_put_autosuspend(priv->dev); 376 return ret; 377 } 378 379 static u32 hix5hd2_i2c_func(struct i2c_adapter *adap) 380 { 381 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 382 } 383 384 static const struct i2c_algorithm hix5hd2_i2c_algorithm = { 385 .master_xfer = hix5hd2_i2c_xfer, 386 .functionality = hix5hd2_i2c_func, 387 }; 388 389 static int hix5hd2_i2c_probe(struct platform_device *pdev) 390 { 391 struct device_node *np = pdev->dev.of_node; 392 struct hix5hd2_i2c_priv *priv; 393 struct resource *mem; 394 unsigned int freq; 395 int irq, ret; 396 397 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 398 if (!priv) 399 return -ENOMEM; 400 401 if (of_property_read_u32(np, "clock-frequency", &freq)) { 402 /* use 100k as default value */ 403 priv->freq = 100000; 404 } else { 405 if (freq > HIX5I2C_MAX_FREQ) { 406 priv->freq = HIX5I2C_MAX_FREQ; 407 dev_warn(priv->dev, "use max freq %d instead\n", 408 HIX5I2C_MAX_FREQ); 409 } else { 410 priv->freq = freq; 411 } 412 } 413 414 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 415 priv->regs = devm_ioremap_resource(&pdev->dev, mem); 416 if (IS_ERR(priv->regs)) 417 return PTR_ERR(priv->regs); 418 419 irq = platform_get_irq(pdev, 0); 420 if (irq <= 0) { 421 dev_err(&pdev->dev, "cannot find HS-I2C IRQ\n"); 422 return irq; 423 } 424 425 priv->clk = devm_clk_get(&pdev->dev, NULL); 426 if (IS_ERR(priv->clk)) { 427 dev_err(&pdev->dev, "cannot get clock\n"); 428 return PTR_ERR(priv->clk); 429 } 430 clk_prepare_enable(priv->clk); 431 432 strlcpy(priv->adap.name, "hix5hd2-i2c", sizeof(priv->adap.name)); 433 priv->dev = &pdev->dev; 434 priv->adap.owner = THIS_MODULE; 435 priv->adap.algo = &hix5hd2_i2c_algorithm; 436 priv->adap.retries = 3; 437 priv->adap.dev.of_node = np; 438 priv->adap.algo_data = priv; 439 priv->adap.dev.parent = &pdev->dev; 440 i2c_set_adapdata(&priv->adap, priv); 441 platform_set_drvdata(pdev, priv); 442 spin_lock_init(&priv->lock); 443 init_completion(&priv->msg_complete); 444 445 hix5hd2_i2c_init(priv); 446 447 ret = devm_request_irq(&pdev->dev, irq, hix5hd2_i2c_irq, 448 IRQF_NO_SUSPEND | IRQF_ONESHOT, 449 dev_name(&pdev->dev), priv); 450 if (ret != 0) { 451 dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n", irq); 452 goto err_clk; 453 } 454 455 pm_runtime_set_autosuspend_delay(priv->dev, MSEC_PER_SEC); 456 pm_runtime_use_autosuspend(priv->dev); 457 pm_runtime_set_active(priv->dev); 458 pm_runtime_enable(priv->dev); 459 460 ret = i2c_add_adapter(&priv->adap); 461 if (ret < 0) 462 goto err_runtime; 463 464 return ret; 465 466 err_runtime: 467 pm_runtime_disable(priv->dev); 468 pm_runtime_set_suspended(priv->dev); 469 err_clk: 470 clk_disable_unprepare(priv->clk); 471 return ret; 472 } 473 474 static int hix5hd2_i2c_remove(struct platform_device *pdev) 475 { 476 struct hix5hd2_i2c_priv *priv = platform_get_drvdata(pdev); 477 478 i2c_del_adapter(&priv->adap); 479 pm_runtime_disable(priv->dev); 480 pm_runtime_set_suspended(priv->dev); 481 482 return 0; 483 } 484 485 #ifdef CONFIG_PM 486 static int hix5hd2_i2c_runtime_suspend(struct device *dev) 487 { 488 struct hix5hd2_i2c_priv *priv = dev_get_drvdata(dev); 489 490 clk_disable_unprepare(priv->clk); 491 492 return 0; 493 } 494 495 static int hix5hd2_i2c_runtime_resume(struct device *dev) 496 { 497 struct hix5hd2_i2c_priv *priv = dev_get_drvdata(dev); 498 499 clk_prepare_enable(priv->clk); 500 hix5hd2_i2c_init(priv); 501 502 return 0; 503 } 504 #endif 505 506 static const struct dev_pm_ops hix5hd2_i2c_pm_ops = { 507 SET_RUNTIME_PM_OPS(hix5hd2_i2c_runtime_suspend, 508 hix5hd2_i2c_runtime_resume, 509 NULL) 510 }; 511 512 static const struct of_device_id hix5hd2_i2c_match[] = { 513 { .compatible = "hisilicon,hix5hd2-i2c" }, 514 {}, 515 }; 516 MODULE_DEVICE_TABLE(of, hix5hd2_i2c_match); 517 518 static struct platform_driver hix5hd2_i2c_driver = { 519 .probe = hix5hd2_i2c_probe, 520 .remove = hix5hd2_i2c_remove, 521 .driver = { 522 .name = "hix5hd2-i2c", 523 .pm = &hix5hd2_i2c_pm_ops, 524 .of_match_table = hix5hd2_i2c_match, 525 }, 526 }; 527 528 module_platform_driver(hix5hd2_i2c_driver); 529 530 MODULE_DESCRIPTION("Hix5hd2 I2C Bus driver"); 531 MODULE_AUTHOR("Wei Yan <sledge.yanwei@huawei.com>"); 532 MODULE_LICENSE("GPL"); 533 MODULE_ALIAS("platform:hix5hd2-i2c"); 534