1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * HiSilicon I2C Controller Driver for Kunpeng SoC 4 * 5 * Copyright (c) 2021 HiSilicon Technologies Co., Ltd. 6 */ 7 8 #include <linux/bits.h> 9 #include <linux/bitfield.h> 10 #include <linux/completion.h> 11 #include <linux/i2c.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/module.h> 15 #include <linux/mod_devicetable.h> 16 #include <linux/platform_device.h> 17 #include <linux/property.h> 18 19 #define HISI_I2C_FRAME_CTRL 0x0000 20 #define HISI_I2C_FRAME_CTRL_SPEED_MODE GENMASK(1, 0) 21 #define HISI_I2C_FRAME_CTRL_ADDR_TEN BIT(2) 22 #define HISI_I2C_SLV_ADDR 0x0004 23 #define HISI_I2C_SLV_ADDR_VAL GENMASK(9, 0) 24 #define HISI_I2C_SLV_ADDR_GC_S_MODE BIT(10) 25 #define HISI_I2C_SLV_ADDR_GC_S_EN BIT(11) 26 #define HISI_I2C_CMD_TXDATA 0x0008 27 #define HISI_I2C_CMD_TXDATA_DATA GENMASK(7, 0) 28 #define HISI_I2C_CMD_TXDATA_RW BIT(8) 29 #define HISI_I2C_CMD_TXDATA_P_EN BIT(9) 30 #define HISI_I2C_CMD_TXDATA_SR_EN BIT(10) 31 #define HISI_I2C_RXDATA 0x000c 32 #define HISI_I2C_RXDATA_DATA GENMASK(7, 0) 33 #define HISI_I2C_SS_SCL_HCNT 0x0010 34 #define HISI_I2C_SS_SCL_LCNT 0x0014 35 #define HISI_I2C_FS_SCL_HCNT 0x0018 36 #define HISI_I2C_FS_SCL_LCNT 0x001c 37 #define HISI_I2C_HS_SCL_HCNT 0x0020 38 #define HISI_I2C_HS_SCL_LCNT 0x0024 39 #define HISI_I2C_FIFO_CTRL 0x0028 40 #define HISI_I2C_FIFO_RX_CLR BIT(0) 41 #define HISI_I2C_FIFO_TX_CLR BIT(1) 42 #define HISI_I2C_FIFO_RX_AF_THRESH GENMASK(7, 2) 43 #define HISI_I2C_FIFO_TX_AE_THRESH GENMASK(13, 8) 44 #define HISI_I2C_FIFO_STATE 0x002c 45 #define HISI_I2C_FIFO_STATE_RX_RERR BIT(0) 46 #define HISI_I2C_FIFO_STATE_RX_WERR BIT(1) 47 #define HISI_I2C_FIFO_STATE_RX_EMPTY BIT(3) 48 #define HISI_I2C_FIFO_STATE_TX_RERR BIT(6) 49 #define HISI_I2C_FIFO_STATE_TX_WERR BIT(7) 50 #define HISI_I2C_FIFO_STATE_TX_FULL BIT(11) 51 #define HISI_I2C_SDA_HOLD 0x0030 52 #define HISI_I2C_SDA_HOLD_TX GENMASK(15, 0) 53 #define HISI_I2C_SDA_HOLD_RX GENMASK(23, 16) 54 #define HISI_I2C_FS_SPK_LEN 0x0038 55 #define HISI_I2C_FS_SPK_LEN_CNT GENMASK(7, 0) 56 #define HISI_I2C_HS_SPK_LEN 0x003c 57 #define HISI_I2C_HS_SPK_LEN_CNT GENMASK(7, 0) 58 #define HISI_I2C_INT_MSTAT 0x0044 59 #define HISI_I2C_INT_CLR 0x0048 60 #define HISI_I2C_INT_MASK 0x004C 61 #define HISI_I2C_TRANS_STATE 0x0050 62 #define HISI_I2C_TRANS_ERR 0x0054 63 #define HISI_I2C_VERSION 0x0058 64 65 #define HISI_I2C_INT_ALL GENMASK(4, 0) 66 #define HISI_I2C_INT_TRANS_CPLT BIT(0) 67 #define HISI_I2C_INT_TRANS_ERR BIT(1) 68 #define HISI_I2C_INT_FIFO_ERR BIT(2) 69 #define HISI_I2C_INT_RX_FULL BIT(3) 70 #define HISI_I2C_INT_TX_EMPTY BIT(4) 71 #define HISI_I2C_INT_ERR \ 72 (HISI_I2C_INT_TRANS_ERR | HISI_I2C_INT_FIFO_ERR) 73 74 #define HISI_I2C_STD_SPEED_MODE 0 75 #define HISI_I2C_FAST_SPEED_MODE 1 76 #define HISI_I2C_HIGH_SPEED_MODE 2 77 78 #define HISI_I2C_TX_FIFO_DEPTH 64 79 #define HISI_I2C_RX_FIFO_DEPTH 64 80 #define HISI_I2C_TX_F_AE_THRESH 1 81 #define HISI_I2C_RX_F_AF_THRESH 60 82 83 #define HZ_PER_KHZ 1000 84 85 #define NSEC_TO_CYCLES(ns, clk_rate_khz) \ 86 DIV_ROUND_UP_ULL((clk_rate_khz) * (ns), NSEC_PER_MSEC) 87 88 struct hisi_i2c_controller { 89 struct i2c_adapter adapter; 90 void __iomem *iobase; 91 struct device *dev; 92 int irq; 93 94 /* Intermediates for recording the transfer process */ 95 struct completion *completion; 96 struct i2c_msg *msgs; 97 int msg_num; 98 int msg_tx_idx; 99 int buf_tx_idx; 100 int msg_rx_idx; 101 int buf_rx_idx; 102 u16 tar_addr; 103 u32 xfer_err; 104 105 /* I2C bus configuration */ 106 struct i2c_timings t; 107 u32 clk_rate_khz; 108 u32 spk_len; 109 }; 110 111 static void hisi_i2c_enable_int(struct hisi_i2c_controller *ctlr, u32 mask) 112 { 113 writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_MASK); 114 } 115 116 static void hisi_i2c_disable_int(struct hisi_i2c_controller *ctlr, u32 mask) 117 { 118 writel_relaxed((~mask) & HISI_I2C_INT_ALL, ctlr->iobase + HISI_I2C_INT_MASK); 119 } 120 121 static void hisi_i2c_clear_int(struct hisi_i2c_controller *ctlr, u32 mask) 122 { 123 writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_CLR); 124 } 125 126 static void hisi_i2c_handle_errors(struct hisi_i2c_controller *ctlr) 127 { 128 u32 int_err = ctlr->xfer_err, reg; 129 130 if (int_err & HISI_I2C_INT_FIFO_ERR) { 131 reg = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); 132 133 if (reg & HISI_I2C_FIFO_STATE_RX_RERR) 134 dev_err(ctlr->dev, "rx fifo error read\n"); 135 136 if (reg & HISI_I2C_FIFO_STATE_RX_WERR) 137 dev_err(ctlr->dev, "rx fifo error write\n"); 138 139 if (reg & HISI_I2C_FIFO_STATE_TX_RERR) 140 dev_err(ctlr->dev, "tx fifo error read\n"); 141 142 if (reg & HISI_I2C_FIFO_STATE_TX_WERR) 143 dev_err(ctlr->dev, "tx fifo error write\n"); 144 } 145 } 146 147 static int hisi_i2c_start_xfer(struct hisi_i2c_controller *ctlr) 148 { 149 struct i2c_msg *msg = ctlr->msgs; 150 u32 reg; 151 152 reg = readl(ctlr->iobase + HISI_I2C_FRAME_CTRL); 153 reg &= ~HISI_I2C_FRAME_CTRL_ADDR_TEN; 154 if (msg->flags & I2C_M_TEN) 155 reg |= HISI_I2C_FRAME_CTRL_ADDR_TEN; 156 writel(reg, ctlr->iobase + HISI_I2C_FRAME_CTRL); 157 158 reg = readl(ctlr->iobase + HISI_I2C_SLV_ADDR); 159 reg &= ~HISI_I2C_SLV_ADDR_VAL; 160 reg |= FIELD_PREP(HISI_I2C_SLV_ADDR_VAL, msg->addr); 161 writel(reg, ctlr->iobase + HISI_I2C_SLV_ADDR); 162 163 reg = readl(ctlr->iobase + HISI_I2C_FIFO_CTRL); 164 reg |= HISI_I2C_FIFO_RX_CLR | HISI_I2C_FIFO_TX_CLR; 165 writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL); 166 reg &= ~(HISI_I2C_FIFO_RX_CLR | HISI_I2C_FIFO_TX_CLR); 167 writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL); 168 169 hisi_i2c_clear_int(ctlr, HISI_I2C_INT_ALL); 170 hisi_i2c_enable_int(ctlr, HISI_I2C_INT_ALL); 171 172 return 0; 173 } 174 175 static void hisi_i2c_reset_xfer(struct hisi_i2c_controller *ctlr) 176 { 177 ctlr->msg_num = 0; 178 ctlr->xfer_err = 0; 179 ctlr->msg_tx_idx = 0; 180 ctlr->msg_rx_idx = 0; 181 ctlr->buf_tx_idx = 0; 182 ctlr->buf_rx_idx = 0; 183 } 184 185 /* 186 * Initialize the transfer information and start the I2C bus transfer. 187 * We only configure the transfer and do some pre/post works here, and 188 * wait for the transfer done. The major transfer process is performed 189 * in the IRQ handler. 190 */ 191 static int hisi_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, 192 int num) 193 { 194 struct hisi_i2c_controller *ctlr = i2c_get_adapdata(adap); 195 DECLARE_COMPLETION_ONSTACK(done); 196 int ret = num; 197 198 hisi_i2c_reset_xfer(ctlr); 199 ctlr->completion = &done; 200 ctlr->msg_num = num; 201 ctlr->msgs = msgs; 202 203 hisi_i2c_start_xfer(ctlr); 204 205 if (!wait_for_completion_timeout(ctlr->completion, adap->timeout)) { 206 hisi_i2c_disable_int(ctlr, HISI_I2C_INT_ALL); 207 synchronize_irq(ctlr->irq); 208 i2c_recover_bus(&ctlr->adapter); 209 dev_err(ctlr->dev, "bus transfer timeout\n"); 210 ret = -EIO; 211 } 212 213 if (ctlr->xfer_err) { 214 hisi_i2c_handle_errors(ctlr); 215 ret = -EIO; 216 } 217 218 hisi_i2c_reset_xfer(ctlr); 219 ctlr->completion = NULL; 220 221 return ret; 222 } 223 224 static u32 hisi_i2c_functionality(struct i2c_adapter *adap) 225 { 226 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL; 227 } 228 229 static const struct i2c_algorithm hisi_i2c_algo = { 230 .master_xfer = hisi_i2c_master_xfer, 231 .functionality = hisi_i2c_functionality, 232 }; 233 234 static int hisi_i2c_read_rx_fifo(struct hisi_i2c_controller *ctlr) 235 { 236 struct i2c_msg *cur_msg; 237 u32 fifo_state; 238 239 while (ctlr->msg_rx_idx < ctlr->msg_num) { 240 cur_msg = ctlr->msgs + ctlr->msg_rx_idx; 241 242 if (!(cur_msg->flags & I2C_M_RD)) { 243 ctlr->msg_rx_idx++; 244 continue; 245 } 246 247 fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); 248 while (!(fifo_state & HISI_I2C_FIFO_STATE_RX_EMPTY) && 249 ctlr->buf_rx_idx < cur_msg->len) { 250 cur_msg->buf[ctlr->buf_rx_idx++] = readl(ctlr->iobase + HISI_I2C_RXDATA); 251 fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); 252 } 253 254 if (ctlr->buf_rx_idx == cur_msg->len) { 255 ctlr->buf_rx_idx = 0; 256 ctlr->msg_rx_idx++; 257 } 258 259 if (fifo_state & HISI_I2C_FIFO_STATE_RX_EMPTY) 260 break; 261 } 262 263 return 0; 264 } 265 266 static void hisi_i2c_xfer_msg(struct hisi_i2c_controller *ctlr) 267 { 268 int max_write = HISI_I2C_TX_FIFO_DEPTH; 269 bool need_restart = false, last_msg; 270 struct i2c_msg *cur_msg; 271 u32 cmd, fifo_state; 272 273 while (ctlr->msg_tx_idx < ctlr->msg_num) { 274 cur_msg = ctlr->msgs + ctlr->msg_tx_idx; 275 last_msg = (ctlr->msg_tx_idx == ctlr->msg_num - 1); 276 277 /* Signal the SR bit when we start transferring a new message */ 278 if (ctlr->msg_tx_idx && !ctlr->buf_tx_idx) 279 need_restart = true; 280 281 fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); 282 while (!(fifo_state & HISI_I2C_FIFO_STATE_TX_FULL) && 283 ctlr->buf_tx_idx < cur_msg->len && max_write) { 284 cmd = 0; 285 286 if (need_restart) { 287 cmd |= HISI_I2C_CMD_TXDATA_SR_EN; 288 need_restart = false; 289 } 290 291 /* Signal the STOP bit at the last frame of the last message */ 292 if (ctlr->buf_tx_idx == cur_msg->len - 1 && last_msg) 293 cmd |= HISI_I2C_CMD_TXDATA_P_EN; 294 295 if (cur_msg->flags & I2C_M_RD) 296 cmd |= HISI_I2C_CMD_TXDATA_RW; 297 else 298 cmd |= FIELD_PREP(HISI_I2C_CMD_TXDATA_DATA, 299 cur_msg->buf[ctlr->buf_tx_idx]); 300 301 writel(cmd, ctlr->iobase + HISI_I2C_CMD_TXDATA); 302 ctlr->buf_tx_idx++; 303 max_write--; 304 305 fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); 306 } 307 308 /* Update the transfer index after per message transfer is done. */ 309 if (ctlr->buf_tx_idx == cur_msg->len) { 310 ctlr->buf_tx_idx = 0; 311 ctlr->msg_tx_idx++; 312 } 313 314 if ((fifo_state & HISI_I2C_FIFO_STATE_TX_FULL) || 315 max_write == 0) 316 break; 317 } 318 } 319 320 static irqreturn_t hisi_i2c_irq(int irq, void *context) 321 { 322 struct hisi_i2c_controller *ctlr = context; 323 u32 int_stat; 324 325 int_stat = readl(ctlr->iobase + HISI_I2C_INT_MSTAT); 326 hisi_i2c_clear_int(ctlr, int_stat); 327 if (!(int_stat & HISI_I2C_INT_ALL)) 328 return IRQ_NONE; 329 330 if (int_stat & HISI_I2C_INT_TX_EMPTY) 331 hisi_i2c_xfer_msg(ctlr); 332 333 if (int_stat & HISI_I2C_INT_ERR) { 334 ctlr->xfer_err = int_stat; 335 goto out; 336 } 337 338 /* Drain the rx fifo before finish the transfer */ 339 if (int_stat & (HISI_I2C_INT_TRANS_CPLT | HISI_I2C_INT_RX_FULL)) 340 hisi_i2c_read_rx_fifo(ctlr); 341 342 out: 343 if (int_stat & HISI_I2C_INT_TRANS_CPLT || ctlr->xfer_err) { 344 hisi_i2c_disable_int(ctlr, HISI_I2C_INT_ALL); 345 hisi_i2c_clear_int(ctlr, HISI_I2C_INT_ALL); 346 complete(ctlr->completion); 347 } 348 349 return IRQ_HANDLED; 350 } 351 352 /* 353 * Helper function for calculating and configuring the HIGH and LOW 354 * periods of SCL clock. The caller will pass the ratio of the 355 * counts (divide / divisor) according to the target speed mode, 356 * and the target registers. 357 */ 358 static void hisi_i2c_set_scl(struct hisi_i2c_controller *ctlr, 359 u32 divide, u32 divisor, 360 u32 reg_hcnt, u32 reg_lcnt) 361 { 362 u32 total_cnt, t_scl_hcnt, t_scl_lcnt, scl_fall_cnt, scl_rise_cnt; 363 u32 scl_hcnt, scl_lcnt; 364 365 /* Total SCL clock cycles per speed period */ 366 total_cnt = DIV_ROUND_UP_ULL(ctlr->clk_rate_khz * HZ_PER_KHZ, ctlr->t.bus_freq_hz); 367 /* Total HIGH level SCL clock cycles including edges */ 368 t_scl_hcnt = DIV_ROUND_UP_ULL(total_cnt * divide, divisor); 369 /* Total LOW level SCL clock cycles including edges */ 370 t_scl_lcnt = total_cnt - t_scl_hcnt; 371 /* Fall edge SCL clock cycles */ 372 scl_fall_cnt = NSEC_TO_CYCLES(ctlr->t.scl_fall_ns, ctlr->clk_rate_khz); 373 /* Rise edge SCL clock cycles */ 374 scl_rise_cnt = NSEC_TO_CYCLES(ctlr->t.scl_rise_ns, ctlr->clk_rate_khz); 375 376 /* Calculated HIGH and LOW periods of SCL clock */ 377 scl_hcnt = t_scl_hcnt - ctlr->spk_len - 7 - scl_fall_cnt; 378 scl_lcnt = t_scl_lcnt - 1 - scl_rise_cnt; 379 380 writel(scl_hcnt, ctlr->iobase + reg_hcnt); 381 writel(scl_lcnt, ctlr->iobase + reg_lcnt); 382 } 383 384 static void hisi_i2c_configure_bus(struct hisi_i2c_controller *ctlr) 385 { 386 u32 reg, sda_hold_cnt, speed_mode; 387 388 i2c_parse_fw_timings(ctlr->dev, &ctlr->t, true); 389 ctlr->spk_len = NSEC_TO_CYCLES(ctlr->t.digital_filter_width_ns, ctlr->clk_rate_khz); 390 391 switch (ctlr->t.bus_freq_hz) { 392 case I2C_MAX_FAST_MODE_FREQ: 393 speed_mode = HISI_I2C_FAST_SPEED_MODE; 394 hisi_i2c_set_scl(ctlr, 26, 76, HISI_I2C_FS_SCL_HCNT, HISI_I2C_FS_SCL_LCNT); 395 break; 396 case I2C_MAX_HIGH_SPEED_MODE_FREQ: 397 speed_mode = HISI_I2C_HIGH_SPEED_MODE; 398 hisi_i2c_set_scl(ctlr, 6, 22, HISI_I2C_HS_SCL_HCNT, HISI_I2C_HS_SCL_LCNT); 399 break; 400 case I2C_MAX_STANDARD_MODE_FREQ: 401 default: 402 speed_mode = HISI_I2C_STD_SPEED_MODE; 403 404 /* For default condition force the bus speed to standard mode. */ 405 ctlr->t.bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ; 406 hisi_i2c_set_scl(ctlr, 40, 87, HISI_I2C_SS_SCL_HCNT, HISI_I2C_SS_SCL_LCNT); 407 break; 408 } 409 410 reg = readl(ctlr->iobase + HISI_I2C_FRAME_CTRL); 411 reg &= ~HISI_I2C_FRAME_CTRL_SPEED_MODE; 412 reg |= FIELD_PREP(HISI_I2C_FRAME_CTRL_SPEED_MODE, speed_mode); 413 writel(reg, ctlr->iobase + HISI_I2C_FRAME_CTRL); 414 415 sda_hold_cnt = NSEC_TO_CYCLES(ctlr->t.sda_hold_ns, ctlr->clk_rate_khz); 416 417 reg = FIELD_PREP(HISI_I2C_SDA_HOLD_TX, sda_hold_cnt); 418 writel(reg, ctlr->iobase + HISI_I2C_SDA_HOLD); 419 420 writel(ctlr->spk_len, ctlr->iobase + HISI_I2C_FS_SPK_LEN); 421 422 reg = FIELD_PREP(HISI_I2C_FIFO_RX_AF_THRESH, HISI_I2C_RX_F_AF_THRESH); 423 reg |= FIELD_PREP(HISI_I2C_FIFO_TX_AE_THRESH, HISI_I2C_TX_F_AE_THRESH); 424 writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL); 425 } 426 427 static int hisi_i2c_probe(struct platform_device *pdev) 428 { 429 struct hisi_i2c_controller *ctlr; 430 struct device *dev = &pdev->dev; 431 struct i2c_adapter *adapter; 432 u64 clk_rate_hz; 433 u32 hw_version; 434 int ret; 435 436 ctlr = devm_kzalloc(dev, sizeof(*ctlr), GFP_KERNEL); 437 if (!ctlr) 438 return -ENOMEM; 439 440 ctlr->iobase = devm_platform_ioremap_resource(pdev, 0); 441 if (IS_ERR(ctlr->iobase)) 442 return PTR_ERR(ctlr->iobase); 443 444 ctlr->irq = platform_get_irq(pdev, 0); 445 if (ctlr->irq < 0) 446 return ctlr->irq; 447 448 ctlr->dev = dev; 449 450 hisi_i2c_disable_int(ctlr, HISI_I2C_INT_ALL); 451 452 ret = devm_request_irq(dev, ctlr->irq, hisi_i2c_irq, 0, "hisi-i2c", ctlr); 453 if (ret) { 454 dev_err(dev, "failed to request irq handler, ret = %d\n", ret); 455 return ret; 456 } 457 458 ret = device_property_read_u64(dev, "clk_rate", &clk_rate_hz); 459 if (ret) { 460 dev_err(dev, "failed to get clock frequency, ret = %d\n", ret); 461 return ret; 462 } 463 464 ctlr->clk_rate_khz = DIV_ROUND_UP_ULL(clk_rate_hz, HZ_PER_KHZ); 465 466 hisi_i2c_configure_bus(ctlr); 467 468 adapter = &ctlr->adapter; 469 snprintf(adapter->name, sizeof(adapter->name), 470 "HiSilicon I2C Controller %s", dev_name(dev)); 471 adapter->owner = THIS_MODULE; 472 adapter->algo = &hisi_i2c_algo; 473 adapter->dev.parent = dev; 474 i2c_set_adapdata(adapter, ctlr); 475 476 ret = devm_i2c_add_adapter(dev, adapter); 477 if (ret) 478 return ret; 479 480 hw_version = readl(ctlr->iobase + HISI_I2C_VERSION); 481 dev_info(ctlr->dev, "speed mode is %s. hw version 0x%x\n", 482 i2c_freq_mode_string(ctlr->t.bus_freq_hz), hw_version); 483 484 return 0; 485 } 486 487 static const struct acpi_device_id hisi_i2c_acpi_ids[] = { 488 { "HISI03D1", 0 }, 489 { } 490 }; 491 MODULE_DEVICE_TABLE(acpi, hisi_i2c_acpi_ids); 492 493 static struct platform_driver hisi_i2c_driver = { 494 .probe = hisi_i2c_probe, 495 .driver = { 496 .name = "hisi-i2c", 497 .acpi_match_table = hisi_i2c_acpi_ids, 498 }, 499 }; 500 module_platform_driver(hisi_i2c_driver); 501 502 MODULE_AUTHOR("Yicong Yang <yangyicong@hisilicon.com>"); 503 MODULE_DESCRIPTION("HiSilicon I2C Controller Driver"); 504 MODULE_LICENSE("GPL"); 505