1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * HiSilicon I2C Controller Driver for Kunpeng SoC 4 * 5 * Copyright (c) 2021 HiSilicon Technologies Co., Ltd. 6 */ 7 8 #include <linux/bits.h> 9 #include <linux/bitfield.h> 10 #include <linux/clk.h> 11 #include <linux/completion.h> 12 #include <linux/i2c.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/mod_devicetable.h> 17 #include <linux/platform_device.h> 18 #include <linux/property.h> 19 #include <linux/units.h> 20 21 #define HISI_I2C_FRAME_CTRL 0x0000 22 #define HISI_I2C_FRAME_CTRL_SPEED_MODE GENMASK(1, 0) 23 #define HISI_I2C_FRAME_CTRL_ADDR_TEN BIT(2) 24 #define HISI_I2C_SLV_ADDR 0x0004 25 #define HISI_I2C_SLV_ADDR_VAL GENMASK(9, 0) 26 #define HISI_I2C_SLV_ADDR_GC_S_MODE BIT(10) 27 #define HISI_I2C_SLV_ADDR_GC_S_EN BIT(11) 28 #define HISI_I2C_CMD_TXDATA 0x0008 29 #define HISI_I2C_CMD_TXDATA_DATA GENMASK(7, 0) 30 #define HISI_I2C_CMD_TXDATA_RW BIT(8) 31 #define HISI_I2C_CMD_TXDATA_P_EN BIT(9) 32 #define HISI_I2C_CMD_TXDATA_SR_EN BIT(10) 33 #define HISI_I2C_RXDATA 0x000c 34 #define HISI_I2C_RXDATA_DATA GENMASK(7, 0) 35 #define HISI_I2C_SS_SCL_HCNT 0x0010 36 #define HISI_I2C_SS_SCL_LCNT 0x0014 37 #define HISI_I2C_FS_SCL_HCNT 0x0018 38 #define HISI_I2C_FS_SCL_LCNT 0x001c 39 #define HISI_I2C_HS_SCL_HCNT 0x0020 40 #define HISI_I2C_HS_SCL_LCNT 0x0024 41 #define HISI_I2C_FIFO_CTRL 0x0028 42 #define HISI_I2C_FIFO_RX_CLR BIT(0) 43 #define HISI_I2C_FIFO_TX_CLR BIT(1) 44 #define HISI_I2C_FIFO_RX_AF_THRESH GENMASK(7, 2) 45 #define HISI_I2C_FIFO_TX_AE_THRESH GENMASK(13, 8) 46 #define HISI_I2C_FIFO_STATE 0x002c 47 #define HISI_I2C_FIFO_STATE_RX_RERR BIT(0) 48 #define HISI_I2C_FIFO_STATE_RX_WERR BIT(1) 49 #define HISI_I2C_FIFO_STATE_RX_EMPTY BIT(3) 50 #define HISI_I2C_FIFO_STATE_TX_RERR BIT(6) 51 #define HISI_I2C_FIFO_STATE_TX_WERR BIT(7) 52 #define HISI_I2C_FIFO_STATE_TX_FULL BIT(11) 53 #define HISI_I2C_SDA_HOLD 0x0030 54 #define HISI_I2C_SDA_HOLD_TX GENMASK(15, 0) 55 #define HISI_I2C_SDA_HOLD_RX GENMASK(23, 16) 56 #define HISI_I2C_FS_SPK_LEN 0x0038 57 #define HISI_I2C_FS_SPK_LEN_CNT GENMASK(7, 0) 58 #define HISI_I2C_HS_SPK_LEN 0x003c 59 #define HISI_I2C_HS_SPK_LEN_CNT GENMASK(7, 0) 60 #define HISI_I2C_INT_MSTAT 0x0044 61 #define HISI_I2C_INT_CLR 0x0048 62 #define HISI_I2C_INT_MASK 0x004C 63 #define HISI_I2C_TRANS_STATE 0x0050 64 #define HISI_I2C_TRANS_ERR 0x0054 65 #define HISI_I2C_VERSION 0x0058 66 67 #define HISI_I2C_INT_ALL GENMASK(4, 0) 68 #define HISI_I2C_INT_TRANS_CPLT BIT(0) 69 #define HISI_I2C_INT_TRANS_ERR BIT(1) 70 #define HISI_I2C_INT_FIFO_ERR BIT(2) 71 #define HISI_I2C_INT_RX_FULL BIT(3) 72 #define HISI_I2C_INT_TX_EMPTY BIT(4) 73 #define HISI_I2C_INT_ERR \ 74 (HISI_I2C_INT_TRANS_ERR | HISI_I2C_INT_FIFO_ERR) 75 76 #define HISI_I2C_STD_SPEED_MODE 0 77 #define HISI_I2C_FAST_SPEED_MODE 1 78 #define HISI_I2C_HIGH_SPEED_MODE 2 79 80 #define HISI_I2C_TX_FIFO_DEPTH 64 81 #define HISI_I2C_RX_FIFO_DEPTH 64 82 #define HISI_I2C_TX_F_AE_THRESH 1 83 #define HISI_I2C_RX_F_AF_THRESH 60 84 85 #define NSEC_TO_CYCLES(ns, clk_rate_khz) \ 86 DIV_ROUND_UP_ULL((clk_rate_khz) * (ns), NSEC_PER_MSEC) 87 88 struct hisi_i2c_controller { 89 struct i2c_adapter adapter; 90 void __iomem *iobase; 91 struct device *dev; 92 struct clk *clk; 93 int irq; 94 95 /* Intermediates for recording the transfer process */ 96 struct completion *completion; 97 struct i2c_msg *msgs; 98 int msg_num; 99 int msg_tx_idx; 100 int buf_tx_idx; 101 int msg_rx_idx; 102 int buf_rx_idx; 103 u16 tar_addr; 104 u32 xfer_err; 105 106 /* I2C bus configuration */ 107 struct i2c_timings t; 108 u32 clk_rate_khz; 109 u32 spk_len; 110 }; 111 112 static void hisi_i2c_enable_int(struct hisi_i2c_controller *ctlr, u32 mask) 113 { 114 writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_MASK); 115 } 116 117 static void hisi_i2c_disable_int(struct hisi_i2c_controller *ctlr, u32 mask) 118 { 119 writel_relaxed((~mask) & HISI_I2C_INT_ALL, ctlr->iobase + HISI_I2C_INT_MASK); 120 } 121 122 static void hisi_i2c_clear_int(struct hisi_i2c_controller *ctlr, u32 mask) 123 { 124 writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_CLR); 125 } 126 127 static void hisi_i2c_handle_errors(struct hisi_i2c_controller *ctlr) 128 { 129 u32 int_err = ctlr->xfer_err, reg; 130 131 if (int_err & HISI_I2C_INT_FIFO_ERR) { 132 reg = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); 133 134 if (reg & HISI_I2C_FIFO_STATE_RX_RERR) 135 dev_err(ctlr->dev, "rx fifo error read\n"); 136 137 if (reg & HISI_I2C_FIFO_STATE_RX_WERR) 138 dev_err(ctlr->dev, "rx fifo error write\n"); 139 140 if (reg & HISI_I2C_FIFO_STATE_TX_RERR) 141 dev_err(ctlr->dev, "tx fifo error read\n"); 142 143 if (reg & HISI_I2C_FIFO_STATE_TX_WERR) 144 dev_err(ctlr->dev, "tx fifo error write\n"); 145 } 146 } 147 148 static int hisi_i2c_start_xfer(struct hisi_i2c_controller *ctlr) 149 { 150 struct i2c_msg *msg = ctlr->msgs; 151 u32 reg; 152 153 reg = readl(ctlr->iobase + HISI_I2C_FRAME_CTRL); 154 reg &= ~HISI_I2C_FRAME_CTRL_ADDR_TEN; 155 if (msg->flags & I2C_M_TEN) 156 reg |= HISI_I2C_FRAME_CTRL_ADDR_TEN; 157 writel(reg, ctlr->iobase + HISI_I2C_FRAME_CTRL); 158 159 reg = readl(ctlr->iobase + HISI_I2C_SLV_ADDR); 160 reg &= ~HISI_I2C_SLV_ADDR_VAL; 161 reg |= FIELD_PREP(HISI_I2C_SLV_ADDR_VAL, msg->addr); 162 writel(reg, ctlr->iobase + HISI_I2C_SLV_ADDR); 163 164 reg = readl(ctlr->iobase + HISI_I2C_FIFO_CTRL); 165 reg |= HISI_I2C_FIFO_RX_CLR | HISI_I2C_FIFO_TX_CLR; 166 writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL); 167 reg &= ~(HISI_I2C_FIFO_RX_CLR | HISI_I2C_FIFO_TX_CLR); 168 writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL); 169 170 hisi_i2c_clear_int(ctlr, HISI_I2C_INT_ALL); 171 hisi_i2c_enable_int(ctlr, HISI_I2C_INT_ALL); 172 173 return 0; 174 } 175 176 static void hisi_i2c_reset_xfer(struct hisi_i2c_controller *ctlr) 177 { 178 ctlr->msg_num = 0; 179 ctlr->xfer_err = 0; 180 ctlr->msg_tx_idx = 0; 181 ctlr->msg_rx_idx = 0; 182 ctlr->buf_tx_idx = 0; 183 ctlr->buf_rx_idx = 0; 184 } 185 186 /* 187 * Initialize the transfer information and start the I2C bus transfer. 188 * We only configure the transfer and do some pre/post works here, and 189 * wait for the transfer done. The major transfer process is performed 190 * in the IRQ handler. 191 */ 192 static int hisi_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, 193 int num) 194 { 195 struct hisi_i2c_controller *ctlr = i2c_get_adapdata(adap); 196 DECLARE_COMPLETION_ONSTACK(done); 197 int ret = num; 198 199 hisi_i2c_reset_xfer(ctlr); 200 ctlr->completion = &done; 201 ctlr->msg_num = num; 202 ctlr->msgs = msgs; 203 204 hisi_i2c_start_xfer(ctlr); 205 206 if (!wait_for_completion_timeout(ctlr->completion, adap->timeout)) { 207 hisi_i2c_disable_int(ctlr, HISI_I2C_INT_ALL); 208 synchronize_irq(ctlr->irq); 209 i2c_recover_bus(&ctlr->adapter); 210 dev_err(ctlr->dev, "bus transfer timeout\n"); 211 ret = -EIO; 212 } 213 214 if (ctlr->xfer_err) { 215 hisi_i2c_handle_errors(ctlr); 216 ret = -EIO; 217 } 218 219 hisi_i2c_reset_xfer(ctlr); 220 ctlr->completion = NULL; 221 222 return ret; 223 } 224 225 static u32 hisi_i2c_functionality(struct i2c_adapter *adap) 226 { 227 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL; 228 } 229 230 static const struct i2c_algorithm hisi_i2c_algo = { 231 .master_xfer = hisi_i2c_master_xfer, 232 .functionality = hisi_i2c_functionality, 233 }; 234 235 static int hisi_i2c_read_rx_fifo(struct hisi_i2c_controller *ctlr) 236 { 237 struct i2c_msg *cur_msg; 238 u32 fifo_state; 239 240 while (ctlr->msg_rx_idx < ctlr->msg_num) { 241 cur_msg = ctlr->msgs + ctlr->msg_rx_idx; 242 243 if (!(cur_msg->flags & I2C_M_RD)) { 244 ctlr->msg_rx_idx++; 245 continue; 246 } 247 248 fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); 249 while (!(fifo_state & HISI_I2C_FIFO_STATE_RX_EMPTY) && 250 ctlr->buf_rx_idx < cur_msg->len) { 251 cur_msg->buf[ctlr->buf_rx_idx++] = readl(ctlr->iobase + HISI_I2C_RXDATA); 252 fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); 253 } 254 255 if (ctlr->buf_rx_idx == cur_msg->len) { 256 ctlr->buf_rx_idx = 0; 257 ctlr->msg_rx_idx++; 258 } 259 260 if (fifo_state & HISI_I2C_FIFO_STATE_RX_EMPTY) 261 break; 262 } 263 264 return 0; 265 } 266 267 static void hisi_i2c_xfer_msg(struct hisi_i2c_controller *ctlr) 268 { 269 int max_write = HISI_I2C_TX_FIFO_DEPTH; 270 bool need_restart = false, last_msg; 271 struct i2c_msg *cur_msg; 272 u32 cmd, fifo_state; 273 274 while (ctlr->msg_tx_idx < ctlr->msg_num) { 275 cur_msg = ctlr->msgs + ctlr->msg_tx_idx; 276 last_msg = (ctlr->msg_tx_idx == ctlr->msg_num - 1); 277 278 /* Signal the SR bit when we start transferring a new message */ 279 if (ctlr->msg_tx_idx && !ctlr->buf_tx_idx) 280 need_restart = true; 281 282 fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); 283 while (!(fifo_state & HISI_I2C_FIFO_STATE_TX_FULL) && 284 ctlr->buf_tx_idx < cur_msg->len && max_write) { 285 cmd = 0; 286 287 if (need_restart) { 288 cmd |= HISI_I2C_CMD_TXDATA_SR_EN; 289 need_restart = false; 290 } 291 292 /* Signal the STOP bit at the last frame of the last message */ 293 if (ctlr->buf_tx_idx == cur_msg->len - 1 && last_msg) 294 cmd |= HISI_I2C_CMD_TXDATA_P_EN; 295 296 if (cur_msg->flags & I2C_M_RD) 297 cmd |= HISI_I2C_CMD_TXDATA_RW; 298 else 299 cmd |= FIELD_PREP(HISI_I2C_CMD_TXDATA_DATA, 300 cur_msg->buf[ctlr->buf_tx_idx]); 301 302 writel(cmd, ctlr->iobase + HISI_I2C_CMD_TXDATA); 303 ctlr->buf_tx_idx++; 304 max_write--; 305 306 fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); 307 } 308 309 /* Update the transfer index after per message transfer is done. */ 310 if (ctlr->buf_tx_idx == cur_msg->len) { 311 ctlr->buf_tx_idx = 0; 312 ctlr->msg_tx_idx++; 313 } 314 315 if ((fifo_state & HISI_I2C_FIFO_STATE_TX_FULL) || 316 max_write == 0) 317 break; 318 } 319 } 320 321 static irqreturn_t hisi_i2c_irq(int irq, void *context) 322 { 323 struct hisi_i2c_controller *ctlr = context; 324 u32 int_stat; 325 326 int_stat = readl(ctlr->iobase + HISI_I2C_INT_MSTAT); 327 hisi_i2c_clear_int(ctlr, int_stat); 328 if (!(int_stat & HISI_I2C_INT_ALL)) 329 return IRQ_NONE; 330 331 if (int_stat & HISI_I2C_INT_TX_EMPTY) 332 hisi_i2c_xfer_msg(ctlr); 333 334 if (int_stat & HISI_I2C_INT_ERR) { 335 ctlr->xfer_err = int_stat; 336 goto out; 337 } 338 339 /* Drain the rx fifo before finish the transfer */ 340 if (int_stat & (HISI_I2C_INT_TRANS_CPLT | HISI_I2C_INT_RX_FULL)) 341 hisi_i2c_read_rx_fifo(ctlr); 342 343 out: 344 if (int_stat & HISI_I2C_INT_TRANS_CPLT || ctlr->xfer_err) { 345 hisi_i2c_disable_int(ctlr, HISI_I2C_INT_ALL); 346 hisi_i2c_clear_int(ctlr, HISI_I2C_INT_ALL); 347 complete(ctlr->completion); 348 } 349 350 return IRQ_HANDLED; 351 } 352 353 /* 354 * Helper function for calculating and configuring the HIGH and LOW 355 * periods of SCL clock. The caller will pass the ratio of the 356 * counts (divide / divisor) according to the target speed mode, 357 * and the target registers. 358 */ 359 static void hisi_i2c_set_scl(struct hisi_i2c_controller *ctlr, 360 u32 divide, u32 divisor, 361 u32 reg_hcnt, u32 reg_lcnt) 362 { 363 u32 total_cnt, t_scl_hcnt, t_scl_lcnt, scl_fall_cnt, scl_rise_cnt; 364 u32 scl_hcnt, scl_lcnt; 365 366 /* Total SCL clock cycles per speed period */ 367 total_cnt = DIV_ROUND_UP_ULL(ctlr->clk_rate_khz * HZ_PER_KHZ, ctlr->t.bus_freq_hz); 368 /* Total HIGH level SCL clock cycles including edges */ 369 t_scl_hcnt = DIV_ROUND_UP_ULL(total_cnt * divide, divisor); 370 /* Total LOW level SCL clock cycles including edges */ 371 t_scl_lcnt = total_cnt - t_scl_hcnt; 372 /* Fall edge SCL clock cycles */ 373 scl_fall_cnt = NSEC_TO_CYCLES(ctlr->t.scl_fall_ns, ctlr->clk_rate_khz); 374 /* Rise edge SCL clock cycles */ 375 scl_rise_cnt = NSEC_TO_CYCLES(ctlr->t.scl_rise_ns, ctlr->clk_rate_khz); 376 377 /* Calculated HIGH and LOW periods of SCL clock */ 378 scl_hcnt = t_scl_hcnt - ctlr->spk_len - 7 - scl_fall_cnt; 379 scl_lcnt = t_scl_lcnt - 1 - scl_rise_cnt; 380 381 writel(scl_hcnt, ctlr->iobase + reg_hcnt); 382 writel(scl_lcnt, ctlr->iobase + reg_lcnt); 383 } 384 385 static void hisi_i2c_configure_bus(struct hisi_i2c_controller *ctlr) 386 { 387 u32 reg, sda_hold_cnt, speed_mode; 388 389 i2c_parse_fw_timings(ctlr->dev, &ctlr->t, true); 390 ctlr->spk_len = NSEC_TO_CYCLES(ctlr->t.digital_filter_width_ns, ctlr->clk_rate_khz); 391 392 switch (ctlr->t.bus_freq_hz) { 393 case I2C_MAX_FAST_MODE_FREQ: 394 speed_mode = HISI_I2C_FAST_SPEED_MODE; 395 hisi_i2c_set_scl(ctlr, 26, 76, HISI_I2C_FS_SCL_HCNT, HISI_I2C_FS_SCL_LCNT); 396 break; 397 case I2C_MAX_HIGH_SPEED_MODE_FREQ: 398 speed_mode = HISI_I2C_HIGH_SPEED_MODE; 399 hisi_i2c_set_scl(ctlr, 6, 22, HISI_I2C_HS_SCL_HCNT, HISI_I2C_HS_SCL_LCNT); 400 break; 401 case I2C_MAX_STANDARD_MODE_FREQ: 402 default: 403 speed_mode = HISI_I2C_STD_SPEED_MODE; 404 405 /* For default condition force the bus speed to standard mode. */ 406 ctlr->t.bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ; 407 hisi_i2c_set_scl(ctlr, 40, 87, HISI_I2C_SS_SCL_HCNT, HISI_I2C_SS_SCL_LCNT); 408 break; 409 } 410 411 reg = readl(ctlr->iobase + HISI_I2C_FRAME_CTRL); 412 reg &= ~HISI_I2C_FRAME_CTRL_SPEED_MODE; 413 reg |= FIELD_PREP(HISI_I2C_FRAME_CTRL_SPEED_MODE, speed_mode); 414 writel(reg, ctlr->iobase + HISI_I2C_FRAME_CTRL); 415 416 sda_hold_cnt = NSEC_TO_CYCLES(ctlr->t.sda_hold_ns, ctlr->clk_rate_khz); 417 418 reg = FIELD_PREP(HISI_I2C_SDA_HOLD_TX, sda_hold_cnt); 419 writel(reg, ctlr->iobase + HISI_I2C_SDA_HOLD); 420 421 writel(ctlr->spk_len, ctlr->iobase + HISI_I2C_FS_SPK_LEN); 422 423 reg = FIELD_PREP(HISI_I2C_FIFO_RX_AF_THRESH, HISI_I2C_RX_F_AF_THRESH); 424 reg |= FIELD_PREP(HISI_I2C_FIFO_TX_AE_THRESH, HISI_I2C_TX_F_AE_THRESH); 425 writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL); 426 } 427 428 static int hisi_i2c_probe(struct platform_device *pdev) 429 { 430 struct hisi_i2c_controller *ctlr; 431 struct device *dev = &pdev->dev; 432 struct i2c_adapter *adapter; 433 u64 clk_rate_hz; 434 u32 hw_version; 435 int ret; 436 437 ctlr = devm_kzalloc(dev, sizeof(*ctlr), GFP_KERNEL); 438 if (!ctlr) 439 return -ENOMEM; 440 441 ctlr->iobase = devm_platform_ioremap_resource(pdev, 0); 442 if (IS_ERR(ctlr->iobase)) 443 return PTR_ERR(ctlr->iobase); 444 445 ctlr->irq = platform_get_irq(pdev, 0); 446 if (ctlr->irq < 0) 447 return ctlr->irq; 448 449 ctlr->dev = dev; 450 451 hisi_i2c_disable_int(ctlr, HISI_I2C_INT_ALL); 452 453 ret = devm_request_irq(dev, ctlr->irq, hisi_i2c_irq, 0, "hisi-i2c", ctlr); 454 if (ret) { 455 dev_err(dev, "failed to request irq handler, ret = %d\n", ret); 456 return ret; 457 } 458 459 ctlr->clk = devm_clk_get_optional_enabled(&pdev->dev, NULL); 460 if (IS_ERR_OR_NULL(ctlr->clk)) { 461 ret = device_property_read_u64(dev, "clk_rate", &clk_rate_hz); 462 if (ret) { 463 dev_err(dev, "failed to get clock frequency, ret = %d\n", ret); 464 return ret; 465 } 466 } else { 467 clk_rate_hz = clk_get_rate(ctlr->clk); 468 } 469 470 ctlr->clk_rate_khz = DIV_ROUND_UP_ULL(clk_rate_hz, HZ_PER_KHZ); 471 472 hisi_i2c_configure_bus(ctlr); 473 474 adapter = &ctlr->adapter; 475 snprintf(adapter->name, sizeof(adapter->name), 476 "HiSilicon I2C Controller %s", dev_name(dev)); 477 adapter->owner = THIS_MODULE; 478 adapter->algo = &hisi_i2c_algo; 479 adapter->dev.parent = dev; 480 i2c_set_adapdata(adapter, ctlr); 481 482 ret = devm_i2c_add_adapter(dev, adapter); 483 if (ret) 484 return ret; 485 486 hw_version = readl(ctlr->iobase + HISI_I2C_VERSION); 487 dev_info(ctlr->dev, "speed mode is %s. hw version 0x%x\n", 488 i2c_freq_mode_string(ctlr->t.bus_freq_hz), hw_version); 489 490 return 0; 491 } 492 493 static const struct acpi_device_id hisi_i2c_acpi_ids[] = { 494 { "HISI03D1", 0 }, 495 { } 496 }; 497 MODULE_DEVICE_TABLE(acpi, hisi_i2c_acpi_ids); 498 499 static const struct of_device_id hisi_i2c_dts_ids[] = { 500 { .compatible = "hisilicon,ascend910-i2c", }, 501 { } 502 }; 503 MODULE_DEVICE_TABLE(of, hisi_i2c_dts_ids); 504 505 static struct platform_driver hisi_i2c_driver = { 506 .probe = hisi_i2c_probe, 507 .driver = { 508 .name = "hisi-i2c", 509 .acpi_match_table = hisi_i2c_acpi_ids, 510 .of_match_table = hisi_i2c_dts_ids, 511 }, 512 }; 513 module_platform_driver(hisi_i2c_driver); 514 515 MODULE_AUTHOR("Yicong Yang <yangyicong@hisilicon.com>"); 516 MODULE_DESCRIPTION("HiSilicon I2C Controller Driver"); 517 MODULE_LICENSE("GPL"); 518