1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * HiSilicon I2C Controller Driver for Kunpeng SoC 4 * 5 * Copyright (c) 2021 HiSilicon Technologies Co., Ltd. 6 */ 7 8 #include <linux/bits.h> 9 #include <linux/bitfield.h> 10 #include <linux/completion.h> 11 #include <linux/i2c.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/module.h> 15 #include <linux/mod_devicetable.h> 16 #include <linux/platform_device.h> 17 #include <linux/property.h> 18 #include <linux/units.h> 19 20 #define HISI_I2C_FRAME_CTRL 0x0000 21 #define HISI_I2C_FRAME_CTRL_SPEED_MODE GENMASK(1, 0) 22 #define HISI_I2C_FRAME_CTRL_ADDR_TEN BIT(2) 23 #define HISI_I2C_SLV_ADDR 0x0004 24 #define HISI_I2C_SLV_ADDR_VAL GENMASK(9, 0) 25 #define HISI_I2C_SLV_ADDR_GC_S_MODE BIT(10) 26 #define HISI_I2C_SLV_ADDR_GC_S_EN BIT(11) 27 #define HISI_I2C_CMD_TXDATA 0x0008 28 #define HISI_I2C_CMD_TXDATA_DATA GENMASK(7, 0) 29 #define HISI_I2C_CMD_TXDATA_RW BIT(8) 30 #define HISI_I2C_CMD_TXDATA_P_EN BIT(9) 31 #define HISI_I2C_CMD_TXDATA_SR_EN BIT(10) 32 #define HISI_I2C_RXDATA 0x000c 33 #define HISI_I2C_RXDATA_DATA GENMASK(7, 0) 34 #define HISI_I2C_SS_SCL_HCNT 0x0010 35 #define HISI_I2C_SS_SCL_LCNT 0x0014 36 #define HISI_I2C_FS_SCL_HCNT 0x0018 37 #define HISI_I2C_FS_SCL_LCNT 0x001c 38 #define HISI_I2C_HS_SCL_HCNT 0x0020 39 #define HISI_I2C_HS_SCL_LCNT 0x0024 40 #define HISI_I2C_FIFO_CTRL 0x0028 41 #define HISI_I2C_FIFO_RX_CLR BIT(0) 42 #define HISI_I2C_FIFO_TX_CLR BIT(1) 43 #define HISI_I2C_FIFO_RX_AF_THRESH GENMASK(7, 2) 44 #define HISI_I2C_FIFO_TX_AE_THRESH GENMASK(13, 8) 45 #define HISI_I2C_FIFO_STATE 0x002c 46 #define HISI_I2C_FIFO_STATE_RX_RERR BIT(0) 47 #define HISI_I2C_FIFO_STATE_RX_WERR BIT(1) 48 #define HISI_I2C_FIFO_STATE_RX_EMPTY BIT(3) 49 #define HISI_I2C_FIFO_STATE_TX_RERR BIT(6) 50 #define HISI_I2C_FIFO_STATE_TX_WERR BIT(7) 51 #define HISI_I2C_FIFO_STATE_TX_FULL BIT(11) 52 #define HISI_I2C_SDA_HOLD 0x0030 53 #define HISI_I2C_SDA_HOLD_TX GENMASK(15, 0) 54 #define HISI_I2C_SDA_HOLD_RX GENMASK(23, 16) 55 #define HISI_I2C_FS_SPK_LEN 0x0038 56 #define HISI_I2C_FS_SPK_LEN_CNT GENMASK(7, 0) 57 #define HISI_I2C_HS_SPK_LEN 0x003c 58 #define HISI_I2C_HS_SPK_LEN_CNT GENMASK(7, 0) 59 #define HISI_I2C_INT_MSTAT 0x0044 60 #define HISI_I2C_INT_CLR 0x0048 61 #define HISI_I2C_INT_MASK 0x004C 62 #define HISI_I2C_TRANS_STATE 0x0050 63 #define HISI_I2C_TRANS_ERR 0x0054 64 #define HISI_I2C_VERSION 0x0058 65 66 #define HISI_I2C_INT_ALL GENMASK(4, 0) 67 #define HISI_I2C_INT_TRANS_CPLT BIT(0) 68 #define HISI_I2C_INT_TRANS_ERR BIT(1) 69 #define HISI_I2C_INT_FIFO_ERR BIT(2) 70 #define HISI_I2C_INT_RX_FULL BIT(3) 71 #define HISI_I2C_INT_TX_EMPTY BIT(4) 72 #define HISI_I2C_INT_ERR \ 73 (HISI_I2C_INT_TRANS_ERR | HISI_I2C_INT_FIFO_ERR) 74 75 #define HISI_I2C_STD_SPEED_MODE 0 76 #define HISI_I2C_FAST_SPEED_MODE 1 77 #define HISI_I2C_HIGH_SPEED_MODE 2 78 79 #define HISI_I2C_TX_FIFO_DEPTH 64 80 #define HISI_I2C_RX_FIFO_DEPTH 64 81 #define HISI_I2C_TX_F_AE_THRESH 1 82 #define HISI_I2C_RX_F_AF_THRESH 60 83 84 #define NSEC_TO_CYCLES(ns, clk_rate_khz) \ 85 DIV_ROUND_UP_ULL((clk_rate_khz) * (ns), NSEC_PER_MSEC) 86 87 struct hisi_i2c_controller { 88 struct i2c_adapter adapter; 89 void __iomem *iobase; 90 struct device *dev; 91 int irq; 92 93 /* Intermediates for recording the transfer process */ 94 struct completion *completion; 95 struct i2c_msg *msgs; 96 int msg_num; 97 int msg_tx_idx; 98 int buf_tx_idx; 99 int msg_rx_idx; 100 int buf_rx_idx; 101 u16 tar_addr; 102 u32 xfer_err; 103 104 /* I2C bus configuration */ 105 struct i2c_timings t; 106 u32 clk_rate_khz; 107 u32 spk_len; 108 }; 109 110 static void hisi_i2c_enable_int(struct hisi_i2c_controller *ctlr, u32 mask) 111 { 112 writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_MASK); 113 } 114 115 static void hisi_i2c_disable_int(struct hisi_i2c_controller *ctlr, u32 mask) 116 { 117 writel_relaxed((~mask) & HISI_I2C_INT_ALL, ctlr->iobase + HISI_I2C_INT_MASK); 118 } 119 120 static void hisi_i2c_clear_int(struct hisi_i2c_controller *ctlr, u32 mask) 121 { 122 writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_CLR); 123 } 124 125 static void hisi_i2c_handle_errors(struct hisi_i2c_controller *ctlr) 126 { 127 u32 int_err = ctlr->xfer_err, reg; 128 129 if (int_err & HISI_I2C_INT_FIFO_ERR) { 130 reg = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); 131 132 if (reg & HISI_I2C_FIFO_STATE_RX_RERR) 133 dev_err(ctlr->dev, "rx fifo error read\n"); 134 135 if (reg & HISI_I2C_FIFO_STATE_RX_WERR) 136 dev_err(ctlr->dev, "rx fifo error write\n"); 137 138 if (reg & HISI_I2C_FIFO_STATE_TX_RERR) 139 dev_err(ctlr->dev, "tx fifo error read\n"); 140 141 if (reg & HISI_I2C_FIFO_STATE_TX_WERR) 142 dev_err(ctlr->dev, "tx fifo error write\n"); 143 } 144 } 145 146 static int hisi_i2c_start_xfer(struct hisi_i2c_controller *ctlr) 147 { 148 struct i2c_msg *msg = ctlr->msgs; 149 u32 reg; 150 151 reg = readl(ctlr->iobase + HISI_I2C_FRAME_CTRL); 152 reg &= ~HISI_I2C_FRAME_CTRL_ADDR_TEN; 153 if (msg->flags & I2C_M_TEN) 154 reg |= HISI_I2C_FRAME_CTRL_ADDR_TEN; 155 writel(reg, ctlr->iobase + HISI_I2C_FRAME_CTRL); 156 157 reg = readl(ctlr->iobase + HISI_I2C_SLV_ADDR); 158 reg &= ~HISI_I2C_SLV_ADDR_VAL; 159 reg |= FIELD_PREP(HISI_I2C_SLV_ADDR_VAL, msg->addr); 160 writel(reg, ctlr->iobase + HISI_I2C_SLV_ADDR); 161 162 reg = readl(ctlr->iobase + HISI_I2C_FIFO_CTRL); 163 reg |= HISI_I2C_FIFO_RX_CLR | HISI_I2C_FIFO_TX_CLR; 164 writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL); 165 reg &= ~(HISI_I2C_FIFO_RX_CLR | HISI_I2C_FIFO_TX_CLR); 166 writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL); 167 168 hisi_i2c_clear_int(ctlr, HISI_I2C_INT_ALL); 169 hisi_i2c_enable_int(ctlr, HISI_I2C_INT_ALL); 170 171 return 0; 172 } 173 174 static void hisi_i2c_reset_xfer(struct hisi_i2c_controller *ctlr) 175 { 176 ctlr->msg_num = 0; 177 ctlr->xfer_err = 0; 178 ctlr->msg_tx_idx = 0; 179 ctlr->msg_rx_idx = 0; 180 ctlr->buf_tx_idx = 0; 181 ctlr->buf_rx_idx = 0; 182 } 183 184 /* 185 * Initialize the transfer information and start the I2C bus transfer. 186 * We only configure the transfer and do some pre/post works here, and 187 * wait for the transfer done. The major transfer process is performed 188 * in the IRQ handler. 189 */ 190 static int hisi_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, 191 int num) 192 { 193 struct hisi_i2c_controller *ctlr = i2c_get_adapdata(adap); 194 DECLARE_COMPLETION_ONSTACK(done); 195 int ret = num; 196 197 hisi_i2c_reset_xfer(ctlr); 198 ctlr->completion = &done; 199 ctlr->msg_num = num; 200 ctlr->msgs = msgs; 201 202 hisi_i2c_start_xfer(ctlr); 203 204 if (!wait_for_completion_timeout(ctlr->completion, adap->timeout)) { 205 hisi_i2c_disable_int(ctlr, HISI_I2C_INT_ALL); 206 synchronize_irq(ctlr->irq); 207 i2c_recover_bus(&ctlr->adapter); 208 dev_err(ctlr->dev, "bus transfer timeout\n"); 209 ret = -EIO; 210 } 211 212 if (ctlr->xfer_err) { 213 hisi_i2c_handle_errors(ctlr); 214 ret = -EIO; 215 } 216 217 hisi_i2c_reset_xfer(ctlr); 218 ctlr->completion = NULL; 219 220 return ret; 221 } 222 223 static u32 hisi_i2c_functionality(struct i2c_adapter *adap) 224 { 225 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL; 226 } 227 228 static const struct i2c_algorithm hisi_i2c_algo = { 229 .master_xfer = hisi_i2c_master_xfer, 230 .functionality = hisi_i2c_functionality, 231 }; 232 233 static int hisi_i2c_read_rx_fifo(struct hisi_i2c_controller *ctlr) 234 { 235 struct i2c_msg *cur_msg; 236 u32 fifo_state; 237 238 while (ctlr->msg_rx_idx < ctlr->msg_num) { 239 cur_msg = ctlr->msgs + ctlr->msg_rx_idx; 240 241 if (!(cur_msg->flags & I2C_M_RD)) { 242 ctlr->msg_rx_idx++; 243 continue; 244 } 245 246 fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); 247 while (!(fifo_state & HISI_I2C_FIFO_STATE_RX_EMPTY) && 248 ctlr->buf_rx_idx < cur_msg->len) { 249 cur_msg->buf[ctlr->buf_rx_idx++] = readl(ctlr->iobase + HISI_I2C_RXDATA); 250 fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); 251 } 252 253 if (ctlr->buf_rx_idx == cur_msg->len) { 254 ctlr->buf_rx_idx = 0; 255 ctlr->msg_rx_idx++; 256 } 257 258 if (fifo_state & HISI_I2C_FIFO_STATE_RX_EMPTY) 259 break; 260 } 261 262 return 0; 263 } 264 265 static void hisi_i2c_xfer_msg(struct hisi_i2c_controller *ctlr) 266 { 267 int max_write = HISI_I2C_TX_FIFO_DEPTH; 268 bool need_restart = false, last_msg; 269 struct i2c_msg *cur_msg; 270 u32 cmd, fifo_state; 271 272 while (ctlr->msg_tx_idx < ctlr->msg_num) { 273 cur_msg = ctlr->msgs + ctlr->msg_tx_idx; 274 last_msg = (ctlr->msg_tx_idx == ctlr->msg_num - 1); 275 276 /* Signal the SR bit when we start transferring a new message */ 277 if (ctlr->msg_tx_idx && !ctlr->buf_tx_idx) 278 need_restart = true; 279 280 fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); 281 while (!(fifo_state & HISI_I2C_FIFO_STATE_TX_FULL) && 282 ctlr->buf_tx_idx < cur_msg->len && max_write) { 283 cmd = 0; 284 285 if (need_restart) { 286 cmd |= HISI_I2C_CMD_TXDATA_SR_EN; 287 need_restart = false; 288 } 289 290 /* Signal the STOP bit at the last frame of the last message */ 291 if (ctlr->buf_tx_idx == cur_msg->len - 1 && last_msg) 292 cmd |= HISI_I2C_CMD_TXDATA_P_EN; 293 294 if (cur_msg->flags & I2C_M_RD) 295 cmd |= HISI_I2C_CMD_TXDATA_RW; 296 else 297 cmd |= FIELD_PREP(HISI_I2C_CMD_TXDATA_DATA, 298 cur_msg->buf[ctlr->buf_tx_idx]); 299 300 writel(cmd, ctlr->iobase + HISI_I2C_CMD_TXDATA); 301 ctlr->buf_tx_idx++; 302 max_write--; 303 304 fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); 305 } 306 307 /* Update the transfer index after per message transfer is done. */ 308 if (ctlr->buf_tx_idx == cur_msg->len) { 309 ctlr->buf_tx_idx = 0; 310 ctlr->msg_tx_idx++; 311 } 312 313 if ((fifo_state & HISI_I2C_FIFO_STATE_TX_FULL) || 314 max_write == 0) 315 break; 316 } 317 } 318 319 static irqreturn_t hisi_i2c_irq(int irq, void *context) 320 { 321 struct hisi_i2c_controller *ctlr = context; 322 u32 int_stat; 323 324 int_stat = readl(ctlr->iobase + HISI_I2C_INT_MSTAT); 325 hisi_i2c_clear_int(ctlr, int_stat); 326 if (!(int_stat & HISI_I2C_INT_ALL)) 327 return IRQ_NONE; 328 329 if (int_stat & HISI_I2C_INT_TX_EMPTY) 330 hisi_i2c_xfer_msg(ctlr); 331 332 if (int_stat & HISI_I2C_INT_ERR) { 333 ctlr->xfer_err = int_stat; 334 goto out; 335 } 336 337 /* Drain the rx fifo before finish the transfer */ 338 if (int_stat & (HISI_I2C_INT_TRANS_CPLT | HISI_I2C_INT_RX_FULL)) 339 hisi_i2c_read_rx_fifo(ctlr); 340 341 out: 342 if (int_stat & HISI_I2C_INT_TRANS_CPLT || ctlr->xfer_err) { 343 hisi_i2c_disable_int(ctlr, HISI_I2C_INT_ALL); 344 hisi_i2c_clear_int(ctlr, HISI_I2C_INT_ALL); 345 complete(ctlr->completion); 346 } 347 348 return IRQ_HANDLED; 349 } 350 351 /* 352 * Helper function for calculating and configuring the HIGH and LOW 353 * periods of SCL clock. The caller will pass the ratio of the 354 * counts (divide / divisor) according to the target speed mode, 355 * and the target registers. 356 */ 357 static void hisi_i2c_set_scl(struct hisi_i2c_controller *ctlr, 358 u32 divide, u32 divisor, 359 u32 reg_hcnt, u32 reg_lcnt) 360 { 361 u32 total_cnt, t_scl_hcnt, t_scl_lcnt, scl_fall_cnt, scl_rise_cnt; 362 u32 scl_hcnt, scl_lcnt; 363 364 /* Total SCL clock cycles per speed period */ 365 total_cnt = DIV_ROUND_UP_ULL(ctlr->clk_rate_khz * HZ_PER_KHZ, ctlr->t.bus_freq_hz); 366 /* Total HIGH level SCL clock cycles including edges */ 367 t_scl_hcnt = DIV_ROUND_UP_ULL(total_cnt * divide, divisor); 368 /* Total LOW level SCL clock cycles including edges */ 369 t_scl_lcnt = total_cnt - t_scl_hcnt; 370 /* Fall edge SCL clock cycles */ 371 scl_fall_cnt = NSEC_TO_CYCLES(ctlr->t.scl_fall_ns, ctlr->clk_rate_khz); 372 /* Rise edge SCL clock cycles */ 373 scl_rise_cnt = NSEC_TO_CYCLES(ctlr->t.scl_rise_ns, ctlr->clk_rate_khz); 374 375 /* Calculated HIGH and LOW periods of SCL clock */ 376 scl_hcnt = t_scl_hcnt - ctlr->spk_len - 7 - scl_fall_cnt; 377 scl_lcnt = t_scl_lcnt - 1 - scl_rise_cnt; 378 379 writel(scl_hcnt, ctlr->iobase + reg_hcnt); 380 writel(scl_lcnt, ctlr->iobase + reg_lcnt); 381 } 382 383 static void hisi_i2c_configure_bus(struct hisi_i2c_controller *ctlr) 384 { 385 u32 reg, sda_hold_cnt, speed_mode; 386 387 i2c_parse_fw_timings(ctlr->dev, &ctlr->t, true); 388 ctlr->spk_len = NSEC_TO_CYCLES(ctlr->t.digital_filter_width_ns, ctlr->clk_rate_khz); 389 390 switch (ctlr->t.bus_freq_hz) { 391 case I2C_MAX_FAST_MODE_FREQ: 392 speed_mode = HISI_I2C_FAST_SPEED_MODE; 393 hisi_i2c_set_scl(ctlr, 26, 76, HISI_I2C_FS_SCL_HCNT, HISI_I2C_FS_SCL_LCNT); 394 break; 395 case I2C_MAX_HIGH_SPEED_MODE_FREQ: 396 speed_mode = HISI_I2C_HIGH_SPEED_MODE; 397 hisi_i2c_set_scl(ctlr, 6, 22, HISI_I2C_HS_SCL_HCNT, HISI_I2C_HS_SCL_LCNT); 398 break; 399 case I2C_MAX_STANDARD_MODE_FREQ: 400 default: 401 speed_mode = HISI_I2C_STD_SPEED_MODE; 402 403 /* For default condition force the bus speed to standard mode. */ 404 ctlr->t.bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ; 405 hisi_i2c_set_scl(ctlr, 40, 87, HISI_I2C_SS_SCL_HCNT, HISI_I2C_SS_SCL_LCNT); 406 break; 407 } 408 409 reg = readl(ctlr->iobase + HISI_I2C_FRAME_CTRL); 410 reg &= ~HISI_I2C_FRAME_CTRL_SPEED_MODE; 411 reg |= FIELD_PREP(HISI_I2C_FRAME_CTRL_SPEED_MODE, speed_mode); 412 writel(reg, ctlr->iobase + HISI_I2C_FRAME_CTRL); 413 414 sda_hold_cnt = NSEC_TO_CYCLES(ctlr->t.sda_hold_ns, ctlr->clk_rate_khz); 415 416 reg = FIELD_PREP(HISI_I2C_SDA_HOLD_TX, sda_hold_cnt); 417 writel(reg, ctlr->iobase + HISI_I2C_SDA_HOLD); 418 419 writel(ctlr->spk_len, ctlr->iobase + HISI_I2C_FS_SPK_LEN); 420 421 reg = FIELD_PREP(HISI_I2C_FIFO_RX_AF_THRESH, HISI_I2C_RX_F_AF_THRESH); 422 reg |= FIELD_PREP(HISI_I2C_FIFO_TX_AE_THRESH, HISI_I2C_TX_F_AE_THRESH); 423 writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL); 424 } 425 426 static int hisi_i2c_probe(struct platform_device *pdev) 427 { 428 struct hisi_i2c_controller *ctlr; 429 struct device *dev = &pdev->dev; 430 struct i2c_adapter *adapter; 431 u64 clk_rate_hz; 432 u32 hw_version; 433 int ret; 434 435 ctlr = devm_kzalloc(dev, sizeof(*ctlr), GFP_KERNEL); 436 if (!ctlr) 437 return -ENOMEM; 438 439 ctlr->iobase = devm_platform_ioremap_resource(pdev, 0); 440 if (IS_ERR(ctlr->iobase)) 441 return PTR_ERR(ctlr->iobase); 442 443 ctlr->irq = platform_get_irq(pdev, 0); 444 if (ctlr->irq < 0) 445 return ctlr->irq; 446 447 ctlr->dev = dev; 448 449 hisi_i2c_disable_int(ctlr, HISI_I2C_INT_ALL); 450 451 ret = devm_request_irq(dev, ctlr->irq, hisi_i2c_irq, 0, "hisi-i2c", ctlr); 452 if (ret) { 453 dev_err(dev, "failed to request irq handler, ret = %d\n", ret); 454 return ret; 455 } 456 457 ret = device_property_read_u64(dev, "clk_rate", &clk_rate_hz); 458 if (ret) { 459 dev_err(dev, "failed to get clock frequency, ret = %d\n", ret); 460 return ret; 461 } 462 463 ctlr->clk_rate_khz = DIV_ROUND_UP_ULL(clk_rate_hz, HZ_PER_KHZ); 464 465 hisi_i2c_configure_bus(ctlr); 466 467 adapter = &ctlr->adapter; 468 snprintf(adapter->name, sizeof(adapter->name), 469 "HiSilicon I2C Controller %s", dev_name(dev)); 470 adapter->owner = THIS_MODULE; 471 adapter->algo = &hisi_i2c_algo; 472 adapter->dev.parent = dev; 473 i2c_set_adapdata(adapter, ctlr); 474 475 ret = devm_i2c_add_adapter(dev, adapter); 476 if (ret) 477 return ret; 478 479 hw_version = readl(ctlr->iobase + HISI_I2C_VERSION); 480 dev_info(ctlr->dev, "speed mode is %s. hw version 0x%x\n", 481 i2c_freq_mode_string(ctlr->t.bus_freq_hz), hw_version); 482 483 return 0; 484 } 485 486 static const struct acpi_device_id hisi_i2c_acpi_ids[] = { 487 { "HISI03D1", 0 }, 488 { } 489 }; 490 MODULE_DEVICE_TABLE(acpi, hisi_i2c_acpi_ids); 491 492 static struct platform_driver hisi_i2c_driver = { 493 .probe = hisi_i2c_probe, 494 .driver = { 495 .name = "hisi-i2c", 496 .acpi_match_table = hisi_i2c_acpi_ids, 497 }, 498 }; 499 module_platform_driver(hisi_i2c_driver); 500 501 MODULE_AUTHOR("Yicong Yang <yangyicong@hisilicon.com>"); 502 MODULE_DESCRIPTION("HiSilicon I2C Controller Driver"); 503 MODULE_LICENSE("GPL"); 504