1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (C) 2022 Hewlett-Packard Enterprise Development Company, L.P. */ 3 4 #include <linux/err.h> 5 #include <linux/io.h> 6 #include <linux/i2c.h> 7 #include <linux/module.h> 8 #include <linux/of_device.h> 9 #include <linux/regmap.h> 10 #include <linux/mfd/syscon.h> 11 12 #define GXP_MAX_I2C_ENGINE 10 13 static const char * const gxp_i2c_name[] = { 14 "gxp-i2c0", "gxp-i2c1", "gxp-i2c2", "gxp-i2c3", 15 "gxp-i2c4", "gxp-i2c5", "gxp-i2c6", "gxp-i2c7", 16 "gxp-i2c8", "gxp-i2c9" }; 17 18 /* GXP I2C Global interrupt status/enable register*/ 19 #define GXP_I2CINTSTAT 0x00 20 #define GXP_I2CINTEN 0x04 21 22 /* GXP I2C registers */ 23 #define GXP_I2CSTAT 0x00 24 #define MASK_STOP_EVENT 0x20 25 #define MASK_ACK 0x08 26 #define MASK_RW 0x04 27 #define GXP_I2CEVTERR 0x01 28 #define MASK_SLAVE_CMD_EVENT 0x01 29 #define MASK_SLAVE_DATA_EVENT 0x02 30 #define MASK_MASTER_EVENT 0x10 31 #define GXP_I2CSNPDAT 0x02 32 #define GXP_I2CMCMD 0x04 33 #define GXP_I2CSCMD 0x06 34 #define GXP_I2CSNPAA 0x09 35 #define GXP_I2CADVFEAT 0x0A 36 #define GXP_I2COWNADR 0x0B 37 #define GXP_I2CFREQDIV 0x0C 38 #define GXP_I2CFLTFAIR 0x0D 39 #define GXP_I2CTMOEDG 0x0E 40 #define GXP_I2CCYCTIM 0x0F 41 42 /* I2CSCMD Bits */ 43 #define SNOOP_EVT_CLR 0x80 44 #define SLAVE_EVT_CLR 0x40 45 #define SNOOP_EVT_MASK 0x20 46 #define SLAVE_EVT_MASK 0x10 47 #define SLAVE_ACK_ENAB 0x08 48 #define SLAVE_EVT_STALL 0x01 49 50 /* I2CMCMD Bits */ 51 #define MASTER_EVT_CLR 0x80 52 #define MASTER_ACK_ENAB 0x08 53 #define RW_CMD 0x04 54 #define STOP_CMD 0x02 55 #define START_CMD 0x01 56 57 /* I2CTMOEDG value */ 58 #define GXP_DATA_EDGE_RST_CTRL 0x0a /* 30ns */ 59 60 /* I2CFLTFAIR Bits */ 61 #define FILTER_CNT 0x30 62 #define FAIRNESS_CNT 0x02 63 64 enum { 65 GXP_I2C_IDLE = 0, 66 GXP_I2C_ADDR_PHASE, 67 GXP_I2C_RDATA_PHASE, 68 GXP_I2C_WDATA_PHASE, 69 GXP_I2C_ADDR_NACK, 70 GXP_I2C_DATA_NACK, 71 GXP_I2C_ERROR, 72 GXP_I2C_COMP 73 }; 74 75 struct gxp_i2c_drvdata { 76 struct device *dev; 77 void __iomem *base; 78 struct i2c_timings t; 79 u32 engine; 80 int irq; 81 struct completion completion; 82 struct i2c_adapter adapter; 83 struct i2c_msg *curr_msg; 84 int msgs_remaining; 85 int msgs_num; 86 u8 *buf; 87 size_t buf_remaining; 88 unsigned char state; 89 struct i2c_client *slave; 90 unsigned char stopped; 91 }; 92 93 static struct regmap *i2cg_map; 94 95 static void gxp_i2c_start(struct gxp_i2c_drvdata *drvdata) 96 { 97 u16 value; 98 99 drvdata->buf = drvdata->curr_msg->buf; 100 drvdata->buf_remaining = drvdata->curr_msg->len; 101 102 /* Note: Address in struct i2c_msg is 7 bits */ 103 value = drvdata->curr_msg->addr << 9; 104 105 /* Read or Write */ 106 value |= drvdata->curr_msg->flags & I2C_M_RD ? RW_CMD | START_CMD : START_CMD; 107 108 drvdata->state = GXP_I2C_ADDR_PHASE; 109 writew(value, drvdata->base + GXP_I2CMCMD); 110 } 111 112 static int gxp_i2c_master_xfer(struct i2c_adapter *adapter, 113 struct i2c_msg *msgs, int num) 114 { 115 int ret; 116 struct gxp_i2c_drvdata *drvdata = i2c_get_adapdata(adapter); 117 unsigned long time_left; 118 119 drvdata->msgs_remaining = num; 120 drvdata->curr_msg = msgs; 121 drvdata->msgs_num = num; 122 reinit_completion(&drvdata->completion); 123 124 gxp_i2c_start(drvdata); 125 126 time_left = wait_for_completion_timeout(&drvdata->completion, 127 adapter->timeout); 128 ret = num - drvdata->msgs_remaining; 129 if (time_left == 0) 130 return -ETIMEDOUT; 131 132 if (drvdata->state == GXP_I2C_ADDR_NACK) 133 return -ENXIO; 134 135 if (drvdata->state == GXP_I2C_DATA_NACK) 136 return -EIO; 137 138 return ret; 139 } 140 141 static u32 gxp_i2c_func(struct i2c_adapter *adap) 142 { 143 if (IS_ENABLED(CONFIG_I2C_SLAVE)) 144 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SLAVE; 145 146 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 147 } 148 149 #if IS_ENABLED(CONFIG_I2C_SLAVE) 150 static int gxp_i2c_reg_slave(struct i2c_client *slave) 151 { 152 struct gxp_i2c_drvdata *drvdata = i2c_get_adapdata(slave->adapter); 153 154 if (drvdata->slave) 155 return -EBUSY; 156 157 if (slave->flags & I2C_CLIENT_TEN) 158 return -EAFNOSUPPORT; 159 160 drvdata->slave = slave; 161 162 writeb(slave->addr << 1, drvdata->base + GXP_I2COWNADR); 163 writeb(SLAVE_EVT_CLR | SNOOP_EVT_MASK | SLAVE_ACK_ENAB | 164 SLAVE_EVT_STALL, drvdata->base + GXP_I2CSCMD); 165 166 return 0; 167 } 168 169 static int gxp_i2c_unreg_slave(struct i2c_client *slave) 170 { 171 struct gxp_i2c_drvdata *drvdata = i2c_get_adapdata(slave->adapter); 172 173 WARN_ON(!drvdata->slave); 174 175 writeb(0x00, drvdata->base + GXP_I2COWNADR); 176 writeb(SNOOP_EVT_CLR | SLAVE_EVT_CLR | SNOOP_EVT_MASK | 177 SLAVE_EVT_MASK, drvdata->base + GXP_I2CSCMD); 178 179 drvdata->slave = NULL; 180 181 return 0; 182 } 183 #endif 184 185 static const struct i2c_algorithm gxp_i2c_algo = { 186 .master_xfer = gxp_i2c_master_xfer, 187 .functionality = gxp_i2c_func, 188 #if IS_ENABLED(CONFIG_I2C_SLAVE) 189 .reg_slave = gxp_i2c_reg_slave, 190 .unreg_slave = gxp_i2c_unreg_slave, 191 #endif 192 }; 193 194 static void gxp_i2c_stop(struct gxp_i2c_drvdata *drvdata) 195 { 196 /* Clear event and send stop */ 197 writeb(MASTER_EVT_CLR | STOP_CMD, drvdata->base + GXP_I2CMCMD); 198 199 complete(&drvdata->completion); 200 } 201 202 static void gxp_i2c_restart(struct gxp_i2c_drvdata *drvdata) 203 { 204 u16 value; 205 206 drvdata->buf = drvdata->curr_msg->buf; 207 drvdata->buf_remaining = drvdata->curr_msg->len; 208 209 value = drvdata->curr_msg->addr << 9; 210 211 if (drvdata->curr_msg->flags & I2C_M_RD) { 212 /* Read and clear master event */ 213 value |= MASTER_EVT_CLR | RW_CMD | START_CMD; 214 } else { 215 /* Write and clear master event */ 216 value |= MASTER_EVT_CLR | START_CMD; 217 } 218 219 drvdata->state = GXP_I2C_ADDR_PHASE; 220 221 writew(value, drvdata->base + GXP_I2CMCMD); 222 } 223 224 static void gxp_i2c_chk_addr_ack(struct gxp_i2c_drvdata *drvdata) 225 { 226 u16 value; 227 228 value = readb(drvdata->base + GXP_I2CSTAT); 229 if (!(value & MASK_ACK)) { 230 /* Got no ack, stop */ 231 drvdata->state = GXP_I2C_ADDR_NACK; 232 gxp_i2c_stop(drvdata); 233 return; 234 } 235 236 if (drvdata->curr_msg->flags & I2C_M_RD) { 237 /* Start to read data from slave */ 238 if (drvdata->buf_remaining == 0) { 239 /* No more data to read, stop */ 240 drvdata->msgs_remaining--; 241 drvdata->state = GXP_I2C_COMP; 242 gxp_i2c_stop(drvdata); 243 return; 244 } 245 drvdata->state = GXP_I2C_RDATA_PHASE; 246 247 if (drvdata->buf_remaining == 1) { 248 /* The last data, do not ack */ 249 writeb(MASTER_EVT_CLR | RW_CMD, 250 drvdata->base + GXP_I2CMCMD); 251 } else { 252 /* Read data and ack it */ 253 writeb(MASTER_EVT_CLR | MASTER_ACK_ENAB | 254 RW_CMD, drvdata->base + GXP_I2CMCMD); 255 } 256 } else { 257 /* Start to write first data to slave */ 258 if (drvdata->buf_remaining == 0) { 259 /* No more data to write, stop */ 260 drvdata->msgs_remaining--; 261 drvdata->state = GXP_I2C_COMP; 262 gxp_i2c_stop(drvdata); 263 return; 264 } 265 value = *drvdata->buf; 266 value = value << 8; 267 /* Clear master event */ 268 value |= MASTER_EVT_CLR; 269 drvdata->buf++; 270 drvdata->buf_remaining--; 271 drvdata->state = GXP_I2C_WDATA_PHASE; 272 writew(value, drvdata->base + GXP_I2CMCMD); 273 } 274 } 275 276 static void gxp_i2c_ack_data(struct gxp_i2c_drvdata *drvdata) 277 { 278 u8 value; 279 280 /* Store the data returned */ 281 value = readb(drvdata->base + GXP_I2CSNPDAT); 282 *drvdata->buf = value; 283 drvdata->buf++; 284 drvdata->buf_remaining--; 285 286 if (drvdata->buf_remaining == 0) { 287 /* No more data, this message is completed. */ 288 drvdata->msgs_remaining--; 289 290 if (drvdata->msgs_remaining == 0) { 291 /* No more messages, stop */ 292 drvdata->state = GXP_I2C_COMP; 293 gxp_i2c_stop(drvdata); 294 return; 295 } 296 /* Move to next message and start transfer */ 297 drvdata->curr_msg++; 298 gxp_i2c_restart(drvdata); 299 return; 300 } 301 302 /* Ack the slave to make it send next byte */ 303 drvdata->state = GXP_I2C_RDATA_PHASE; 304 if (drvdata->buf_remaining == 1) { 305 /* The last data, do not ack */ 306 writeb(MASTER_EVT_CLR | RW_CMD, 307 drvdata->base + GXP_I2CMCMD); 308 } else { 309 /* Read data and ack it */ 310 writeb(MASTER_EVT_CLR | MASTER_ACK_ENAB | 311 RW_CMD, drvdata->base + GXP_I2CMCMD); 312 } 313 } 314 315 static void gxp_i2c_chk_data_ack(struct gxp_i2c_drvdata *drvdata) 316 { 317 u16 value; 318 319 value = readb(drvdata->base + GXP_I2CSTAT); 320 if (!(value & MASK_ACK)) { 321 /* Received No ack, stop */ 322 drvdata->state = GXP_I2C_DATA_NACK; 323 gxp_i2c_stop(drvdata); 324 return; 325 } 326 327 /* Got ack, check if there is more data to write */ 328 if (drvdata->buf_remaining == 0) { 329 /* No more data, this message is completed */ 330 drvdata->msgs_remaining--; 331 332 if (drvdata->msgs_remaining == 0) { 333 /* No more messages, stop */ 334 drvdata->state = GXP_I2C_COMP; 335 gxp_i2c_stop(drvdata); 336 return; 337 } 338 /* Move to next message and start transfer */ 339 drvdata->curr_msg++; 340 gxp_i2c_restart(drvdata); 341 return; 342 } 343 344 /* Write data to slave */ 345 value = *drvdata->buf; 346 value = value << 8; 347 348 /* Clear master event */ 349 value |= MASTER_EVT_CLR; 350 drvdata->buf++; 351 drvdata->buf_remaining--; 352 drvdata->state = GXP_I2C_WDATA_PHASE; 353 writew(value, drvdata->base + GXP_I2CMCMD); 354 } 355 356 static bool gxp_i2c_slave_irq_handler(struct gxp_i2c_drvdata *drvdata) 357 { 358 u8 value; 359 u8 buf; 360 int ret; 361 362 value = readb(drvdata->base + GXP_I2CEVTERR); 363 364 /* Received start or stop event */ 365 if (value & MASK_SLAVE_CMD_EVENT) { 366 value = readb(drvdata->base + GXP_I2CSTAT); 367 /* Master sent stop */ 368 if (value & MASK_STOP_EVENT) { 369 if (drvdata->stopped == 0) 370 i2c_slave_event(drvdata->slave, I2C_SLAVE_STOP, &buf); 371 writeb(SLAVE_EVT_CLR | SNOOP_EVT_MASK | 372 SLAVE_ACK_ENAB | SLAVE_EVT_STALL, drvdata->base + GXP_I2CSCMD); 373 drvdata->stopped = 1; 374 } else { 375 /* Master sent start and wants to read */ 376 drvdata->stopped = 0; 377 if (value & MASK_RW) { 378 i2c_slave_event(drvdata->slave, 379 I2C_SLAVE_READ_REQUESTED, &buf); 380 value = buf << 8 | (SLAVE_EVT_CLR | SNOOP_EVT_MASK | 381 SLAVE_EVT_STALL); 382 writew(value, drvdata->base + GXP_I2CSCMD); 383 } else { 384 /* Master wants to write to us */ 385 ret = i2c_slave_event(drvdata->slave, 386 I2C_SLAVE_WRITE_REQUESTED, &buf); 387 if (!ret) { 388 /* Ack next byte from master */ 389 writeb(SLAVE_EVT_CLR | SNOOP_EVT_MASK | 390 SLAVE_ACK_ENAB | SLAVE_EVT_STALL, 391 drvdata->base + GXP_I2CSCMD); 392 } else { 393 /* Nack next byte from master */ 394 writeb(SLAVE_EVT_CLR | SNOOP_EVT_MASK | 395 SLAVE_EVT_STALL, drvdata->base + GXP_I2CSCMD); 396 } 397 } 398 } 399 } else if (value & MASK_SLAVE_DATA_EVENT) { 400 value = readb(drvdata->base + GXP_I2CSTAT); 401 /* Master wants to read */ 402 if (value & MASK_RW) { 403 /* Master wants another byte */ 404 if (value & MASK_ACK) { 405 i2c_slave_event(drvdata->slave, 406 I2C_SLAVE_READ_PROCESSED, &buf); 407 value = buf << 8 | (SLAVE_EVT_CLR | SNOOP_EVT_MASK | 408 SLAVE_EVT_STALL); 409 writew(value, drvdata->base + GXP_I2CSCMD); 410 } else { 411 /* No more bytes needed */ 412 writew(SLAVE_EVT_CLR | SNOOP_EVT_MASK | 413 SLAVE_ACK_ENAB | SLAVE_EVT_STALL, 414 drvdata->base + GXP_I2CSCMD); 415 } 416 } else { 417 /* Master wants to write to us */ 418 value = readb(drvdata->base + GXP_I2CSNPDAT); 419 buf = (uint8_t)value; 420 ret = i2c_slave_event(drvdata->slave, 421 I2C_SLAVE_WRITE_RECEIVED, &buf); 422 if (!ret) { 423 /* Ack next byte from master */ 424 writeb(SLAVE_EVT_CLR | SNOOP_EVT_MASK | 425 SLAVE_ACK_ENAB | SLAVE_EVT_STALL, 426 drvdata->base + GXP_I2CSCMD); 427 } else { 428 /* Nack next byte from master */ 429 writeb(SLAVE_EVT_CLR | SNOOP_EVT_MASK | 430 SLAVE_EVT_STALL, drvdata->base + GXP_I2CSCMD); 431 } 432 } 433 } else { 434 return false; 435 } 436 437 return true; 438 } 439 440 static irqreturn_t gxp_i2c_irq_handler(int irq, void *_drvdata) 441 { 442 struct gxp_i2c_drvdata *drvdata = (struct gxp_i2c_drvdata *)_drvdata; 443 u32 value; 444 445 /* Check if the interrupt is for the current engine */ 446 regmap_read(i2cg_map, GXP_I2CINTSTAT, &value); 447 if (!(value & BIT(drvdata->engine))) 448 return IRQ_NONE; 449 450 value = readb(drvdata->base + GXP_I2CEVTERR); 451 452 /* Error */ 453 if (value & ~(MASK_MASTER_EVENT | MASK_SLAVE_CMD_EVENT | 454 MASK_SLAVE_DATA_EVENT)) { 455 /* Clear all events */ 456 writeb(0x00, drvdata->base + GXP_I2CEVTERR); 457 drvdata->state = GXP_I2C_ERROR; 458 gxp_i2c_stop(drvdata); 459 return IRQ_HANDLED; 460 } 461 462 if (IS_ENABLED(CONFIG_I2C_SLAVE)) { 463 /* Slave mode */ 464 if (value & (MASK_SLAVE_CMD_EVENT | MASK_SLAVE_DATA_EVENT)) { 465 if (gxp_i2c_slave_irq_handler(drvdata)) 466 return IRQ_HANDLED; 467 return IRQ_NONE; 468 } 469 } 470 471 /* Master mode */ 472 switch (drvdata->state) { 473 case GXP_I2C_ADDR_PHASE: 474 gxp_i2c_chk_addr_ack(drvdata); 475 break; 476 477 case GXP_I2C_RDATA_PHASE: 478 gxp_i2c_ack_data(drvdata); 479 break; 480 481 case GXP_I2C_WDATA_PHASE: 482 gxp_i2c_chk_data_ack(drvdata); 483 break; 484 } 485 486 return IRQ_HANDLED; 487 } 488 489 static void gxp_i2c_init(struct gxp_i2c_drvdata *drvdata) 490 { 491 drvdata->state = GXP_I2C_IDLE; 492 writeb(2000000 / drvdata->t.bus_freq_hz, 493 drvdata->base + GXP_I2CFREQDIV); 494 writeb(FILTER_CNT | FAIRNESS_CNT, 495 drvdata->base + GXP_I2CFLTFAIR); 496 writeb(GXP_DATA_EDGE_RST_CTRL, drvdata->base + GXP_I2CTMOEDG); 497 writeb(0x00, drvdata->base + GXP_I2CCYCTIM); 498 writeb(0x00, drvdata->base + GXP_I2CSNPAA); 499 writeb(0x00, drvdata->base + GXP_I2CADVFEAT); 500 writeb(SNOOP_EVT_CLR | SLAVE_EVT_CLR | SNOOP_EVT_MASK | 501 SLAVE_EVT_MASK, drvdata->base + GXP_I2CSCMD); 502 writeb(MASTER_EVT_CLR, drvdata->base + GXP_I2CMCMD); 503 writeb(0x00, drvdata->base + GXP_I2CEVTERR); 504 writeb(0x00, drvdata->base + GXP_I2COWNADR); 505 } 506 507 static int gxp_i2c_probe(struct platform_device *pdev) 508 { 509 struct gxp_i2c_drvdata *drvdata; 510 int rc; 511 struct i2c_adapter *adapter; 512 513 if (!i2cg_map) { 514 i2cg_map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 515 "hpe,sysreg"); 516 if (IS_ERR(i2cg_map)) { 517 return dev_err_probe(&pdev->dev, PTR_ERR(i2cg_map), 518 "failed to map i2cg_handle\n"); 519 } 520 521 /* Disable interrupt */ 522 regmap_update_bits(i2cg_map, GXP_I2CINTEN, 0x00000FFF, 0); 523 } 524 525 drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), 526 GFP_KERNEL); 527 if (!drvdata) 528 return -ENOMEM; 529 530 platform_set_drvdata(pdev, drvdata); 531 drvdata->dev = &pdev->dev; 532 init_completion(&drvdata->completion); 533 534 drvdata->base = devm_platform_ioremap_resource(pdev, 0); 535 if (IS_ERR(drvdata->base)) 536 return PTR_ERR(drvdata->base); 537 538 /* Use physical memory address to determine which I2C engine this is. */ 539 drvdata->engine = ((size_t)drvdata->base & 0xf00) >> 8; 540 541 if (drvdata->engine >= GXP_MAX_I2C_ENGINE) { 542 return dev_err_probe(&pdev->dev, -EINVAL, "i2c engine% is unsupported\n", 543 drvdata->engine); 544 } 545 546 rc = platform_get_irq(pdev, 0); 547 if (rc < 0) 548 return rc; 549 550 drvdata->irq = rc; 551 rc = devm_request_irq(&pdev->dev, drvdata->irq, gxp_i2c_irq_handler, 552 IRQF_SHARED, gxp_i2c_name[drvdata->engine], drvdata); 553 if (rc < 0) 554 return dev_err_probe(&pdev->dev, rc, "irq request failed\n"); 555 556 i2c_parse_fw_timings(&pdev->dev, &drvdata->t, true); 557 558 gxp_i2c_init(drvdata); 559 560 /* Enable interrupt */ 561 regmap_update_bits(i2cg_map, GXP_I2CINTEN, BIT(drvdata->engine), 562 BIT(drvdata->engine)); 563 564 adapter = &drvdata->adapter; 565 i2c_set_adapdata(adapter, drvdata); 566 567 adapter->owner = THIS_MODULE; 568 strscpy(adapter->name, "HPE GXP I2C adapter", sizeof(adapter->name)); 569 adapter->algo = &gxp_i2c_algo; 570 adapter->dev.parent = &pdev->dev; 571 adapter->dev.of_node = pdev->dev.of_node; 572 573 rc = i2c_add_adapter(adapter); 574 if (rc) 575 return dev_err_probe(&pdev->dev, rc, "i2c add adapter failed\n"); 576 577 return 0; 578 } 579 580 static void gxp_i2c_remove(struct platform_device *pdev) 581 { 582 struct gxp_i2c_drvdata *drvdata = platform_get_drvdata(pdev); 583 584 /* Disable interrupt */ 585 regmap_update_bits(i2cg_map, GXP_I2CINTEN, BIT(drvdata->engine), 0); 586 i2c_del_adapter(&drvdata->adapter); 587 } 588 589 static const struct of_device_id gxp_i2c_of_match[] = { 590 { .compatible = "hpe,gxp-i2c" }, 591 {}, 592 }; 593 MODULE_DEVICE_TABLE(of, gxp_i2c_of_match); 594 595 static struct platform_driver gxp_i2c_driver = { 596 .probe = gxp_i2c_probe, 597 .remove_new = gxp_i2c_remove, 598 .driver = { 599 .name = "gxp-i2c", 600 .of_match_table = gxp_i2c_of_match, 601 }, 602 }; 603 module_platform_driver(gxp_i2c_driver); 604 605 MODULE_AUTHOR("Nick Hawkins <nick.hawkins@hpe.com>"); 606 MODULE_DESCRIPTION("HPE GXP I2C bus driver"); 607 MODULE_LICENSE("GPL"); 608