1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (C) 2022 Hewlett-Packard Enterprise Development Company, L.P. */ 3 4 #include <linux/err.h> 5 #include <linux/io.h> 6 #include <linux/i2c.h> 7 #include <linux/module.h> 8 #include <linux/of_device.h> 9 #include <linux/regmap.h> 10 #include <linux/mfd/syscon.h> 11 12 #define GXP_MAX_I2C_ENGINE 10 13 static const char * const gxp_i2c_name[] = { 14 "gxp-i2c0", "gxp-i2c1", "gxp-i2c2", "gxp-i2c3", 15 "gxp-i2c4", "gxp-i2c5", "gxp-i2c6", "gxp-i2c7", 16 "gxp-i2c8", "gxp-i2c9" }; 17 18 /* GXP I2C Global interrupt status/enable register*/ 19 #define GXP_I2CINTSTAT 0x00 20 #define GXP_I2CINTEN 0x04 21 22 /* GXP I2C registers */ 23 #define GXP_I2CSTAT 0x00 24 #define MASK_STOP_EVENT 0x20 25 #define MASK_ACK 0x08 26 #define MASK_RW 0x04 27 #define GXP_I2CEVTERR 0x01 28 #define MASK_SLAVE_CMD_EVENT 0x01 29 #define MASK_SLAVE_DATA_EVENT 0x02 30 #define MASK_MASTER_EVENT 0x10 31 #define GXP_I2CSNPDAT 0x02 32 #define GXP_I2CMCMD 0x04 33 #define GXP_I2CSCMD 0x06 34 #define GXP_I2CSNPAA 0x09 35 #define GXP_I2CADVFEAT 0x0A 36 #define GXP_I2COWNADR 0x0B 37 #define GXP_I2CFREQDIV 0x0C 38 #define GXP_I2CFLTFAIR 0x0D 39 #define GXP_I2CTMOEDG 0x0E 40 #define GXP_I2CCYCTIM 0x0F 41 42 /* I2CSCMD Bits */ 43 #define SNOOP_EVT_CLR 0x80 44 #define SLAVE_EVT_CLR 0x40 45 #define SNOOP_EVT_MASK 0x20 46 #define SLAVE_EVT_MASK 0x10 47 #define SLAVE_ACK_ENAB 0x08 48 #define SLAVE_EVT_STALL 0x01 49 50 /* I2CMCMD Bits */ 51 #define MASTER_EVT_CLR 0x80 52 #define MASTER_ACK_ENAB 0x08 53 #define RW_CMD 0x04 54 #define STOP_CMD 0x02 55 #define START_CMD 0x01 56 57 /* I2CTMOEDG value */ 58 #define GXP_DATA_EDGE_RST_CTRL 0x0a /* 30ns */ 59 60 /* I2CFLTFAIR Bits */ 61 #define FILTER_CNT 0x30 62 #define FAIRNESS_CNT 0x02 63 64 enum { 65 GXP_I2C_IDLE = 0, 66 GXP_I2C_ADDR_PHASE, 67 GXP_I2C_RDATA_PHASE, 68 GXP_I2C_WDATA_PHASE, 69 GXP_I2C_ADDR_NACK, 70 GXP_I2C_DATA_NACK, 71 GXP_I2C_ERROR, 72 GXP_I2C_COMP 73 }; 74 75 struct gxp_i2c_drvdata { 76 struct device *dev; 77 void __iomem *base; 78 struct i2c_timings t; 79 u32 engine; 80 int irq; 81 struct completion completion; 82 struct i2c_adapter adapter; 83 struct i2c_msg *curr_msg; 84 int msgs_remaining; 85 int msgs_num; 86 u8 *buf; 87 size_t buf_remaining; 88 unsigned char state; 89 struct i2c_client *slave; 90 unsigned char stopped; 91 }; 92 93 static struct regmap *i2cg_map; 94 95 static void gxp_i2c_start(struct gxp_i2c_drvdata *drvdata) 96 { 97 u16 value; 98 99 drvdata->buf = drvdata->curr_msg->buf; 100 drvdata->buf_remaining = drvdata->curr_msg->len; 101 102 /* Note: Address in struct i2c_msg is 7 bits */ 103 value = drvdata->curr_msg->addr << 9; 104 105 /* Read or Write */ 106 value |= drvdata->curr_msg->flags & I2C_M_RD ? RW_CMD | START_CMD : START_CMD; 107 108 drvdata->state = GXP_I2C_ADDR_PHASE; 109 writew(value, drvdata->base + GXP_I2CMCMD); 110 } 111 112 static int gxp_i2c_master_xfer(struct i2c_adapter *adapter, 113 struct i2c_msg *msgs, int num) 114 { 115 int ret; 116 struct gxp_i2c_drvdata *drvdata = i2c_get_adapdata(adapter); 117 unsigned long time_left; 118 119 drvdata->msgs_remaining = num; 120 drvdata->curr_msg = msgs; 121 drvdata->msgs_num = num; 122 reinit_completion(&drvdata->completion); 123 124 gxp_i2c_start(drvdata); 125 126 time_left = wait_for_completion_timeout(&drvdata->completion, 127 adapter->timeout); 128 ret = num - drvdata->msgs_remaining; 129 if (time_left == 0) { 130 switch (drvdata->state) { 131 case GXP_I2C_WDATA_PHASE: 132 break; 133 case GXP_I2C_RDATA_PHASE: 134 break; 135 case GXP_I2C_ADDR_PHASE: 136 break; 137 default: 138 break; 139 } 140 return -ETIMEDOUT; 141 } 142 143 if (drvdata->state == GXP_I2C_ADDR_NACK || 144 drvdata->state == GXP_I2C_DATA_NACK) 145 return -EIO; 146 147 return ret; 148 } 149 150 static u32 gxp_i2c_func(struct i2c_adapter *adap) 151 { 152 if (IS_ENABLED(CONFIG_I2C_SLAVE)) 153 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SLAVE; 154 155 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 156 } 157 158 #if IS_ENABLED(CONFIG_I2C_SLAVE) 159 static int gxp_i2c_reg_slave(struct i2c_client *slave) 160 { 161 struct gxp_i2c_drvdata *drvdata = i2c_get_adapdata(slave->adapter); 162 163 if (drvdata->slave) 164 return -EBUSY; 165 166 if (slave->flags & I2C_CLIENT_TEN) 167 return -EAFNOSUPPORT; 168 169 drvdata->slave = slave; 170 171 writeb(slave->addr << 1, drvdata->base + GXP_I2COWNADR); 172 writeb(SLAVE_EVT_CLR | SNOOP_EVT_MASK | SLAVE_ACK_ENAB | 173 SLAVE_EVT_STALL, drvdata->base + GXP_I2CSCMD); 174 175 return 0; 176 } 177 178 static int gxp_i2c_unreg_slave(struct i2c_client *slave) 179 { 180 struct gxp_i2c_drvdata *drvdata = i2c_get_adapdata(slave->adapter); 181 182 WARN_ON(!drvdata->slave); 183 184 writeb(0x00, drvdata->base + GXP_I2COWNADR); 185 writeb(SNOOP_EVT_CLR | SLAVE_EVT_CLR | SNOOP_EVT_MASK | 186 SLAVE_EVT_MASK, drvdata->base + GXP_I2CSCMD); 187 188 drvdata->slave = NULL; 189 190 return 0; 191 } 192 #endif 193 194 static const struct i2c_algorithm gxp_i2c_algo = { 195 .master_xfer = gxp_i2c_master_xfer, 196 .functionality = gxp_i2c_func, 197 #if IS_ENABLED(CONFIG_I2C_SLAVE) 198 .reg_slave = gxp_i2c_reg_slave, 199 .unreg_slave = gxp_i2c_unreg_slave, 200 #endif 201 }; 202 203 static void gxp_i2c_stop(struct gxp_i2c_drvdata *drvdata) 204 { 205 /* Clear event and send stop */ 206 writeb(MASTER_EVT_CLR | STOP_CMD, drvdata->base + GXP_I2CMCMD); 207 208 complete(&drvdata->completion); 209 } 210 211 static void gxp_i2c_restart(struct gxp_i2c_drvdata *drvdata) 212 { 213 u16 value; 214 215 drvdata->buf = drvdata->curr_msg->buf; 216 drvdata->buf_remaining = drvdata->curr_msg->len; 217 218 value = drvdata->curr_msg->addr << 9; 219 220 if (drvdata->curr_msg->flags & I2C_M_RD) { 221 /* Read and clear master event */ 222 value |= MASTER_EVT_CLR | RW_CMD | START_CMD; 223 } else { 224 /* Write and clear master event */ 225 value |= MASTER_EVT_CLR | START_CMD; 226 } 227 228 drvdata->state = GXP_I2C_ADDR_PHASE; 229 230 writew(value, drvdata->base + GXP_I2CMCMD); 231 } 232 233 static void gxp_i2c_chk_addr_ack(struct gxp_i2c_drvdata *drvdata) 234 { 235 u16 value; 236 237 value = readb(drvdata->base + GXP_I2CSTAT); 238 if (!(value & MASK_ACK)) { 239 /* Got no ack, stop */ 240 drvdata->state = GXP_I2C_ADDR_NACK; 241 gxp_i2c_stop(drvdata); 242 return; 243 } 244 245 if (drvdata->curr_msg->flags & I2C_M_RD) { 246 /* Start to read data from slave */ 247 if (drvdata->buf_remaining == 0) { 248 /* No more data to read, stop */ 249 drvdata->msgs_remaining--; 250 drvdata->state = GXP_I2C_COMP; 251 gxp_i2c_stop(drvdata); 252 return; 253 } 254 drvdata->state = GXP_I2C_RDATA_PHASE; 255 256 if (drvdata->buf_remaining == 1) { 257 /* The last data, do not ack */ 258 writeb(MASTER_EVT_CLR | RW_CMD, 259 drvdata->base + GXP_I2CMCMD); 260 } else { 261 /* Read data and ack it */ 262 writeb(MASTER_EVT_CLR | MASTER_ACK_ENAB | 263 RW_CMD, drvdata->base + GXP_I2CMCMD); 264 } 265 } else { 266 /* Start to write first data to slave */ 267 if (drvdata->buf_remaining == 0) { 268 /* No more data to write, stop */ 269 drvdata->msgs_remaining--; 270 drvdata->state = GXP_I2C_COMP; 271 gxp_i2c_stop(drvdata); 272 return; 273 } 274 value = *drvdata->buf; 275 value = value << 8; 276 /* Clear master event */ 277 value |= MASTER_EVT_CLR; 278 drvdata->buf++; 279 drvdata->buf_remaining--; 280 drvdata->state = GXP_I2C_WDATA_PHASE; 281 writew(value, drvdata->base + GXP_I2CMCMD); 282 } 283 } 284 285 static void gxp_i2c_ack_data(struct gxp_i2c_drvdata *drvdata) 286 { 287 u8 value; 288 289 /* Store the data returned */ 290 value = readb(drvdata->base + GXP_I2CSNPDAT); 291 *drvdata->buf = value; 292 drvdata->buf++; 293 drvdata->buf_remaining--; 294 295 if (drvdata->buf_remaining == 0) { 296 /* No more data, this message is completed. */ 297 drvdata->msgs_remaining--; 298 299 if (drvdata->msgs_remaining == 0) { 300 /* No more messages, stop */ 301 drvdata->state = GXP_I2C_COMP; 302 gxp_i2c_stop(drvdata); 303 return; 304 } 305 /* Move to next message and start transfer */ 306 drvdata->curr_msg++; 307 gxp_i2c_restart(drvdata); 308 return; 309 } 310 311 /* Ack the slave to make it send next byte */ 312 drvdata->state = GXP_I2C_RDATA_PHASE; 313 if (drvdata->buf_remaining == 1) { 314 /* The last data, do not ack */ 315 writeb(MASTER_EVT_CLR | RW_CMD, 316 drvdata->base + GXP_I2CMCMD); 317 } else { 318 /* Read data and ack it */ 319 writeb(MASTER_EVT_CLR | MASTER_ACK_ENAB | 320 RW_CMD, drvdata->base + GXP_I2CMCMD); 321 } 322 } 323 324 static void gxp_i2c_chk_data_ack(struct gxp_i2c_drvdata *drvdata) 325 { 326 u16 value; 327 328 value = readb(drvdata->base + GXP_I2CSTAT); 329 if (!(value & MASK_ACK)) { 330 /* Received No ack, stop */ 331 drvdata->state = GXP_I2C_DATA_NACK; 332 gxp_i2c_stop(drvdata); 333 return; 334 } 335 336 /* Got ack, check if there is more data to write */ 337 if (drvdata->buf_remaining == 0) { 338 /* No more data, this message is completed */ 339 drvdata->msgs_remaining--; 340 341 if (drvdata->msgs_remaining == 0) { 342 /* No more messages, stop */ 343 drvdata->state = GXP_I2C_COMP; 344 gxp_i2c_stop(drvdata); 345 return; 346 } 347 /* Move to next message and start transfer */ 348 drvdata->curr_msg++; 349 gxp_i2c_restart(drvdata); 350 return; 351 } 352 353 /* Write data to slave */ 354 value = *drvdata->buf; 355 value = value << 8; 356 357 /* Clear master event */ 358 value |= MASTER_EVT_CLR; 359 drvdata->buf++; 360 drvdata->buf_remaining--; 361 drvdata->state = GXP_I2C_WDATA_PHASE; 362 writew(value, drvdata->base + GXP_I2CMCMD); 363 } 364 365 #if IS_ENABLED(CONFIG_I2C_SLAVE) 366 static bool gxp_i2c_slave_irq_handler(struct gxp_i2c_drvdata *drvdata) 367 { 368 u8 value; 369 u8 buf; 370 int ret; 371 372 value = readb(drvdata->base + GXP_I2CEVTERR); 373 374 /* Received start or stop event */ 375 if (value & MASK_SLAVE_CMD_EVENT) { 376 value = readb(drvdata->base + GXP_I2CSTAT); 377 /* Master sent stop */ 378 if (value & MASK_STOP_EVENT) { 379 if (drvdata->stopped == 0) 380 i2c_slave_event(drvdata->slave, I2C_SLAVE_STOP, &buf); 381 writeb(SLAVE_EVT_CLR | SNOOP_EVT_MASK | 382 SLAVE_ACK_ENAB | SLAVE_EVT_STALL, drvdata->base + GXP_I2CSCMD); 383 drvdata->stopped = 1; 384 } else { 385 /* Master sent start and wants to read */ 386 drvdata->stopped = 0; 387 if (value & MASK_RW) { 388 i2c_slave_event(drvdata->slave, 389 I2C_SLAVE_READ_REQUESTED, &buf); 390 value = buf << 8 | (SLAVE_EVT_CLR | SNOOP_EVT_MASK | 391 SLAVE_EVT_STALL); 392 writew(value, drvdata->base + GXP_I2CSCMD); 393 } else { 394 /* Master wants to write to us */ 395 ret = i2c_slave_event(drvdata->slave, 396 I2C_SLAVE_WRITE_REQUESTED, &buf); 397 if (!ret) { 398 /* Ack next byte from master */ 399 writeb(SLAVE_EVT_CLR | SNOOP_EVT_MASK | 400 SLAVE_ACK_ENAB | SLAVE_EVT_STALL, 401 drvdata->base + GXP_I2CSCMD); 402 } else { 403 /* Nack next byte from master */ 404 writeb(SLAVE_EVT_CLR | SNOOP_EVT_MASK | 405 SLAVE_EVT_STALL, drvdata->base + GXP_I2CSCMD); 406 } 407 } 408 } 409 } else if (value & MASK_SLAVE_DATA_EVENT) { 410 value = readb(drvdata->base + GXP_I2CSTAT); 411 /* Master wants to read */ 412 if (value & MASK_RW) { 413 /* Master wants another byte */ 414 if (value & MASK_ACK) { 415 i2c_slave_event(drvdata->slave, 416 I2C_SLAVE_READ_PROCESSED, &buf); 417 value = buf << 8 | (SLAVE_EVT_CLR | SNOOP_EVT_MASK | 418 SLAVE_EVT_STALL); 419 writew(value, drvdata->base + GXP_I2CSCMD); 420 } else { 421 /* No more bytes needed */ 422 writew(SLAVE_EVT_CLR | SNOOP_EVT_MASK | 423 SLAVE_ACK_ENAB | SLAVE_EVT_STALL, 424 drvdata->base + GXP_I2CSCMD); 425 } 426 } else { 427 /* Master wants to write to us */ 428 value = readb(drvdata->base + GXP_I2CSNPDAT); 429 buf = (uint8_t)value; 430 ret = i2c_slave_event(drvdata->slave, 431 I2C_SLAVE_WRITE_RECEIVED, &buf); 432 if (!ret) { 433 /* Ack next byte from master */ 434 writeb(SLAVE_EVT_CLR | SNOOP_EVT_MASK | 435 SLAVE_ACK_ENAB | SLAVE_EVT_STALL, 436 drvdata->base + GXP_I2CSCMD); 437 } else { 438 /* Nack next byte from master */ 439 writeb(SLAVE_EVT_CLR | SNOOP_EVT_MASK | 440 SLAVE_EVT_STALL, drvdata->base + GXP_I2CSCMD); 441 } 442 } 443 } else { 444 return false; 445 } 446 447 return true; 448 } 449 #endif 450 451 static irqreturn_t gxp_i2c_irq_handler(int irq, void *_drvdata) 452 { 453 struct gxp_i2c_drvdata *drvdata = (struct gxp_i2c_drvdata *)_drvdata; 454 u32 value; 455 456 /* Check if the interrupt is for the current engine */ 457 regmap_read(i2cg_map, GXP_I2CINTSTAT, &value); 458 if (!(value & BIT(drvdata->engine))) 459 return IRQ_NONE; 460 461 value = readb(drvdata->base + GXP_I2CEVTERR); 462 463 /* Error */ 464 if (value & ~(MASK_MASTER_EVENT | MASK_SLAVE_CMD_EVENT | 465 MASK_SLAVE_DATA_EVENT)) { 466 /* Clear all events */ 467 writeb(0x00, drvdata->base + GXP_I2CEVTERR); 468 drvdata->state = GXP_I2C_ERROR; 469 gxp_i2c_stop(drvdata); 470 return IRQ_HANDLED; 471 } 472 473 if (IS_ENABLED(CONFIG_I2C_SLAVE)) { 474 /* Slave mode */ 475 if (value & (MASK_SLAVE_CMD_EVENT | MASK_SLAVE_DATA_EVENT)) { 476 if (gxp_i2c_slave_irq_handler(drvdata)) 477 return IRQ_HANDLED; 478 return IRQ_NONE; 479 } 480 } 481 482 /* Master mode */ 483 switch (drvdata->state) { 484 case GXP_I2C_ADDR_PHASE: 485 gxp_i2c_chk_addr_ack(drvdata); 486 break; 487 488 case GXP_I2C_RDATA_PHASE: 489 gxp_i2c_ack_data(drvdata); 490 break; 491 492 case GXP_I2C_WDATA_PHASE: 493 gxp_i2c_chk_data_ack(drvdata); 494 break; 495 } 496 497 return IRQ_HANDLED; 498 } 499 500 static void gxp_i2c_init(struct gxp_i2c_drvdata *drvdata) 501 { 502 drvdata->state = GXP_I2C_IDLE; 503 writeb(2000000 / drvdata->t.bus_freq_hz, 504 drvdata->base + GXP_I2CFREQDIV); 505 writeb(FILTER_CNT | FAIRNESS_CNT, 506 drvdata->base + GXP_I2CFLTFAIR); 507 writeb(GXP_DATA_EDGE_RST_CTRL, drvdata->base + GXP_I2CTMOEDG); 508 writeb(0x00, drvdata->base + GXP_I2CCYCTIM); 509 writeb(0x00, drvdata->base + GXP_I2CSNPAA); 510 writeb(0x00, drvdata->base + GXP_I2CADVFEAT); 511 writeb(SNOOP_EVT_CLR | SLAVE_EVT_CLR | SNOOP_EVT_MASK | 512 SLAVE_EVT_MASK, drvdata->base + GXP_I2CSCMD); 513 writeb(MASTER_EVT_CLR, drvdata->base + GXP_I2CMCMD); 514 writeb(0x00, drvdata->base + GXP_I2CEVTERR); 515 writeb(0x00, drvdata->base + GXP_I2COWNADR); 516 } 517 518 static int gxp_i2c_probe(struct platform_device *pdev) 519 { 520 struct gxp_i2c_drvdata *drvdata; 521 int rc; 522 struct i2c_adapter *adapter; 523 524 if (!i2cg_map) { 525 i2cg_map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 526 "hpe,sysreg"); 527 if (IS_ERR(i2cg_map)) { 528 return dev_err_probe(&pdev->dev, IS_ERR(i2cg_map), 529 "failed to map i2cg_handle\n"); 530 } 531 532 /* Disable interrupt */ 533 regmap_update_bits(i2cg_map, GXP_I2CINTEN, 0x00000FFF, 0); 534 } 535 536 drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), 537 GFP_KERNEL); 538 if (!drvdata) 539 return -ENOMEM; 540 541 platform_set_drvdata(pdev, drvdata); 542 drvdata->dev = &pdev->dev; 543 init_completion(&drvdata->completion); 544 545 drvdata->base = devm_platform_ioremap_resource(pdev, 0); 546 if (IS_ERR(drvdata->base)) 547 return PTR_ERR(drvdata->base); 548 549 /* Use physical memory address to determine which I2C engine this is. */ 550 drvdata->engine = ((size_t)drvdata->base & 0xf00) >> 8; 551 552 if (drvdata->engine >= GXP_MAX_I2C_ENGINE) { 553 return dev_err_probe(&pdev->dev, -EINVAL, "i2c engine% is unsupported\n", 554 drvdata->engine); 555 } 556 557 rc = platform_get_irq(pdev, 0); 558 if (rc < 0) 559 return rc; 560 561 drvdata->irq = rc; 562 rc = devm_request_irq(&pdev->dev, drvdata->irq, gxp_i2c_irq_handler, 563 IRQF_SHARED, gxp_i2c_name[drvdata->engine], drvdata); 564 if (rc < 0) 565 return dev_err_probe(&pdev->dev, rc, "irq request failed\n"); 566 567 i2c_parse_fw_timings(&pdev->dev, &drvdata->t, true); 568 569 gxp_i2c_init(drvdata); 570 571 /* Enable interrupt */ 572 regmap_update_bits(i2cg_map, GXP_I2CINTEN, BIT(drvdata->engine), 573 BIT(drvdata->engine)); 574 575 adapter = &drvdata->adapter; 576 i2c_set_adapdata(adapter, drvdata); 577 578 adapter->owner = THIS_MODULE; 579 strscpy(adapter->name, "HPE GXP I2C adapter", sizeof(adapter->name)); 580 adapter->algo = &gxp_i2c_algo; 581 adapter->dev.parent = &pdev->dev; 582 adapter->dev.of_node = pdev->dev.of_node; 583 584 rc = i2c_add_adapter(adapter); 585 if (rc) 586 return dev_err_probe(&pdev->dev, rc, "i2c add adapter failed\n"); 587 588 return 0; 589 } 590 591 static int gxp_i2c_remove(struct platform_device *pdev) 592 { 593 struct gxp_i2c_drvdata *drvdata = platform_get_drvdata(pdev); 594 595 /* Disable interrupt */ 596 regmap_update_bits(i2cg_map, GXP_I2CINTEN, BIT(drvdata->engine), 0); 597 i2c_del_adapter(&drvdata->adapter); 598 599 return 0; 600 } 601 602 static const struct of_device_id gxp_i2c_of_match[] = { 603 { .compatible = "hpe,gxp-i2c" }, 604 {}, 605 }; 606 MODULE_DEVICE_TABLE(of, gxp_i2c_of_match); 607 608 static struct platform_driver gxp_i2c_driver = { 609 .probe = gxp_i2c_probe, 610 .remove = gxp_i2c_remove, 611 .driver = { 612 .name = "gxp-i2c", 613 .of_match_table = gxp_i2c_of_match, 614 }, 615 }; 616 module_platform_driver(gxp_i2c_driver); 617 618 MODULE_AUTHOR("Nick Hawkins <nick.hawkins@hpe.com>"); 619 MODULE_DESCRIPTION("HPE GXP I2C bus driver"); 620 MODULE_LICENSE("GPL"); 621