1 /** 2 * i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver 3 * 4 * Copyright (C) 2013 Samsung Electronics Co., Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 14 #include <linux/i2c.h> 15 #include <linux/time.h> 16 #include <linux/interrupt.h> 17 #include <linux/delay.h> 18 #include <linux/errno.h> 19 #include <linux/err.h> 20 #include <linux/platform_device.h> 21 #include <linux/clk.h> 22 #include <linux/slab.h> 23 #include <linux/io.h> 24 #include <linux/of_address.h> 25 #include <linux/of_device.h> 26 #include <linux/of_irq.h> 27 #include <linux/spinlock.h> 28 29 /* 30 * HSI2C controller from Samsung supports 2 modes of operation 31 * 1. Auto mode: Where in master automatically controls the whole transaction 32 * 2. Manual mode: Software controls the transaction by issuing commands 33 * START, READ, WRITE, STOP, RESTART in I2C_MANUAL_CMD register. 34 * 35 * Operation mode can be selected by setting AUTO_MODE bit in I2C_CONF register 36 * 37 * Special bits are available for both modes of operation to set commands 38 * and for checking transfer status 39 */ 40 41 /* Register Map */ 42 #define HSI2C_CTL 0x00 43 #define HSI2C_FIFO_CTL 0x04 44 #define HSI2C_TRAILIG_CTL 0x08 45 #define HSI2C_CLK_CTL 0x0C 46 #define HSI2C_CLK_SLOT 0x10 47 #define HSI2C_INT_ENABLE 0x20 48 #define HSI2C_INT_STATUS 0x24 49 #define HSI2C_ERR_STATUS 0x2C 50 #define HSI2C_FIFO_STATUS 0x30 51 #define HSI2C_TX_DATA 0x34 52 #define HSI2C_RX_DATA 0x38 53 #define HSI2C_CONF 0x40 54 #define HSI2C_AUTO_CONF 0x44 55 #define HSI2C_TIMEOUT 0x48 56 #define HSI2C_MANUAL_CMD 0x4C 57 #define HSI2C_TRANS_STATUS 0x50 58 #define HSI2C_TIMING_HS1 0x54 59 #define HSI2C_TIMING_HS2 0x58 60 #define HSI2C_TIMING_HS3 0x5C 61 #define HSI2C_TIMING_FS1 0x60 62 #define HSI2C_TIMING_FS2 0x64 63 #define HSI2C_TIMING_FS3 0x68 64 #define HSI2C_TIMING_SLA 0x6C 65 #define HSI2C_ADDR 0x70 66 67 /* I2C_CTL Register bits */ 68 #define HSI2C_FUNC_MODE_I2C (1u << 0) 69 #define HSI2C_MASTER (1u << 3) 70 #define HSI2C_RXCHON (1u << 6) 71 #define HSI2C_TXCHON (1u << 7) 72 #define HSI2C_SW_RST (1u << 31) 73 74 /* I2C_FIFO_CTL Register bits */ 75 #define HSI2C_RXFIFO_EN (1u << 0) 76 #define HSI2C_TXFIFO_EN (1u << 1) 77 #define HSI2C_RXFIFO_TRIGGER_LEVEL(x) ((x) << 4) 78 #define HSI2C_TXFIFO_TRIGGER_LEVEL(x) ((x) << 16) 79 80 /* I2C_TRAILING_CTL Register bits */ 81 #define HSI2C_TRAILING_COUNT (0xf) 82 83 /* I2C_INT_EN Register bits */ 84 #define HSI2C_INT_TX_ALMOSTEMPTY_EN (1u << 0) 85 #define HSI2C_INT_RX_ALMOSTFULL_EN (1u << 1) 86 #define HSI2C_INT_TRAILING_EN (1u << 6) 87 88 /* I2C_INT_STAT Register bits */ 89 #define HSI2C_INT_TX_ALMOSTEMPTY (1u << 0) 90 #define HSI2C_INT_RX_ALMOSTFULL (1u << 1) 91 #define HSI2C_INT_TX_UNDERRUN (1u << 2) 92 #define HSI2C_INT_TX_OVERRUN (1u << 3) 93 #define HSI2C_INT_RX_UNDERRUN (1u << 4) 94 #define HSI2C_INT_RX_OVERRUN (1u << 5) 95 #define HSI2C_INT_TRAILING (1u << 6) 96 #define HSI2C_INT_I2C (1u << 9) 97 98 #define HSI2C_INT_TRANS_DONE (1u << 7) 99 #define HSI2C_INT_TRANS_ABORT (1u << 8) 100 #define HSI2C_INT_NO_DEV_ACK (1u << 9) 101 #define HSI2C_INT_NO_DEV (1u << 10) 102 #define HSI2C_INT_TIMEOUT (1u << 11) 103 #define HSI2C_INT_I2C_TRANS (HSI2C_INT_TRANS_DONE | \ 104 HSI2C_INT_TRANS_ABORT | \ 105 HSI2C_INT_NO_DEV_ACK | \ 106 HSI2C_INT_NO_DEV | \ 107 HSI2C_INT_TIMEOUT) 108 109 /* I2C_FIFO_STAT Register bits */ 110 #define HSI2C_RX_FIFO_EMPTY (1u << 24) 111 #define HSI2C_RX_FIFO_FULL (1u << 23) 112 #define HSI2C_RX_FIFO_LVL(x) ((x >> 16) & 0x7f) 113 #define HSI2C_TX_FIFO_EMPTY (1u << 8) 114 #define HSI2C_TX_FIFO_FULL (1u << 7) 115 #define HSI2C_TX_FIFO_LVL(x) ((x >> 0) & 0x7f) 116 117 /* I2C_CONF Register bits */ 118 #define HSI2C_AUTO_MODE (1u << 31) 119 #define HSI2C_10BIT_ADDR_MODE (1u << 30) 120 #define HSI2C_HS_MODE (1u << 29) 121 122 /* I2C_AUTO_CONF Register bits */ 123 #define HSI2C_READ_WRITE (1u << 16) 124 #define HSI2C_STOP_AFTER_TRANS (1u << 17) 125 #define HSI2C_MASTER_RUN (1u << 31) 126 127 /* I2C_TIMEOUT Register bits */ 128 #define HSI2C_TIMEOUT_EN (1u << 31) 129 #define HSI2C_TIMEOUT_MASK 0xff 130 131 /* I2C_MANUAL_CMD register bits */ 132 #define HSI2C_CMD_READ_DATA (1u << 4) 133 #define HSI2C_CMD_SEND_STOP (1u << 2) 134 135 /* I2C_TRANS_STATUS register bits */ 136 #define HSI2C_MASTER_BUSY (1u << 17) 137 #define HSI2C_SLAVE_BUSY (1u << 16) 138 139 /* I2C_TRANS_STATUS register bits for Exynos5 variant */ 140 #define HSI2C_TIMEOUT_AUTO (1u << 4) 141 #define HSI2C_NO_DEV (1u << 3) 142 #define HSI2C_NO_DEV_ACK (1u << 2) 143 #define HSI2C_TRANS_ABORT (1u << 1) 144 #define HSI2C_TRANS_DONE (1u << 0) 145 146 /* I2C_TRANS_STATUS register bits for Exynos7 variant */ 147 #define HSI2C_MASTER_ST_MASK 0xf 148 #define HSI2C_MASTER_ST_IDLE 0x0 149 #define HSI2C_MASTER_ST_START 0x1 150 #define HSI2C_MASTER_ST_RESTART 0x2 151 #define HSI2C_MASTER_ST_STOP 0x3 152 #define HSI2C_MASTER_ST_MASTER_ID 0x4 153 #define HSI2C_MASTER_ST_ADDR0 0x5 154 #define HSI2C_MASTER_ST_ADDR1 0x6 155 #define HSI2C_MASTER_ST_ADDR2 0x7 156 #define HSI2C_MASTER_ST_ADDR_SR 0x8 157 #define HSI2C_MASTER_ST_READ 0x9 158 #define HSI2C_MASTER_ST_WRITE 0xa 159 #define HSI2C_MASTER_ST_NO_ACK 0xb 160 #define HSI2C_MASTER_ST_LOSE 0xc 161 #define HSI2C_MASTER_ST_WAIT 0xd 162 #define HSI2C_MASTER_ST_WAIT_CMD 0xe 163 164 /* I2C_ADDR register bits */ 165 #define HSI2C_SLV_ADDR_SLV(x) ((x & 0x3ff) << 0) 166 #define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10) 167 #define HSI2C_MASTER_ID(x) ((x & 0xff) << 24) 168 #define MASTER_ID(x) ((x & 0x7) + 0x08) 169 170 /* 171 * Controller operating frequency, timing values for operation 172 * are calculated against this frequency 173 */ 174 #define HSI2C_HS_TX_CLOCK 1000000 175 #define HSI2C_FS_TX_CLOCK 100000 176 177 #define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(100)) 178 179 #define HSI2C_EXYNOS7 BIT(0) 180 181 struct exynos5_i2c { 182 struct i2c_adapter adap; 183 unsigned int suspended:1; 184 185 struct i2c_msg *msg; 186 struct completion msg_complete; 187 unsigned int msg_ptr; 188 189 unsigned int irq; 190 191 void __iomem *regs; 192 struct clk *clk; 193 struct device *dev; 194 int state; 195 196 spinlock_t lock; /* IRQ synchronization */ 197 198 /* 199 * Since the TRANS_DONE bit is cleared on read, and we may read it 200 * either during an IRQ or after a transaction, keep track of its 201 * state here. 202 */ 203 int trans_done; 204 205 /* Controller operating frequency */ 206 unsigned int op_clock; 207 208 /* Version of HS-I2C Hardware */ 209 const struct exynos_hsi2c_variant *variant; 210 }; 211 212 /** 213 * struct exynos_hsi2c_variant - platform specific HSI2C driver data 214 * @fifo_depth: the fifo depth supported by the HSI2C module 215 * 216 * Specifies platform specific configuration of HSI2C module. 217 * Note: A structure for driver specific platform data is used for future 218 * expansion of its usage. 219 */ 220 struct exynos_hsi2c_variant { 221 unsigned int fifo_depth; 222 unsigned int hw; 223 }; 224 225 static const struct exynos_hsi2c_variant exynos5250_hsi2c_data = { 226 .fifo_depth = 64, 227 }; 228 229 static const struct exynos_hsi2c_variant exynos5260_hsi2c_data = { 230 .fifo_depth = 16, 231 }; 232 233 static const struct exynos_hsi2c_variant exynos7_hsi2c_data = { 234 .fifo_depth = 16, 235 .hw = HSI2C_EXYNOS7, 236 }; 237 238 static const struct of_device_id exynos5_i2c_match[] = { 239 { 240 .compatible = "samsung,exynos5-hsi2c", 241 .data = &exynos5250_hsi2c_data 242 }, { 243 .compatible = "samsung,exynos5250-hsi2c", 244 .data = &exynos5250_hsi2c_data 245 }, { 246 .compatible = "samsung,exynos5260-hsi2c", 247 .data = &exynos5260_hsi2c_data 248 }, { 249 .compatible = "samsung,exynos7-hsi2c", 250 .data = &exynos7_hsi2c_data 251 }, {}, 252 }; 253 MODULE_DEVICE_TABLE(of, exynos5_i2c_match); 254 255 static void exynos5_i2c_clr_pend_irq(struct exynos5_i2c *i2c) 256 { 257 writel(readl(i2c->regs + HSI2C_INT_STATUS), 258 i2c->regs + HSI2C_INT_STATUS); 259 } 260 261 /* 262 * exynos5_i2c_set_timing: updates the registers with appropriate 263 * timing values calculated 264 * 265 * Returns 0 on success, -EINVAL if the cycle length cannot 266 * be calculated. 267 */ 268 static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, bool hs_timings) 269 { 270 u32 i2c_timing_s1; 271 u32 i2c_timing_s2; 272 u32 i2c_timing_s3; 273 u32 i2c_timing_sla; 274 unsigned int t_start_su, t_start_hd; 275 unsigned int t_stop_su; 276 unsigned int t_data_su, t_data_hd; 277 unsigned int t_scl_l, t_scl_h; 278 unsigned int t_sr_release; 279 unsigned int t_ftl_cycle; 280 unsigned int clkin = clk_get_rate(i2c->clk); 281 unsigned int op_clk = hs_timings ? i2c->op_clock : 282 (i2c->op_clock >= HSI2C_HS_TX_CLOCK) ? HSI2C_FS_TX_CLOCK : 283 i2c->op_clock; 284 int div, clk_cycle, temp; 285 286 /* 287 * In case of HSI2C controller in Exynos5 series 288 * FPCLK / FI2C = 289 * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE 290 * 291 * In case of HSI2C controllers in Exynos7 series 292 * FPCLK / FI2C = 293 * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + FLT_CYCLE 294 * 295 * clk_cycle := TSCLK_L + TSCLK_H 296 * temp := (CLK_DIV + 1) * (clk_cycle + 2) 297 * 298 * Constraints: 4 <= temp, 0 <= CLK_DIV < 256, 2 <= clk_cycle <= 510 299 * 300 */ 301 t_ftl_cycle = (readl(i2c->regs + HSI2C_CONF) >> 16) & 0x7; 302 temp = clkin / op_clk - 8 - t_ftl_cycle; 303 if (i2c->variant->hw != HSI2C_EXYNOS7) 304 temp -= t_ftl_cycle; 305 div = temp / 512; 306 clk_cycle = temp / (div + 1) - 2; 307 if (temp < 4 || div >= 256 || clk_cycle < 2) { 308 dev_err(i2c->dev, "%s clock set-up failed\n", 309 hs_timings ? "HS" : "FS"); 310 return -EINVAL; 311 } 312 313 t_scl_l = clk_cycle / 2; 314 t_scl_h = clk_cycle / 2; 315 t_start_su = t_scl_l; 316 t_start_hd = t_scl_l; 317 t_stop_su = t_scl_l; 318 t_data_su = t_scl_l / 2; 319 t_data_hd = t_scl_l / 2; 320 t_sr_release = clk_cycle; 321 322 i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8; 323 i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0; 324 i2c_timing_s3 = div << 16 | t_sr_release << 0; 325 i2c_timing_sla = t_data_hd << 0; 326 327 dev_dbg(i2c->dev, "tSTART_SU: %X, tSTART_HD: %X, tSTOP_SU: %X\n", 328 t_start_su, t_start_hd, t_stop_su); 329 dev_dbg(i2c->dev, "tDATA_SU: %X, tSCL_L: %X, tSCL_H: %X\n", 330 t_data_su, t_scl_l, t_scl_h); 331 dev_dbg(i2c->dev, "nClkDiv: %X, tSR_RELEASE: %X\n", 332 div, t_sr_release); 333 dev_dbg(i2c->dev, "tDATA_HD: %X\n", t_data_hd); 334 335 if (hs_timings) { 336 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_HS1); 337 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_HS2); 338 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3); 339 } else { 340 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_FS1); 341 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_FS2); 342 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3); 343 } 344 writel(i2c_timing_sla, i2c->regs + HSI2C_TIMING_SLA); 345 346 return 0; 347 } 348 349 static int exynos5_hsi2c_clock_setup(struct exynos5_i2c *i2c) 350 { 351 /* always set Fast Speed timings */ 352 int ret = exynos5_i2c_set_timing(i2c, false); 353 354 if (ret < 0 || i2c->op_clock < HSI2C_HS_TX_CLOCK) 355 return ret; 356 357 return exynos5_i2c_set_timing(i2c, true); 358 } 359 360 /* 361 * exynos5_i2c_init: configures the controller for I2C functionality 362 * Programs I2C controller for Master mode operation 363 */ 364 static void exynos5_i2c_init(struct exynos5_i2c *i2c) 365 { 366 u32 i2c_conf = readl(i2c->regs + HSI2C_CONF); 367 u32 i2c_timeout = readl(i2c->regs + HSI2C_TIMEOUT); 368 369 /* Clear to disable Timeout */ 370 i2c_timeout &= ~HSI2C_TIMEOUT_EN; 371 writel(i2c_timeout, i2c->regs + HSI2C_TIMEOUT); 372 373 writel((HSI2C_FUNC_MODE_I2C | HSI2C_MASTER), 374 i2c->regs + HSI2C_CTL); 375 writel(HSI2C_TRAILING_COUNT, i2c->regs + HSI2C_TRAILIG_CTL); 376 377 if (i2c->op_clock >= HSI2C_HS_TX_CLOCK) { 378 writel(HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr)), 379 i2c->regs + HSI2C_ADDR); 380 i2c_conf |= HSI2C_HS_MODE; 381 } 382 383 writel(i2c_conf | HSI2C_AUTO_MODE, i2c->regs + HSI2C_CONF); 384 } 385 386 static void exynos5_i2c_reset(struct exynos5_i2c *i2c) 387 { 388 u32 i2c_ctl; 389 390 /* Set and clear the bit for reset */ 391 i2c_ctl = readl(i2c->regs + HSI2C_CTL); 392 i2c_ctl |= HSI2C_SW_RST; 393 writel(i2c_ctl, i2c->regs + HSI2C_CTL); 394 395 i2c_ctl = readl(i2c->regs + HSI2C_CTL); 396 i2c_ctl &= ~HSI2C_SW_RST; 397 writel(i2c_ctl, i2c->regs + HSI2C_CTL); 398 399 /* We don't expect calculations to fail during the run */ 400 exynos5_hsi2c_clock_setup(i2c); 401 /* Initialize the configure registers */ 402 exynos5_i2c_init(i2c); 403 } 404 405 /* 406 * exynos5_i2c_irq: top level IRQ servicing routine 407 * 408 * INT_STATUS registers gives the interrupt details. Further, 409 * FIFO_STATUS or TRANS_STATUS registers are to be check for detailed 410 * state of the bus. 411 */ 412 static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id) 413 { 414 struct exynos5_i2c *i2c = dev_id; 415 u32 fifo_level, int_status, fifo_status, trans_status; 416 unsigned char byte; 417 int len = 0; 418 419 i2c->state = -EINVAL; 420 421 spin_lock(&i2c->lock); 422 423 int_status = readl(i2c->regs + HSI2C_INT_STATUS); 424 writel(int_status, i2c->regs + HSI2C_INT_STATUS); 425 426 /* handle interrupt related to the transfer status */ 427 if (i2c->variant->hw == HSI2C_EXYNOS7) { 428 if (int_status & HSI2C_INT_TRANS_DONE) { 429 i2c->trans_done = 1; 430 i2c->state = 0; 431 } else if (int_status & HSI2C_INT_TRANS_ABORT) { 432 dev_dbg(i2c->dev, "Deal with arbitration lose\n"); 433 i2c->state = -EAGAIN; 434 goto stop; 435 } else if (int_status & HSI2C_INT_NO_DEV_ACK) { 436 dev_dbg(i2c->dev, "No ACK from device\n"); 437 i2c->state = -ENXIO; 438 goto stop; 439 } else if (int_status & HSI2C_INT_NO_DEV) { 440 dev_dbg(i2c->dev, "No device\n"); 441 i2c->state = -ENXIO; 442 goto stop; 443 } else if (int_status & HSI2C_INT_TIMEOUT) { 444 dev_dbg(i2c->dev, "Accessing device timed out\n"); 445 i2c->state = -ETIMEDOUT; 446 goto stop; 447 } 448 } else if (int_status & HSI2C_INT_I2C) { 449 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS); 450 if (trans_status & HSI2C_NO_DEV_ACK) { 451 dev_dbg(i2c->dev, "No ACK from device\n"); 452 i2c->state = -ENXIO; 453 goto stop; 454 } else if (trans_status & HSI2C_NO_DEV) { 455 dev_dbg(i2c->dev, "No device\n"); 456 i2c->state = -ENXIO; 457 goto stop; 458 } else if (trans_status & HSI2C_TRANS_ABORT) { 459 dev_dbg(i2c->dev, "Deal with arbitration lose\n"); 460 i2c->state = -EAGAIN; 461 goto stop; 462 } else if (trans_status & HSI2C_TIMEOUT_AUTO) { 463 dev_dbg(i2c->dev, "Accessing device timed out\n"); 464 i2c->state = -ETIMEDOUT; 465 goto stop; 466 } else if (trans_status & HSI2C_TRANS_DONE) { 467 i2c->trans_done = 1; 468 i2c->state = 0; 469 } 470 } 471 472 if ((i2c->msg->flags & I2C_M_RD) && (int_status & 473 (HSI2C_INT_TRAILING | HSI2C_INT_RX_ALMOSTFULL))) { 474 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS); 475 fifo_level = HSI2C_RX_FIFO_LVL(fifo_status); 476 len = min(fifo_level, i2c->msg->len - i2c->msg_ptr); 477 478 while (len > 0) { 479 byte = (unsigned char) 480 readl(i2c->regs + HSI2C_RX_DATA); 481 i2c->msg->buf[i2c->msg_ptr++] = byte; 482 len--; 483 } 484 i2c->state = 0; 485 } else if (int_status & HSI2C_INT_TX_ALMOSTEMPTY) { 486 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS); 487 fifo_level = HSI2C_TX_FIFO_LVL(fifo_status); 488 489 len = i2c->variant->fifo_depth - fifo_level; 490 if (len > (i2c->msg->len - i2c->msg_ptr)) { 491 u32 int_en = readl(i2c->regs + HSI2C_INT_ENABLE); 492 493 int_en &= ~HSI2C_INT_TX_ALMOSTEMPTY_EN; 494 writel(int_en, i2c->regs + HSI2C_INT_ENABLE); 495 len = i2c->msg->len - i2c->msg_ptr; 496 } 497 498 while (len > 0) { 499 byte = i2c->msg->buf[i2c->msg_ptr++]; 500 writel(byte, i2c->regs + HSI2C_TX_DATA); 501 len--; 502 } 503 i2c->state = 0; 504 } 505 506 stop: 507 if ((i2c->trans_done && (i2c->msg->len == i2c->msg_ptr)) || 508 (i2c->state < 0)) { 509 writel(0, i2c->regs + HSI2C_INT_ENABLE); 510 exynos5_i2c_clr_pend_irq(i2c); 511 complete(&i2c->msg_complete); 512 } 513 514 spin_unlock(&i2c->lock); 515 516 return IRQ_HANDLED; 517 } 518 519 /* 520 * exynos5_i2c_wait_bus_idle 521 * 522 * Wait for the bus to go idle, indicated by the MASTER_BUSY bit being 523 * cleared. 524 * 525 * Returns -EBUSY if the bus cannot be bought to idle 526 */ 527 static int exynos5_i2c_wait_bus_idle(struct exynos5_i2c *i2c) 528 { 529 unsigned long stop_time; 530 u32 trans_status; 531 532 /* wait for 100 milli seconds for the bus to be idle */ 533 stop_time = jiffies + msecs_to_jiffies(100) + 1; 534 do { 535 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS); 536 if (!(trans_status & HSI2C_MASTER_BUSY)) 537 return 0; 538 539 usleep_range(50, 200); 540 } while (time_before(jiffies, stop_time)); 541 542 return -EBUSY; 543 } 544 545 static void exynos5_i2c_bus_recover(struct exynos5_i2c *i2c) 546 { 547 u32 val; 548 549 val = readl(i2c->regs + HSI2C_CTL) | HSI2C_RXCHON; 550 writel(val, i2c->regs + HSI2C_CTL); 551 val = readl(i2c->regs + HSI2C_CONF) & ~HSI2C_AUTO_MODE; 552 writel(val, i2c->regs + HSI2C_CONF); 553 554 /* 555 * Specification says master should send nine clock pulses. It can be 556 * emulated by sending manual read command (nine pulses for read eight 557 * bits + one pulse for NACK). 558 */ 559 writel(HSI2C_CMD_READ_DATA, i2c->regs + HSI2C_MANUAL_CMD); 560 exynos5_i2c_wait_bus_idle(i2c); 561 writel(HSI2C_CMD_SEND_STOP, i2c->regs + HSI2C_MANUAL_CMD); 562 exynos5_i2c_wait_bus_idle(i2c); 563 564 val = readl(i2c->regs + HSI2C_CTL) & ~HSI2C_RXCHON; 565 writel(val, i2c->regs + HSI2C_CTL); 566 val = readl(i2c->regs + HSI2C_CONF) | HSI2C_AUTO_MODE; 567 writel(val, i2c->regs + HSI2C_CONF); 568 } 569 570 static void exynos5_i2c_bus_check(struct exynos5_i2c *i2c) 571 { 572 unsigned long timeout; 573 574 if (i2c->variant->hw != HSI2C_EXYNOS7) 575 return; 576 577 /* 578 * HSI2C_MASTER_ST_LOSE state in EXYNOS7 variant before transaction 579 * indicates that bus is stuck (SDA is low). In such case bus recovery 580 * can be performed. 581 */ 582 timeout = jiffies + msecs_to_jiffies(100); 583 for (;;) { 584 u32 st = readl(i2c->regs + HSI2C_TRANS_STATUS); 585 586 if ((st & HSI2C_MASTER_ST_MASK) != HSI2C_MASTER_ST_LOSE) 587 return; 588 589 if (time_is_before_jiffies(timeout)) 590 return; 591 592 exynos5_i2c_bus_recover(i2c); 593 } 594 } 595 596 /* 597 * exynos5_i2c_message_start: Configures the bus and starts the xfer 598 * i2c: struct exynos5_i2c pointer for the current bus 599 * stop: Enables stop after transfer if set. Set for last transfer of 600 * in the list of messages. 601 * 602 * Configures the bus for read/write function 603 * Sets chip address to talk to, message length to be sent. 604 * Enables appropriate interrupts and sends start xfer command. 605 */ 606 static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop) 607 { 608 u32 i2c_ctl; 609 u32 int_en = 0; 610 u32 i2c_auto_conf = 0; 611 u32 fifo_ctl; 612 unsigned long flags; 613 unsigned short trig_lvl; 614 615 if (i2c->variant->hw == HSI2C_EXYNOS7) 616 int_en |= HSI2C_INT_I2C_TRANS; 617 else 618 int_en |= HSI2C_INT_I2C; 619 620 i2c_ctl = readl(i2c->regs + HSI2C_CTL); 621 i2c_ctl &= ~(HSI2C_TXCHON | HSI2C_RXCHON); 622 fifo_ctl = HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN; 623 624 if (i2c->msg->flags & I2C_M_RD) { 625 i2c_ctl |= HSI2C_RXCHON; 626 627 i2c_auto_conf |= HSI2C_READ_WRITE; 628 629 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ? 630 (i2c->variant->fifo_depth * 3 / 4) : i2c->msg->len; 631 fifo_ctl |= HSI2C_RXFIFO_TRIGGER_LEVEL(trig_lvl); 632 633 int_en |= (HSI2C_INT_RX_ALMOSTFULL_EN | 634 HSI2C_INT_TRAILING_EN); 635 } else { 636 i2c_ctl |= HSI2C_TXCHON; 637 638 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ? 639 (i2c->variant->fifo_depth * 1 / 4) : i2c->msg->len; 640 fifo_ctl |= HSI2C_TXFIFO_TRIGGER_LEVEL(trig_lvl); 641 642 int_en |= HSI2C_INT_TX_ALMOSTEMPTY_EN; 643 } 644 645 writel(HSI2C_SLV_ADDR_MAS(i2c->msg->addr), i2c->regs + HSI2C_ADDR); 646 647 writel(fifo_ctl, i2c->regs + HSI2C_FIFO_CTL); 648 writel(i2c_ctl, i2c->regs + HSI2C_CTL); 649 650 exynos5_i2c_bus_check(i2c); 651 652 /* 653 * Enable interrupts before starting the transfer so that we don't 654 * miss any INT_I2C interrupts. 655 */ 656 spin_lock_irqsave(&i2c->lock, flags); 657 writel(int_en, i2c->regs + HSI2C_INT_ENABLE); 658 659 if (stop == 1) 660 i2c_auto_conf |= HSI2C_STOP_AFTER_TRANS; 661 i2c_auto_conf |= i2c->msg->len; 662 i2c_auto_conf |= HSI2C_MASTER_RUN; 663 writel(i2c_auto_conf, i2c->regs + HSI2C_AUTO_CONF); 664 spin_unlock_irqrestore(&i2c->lock, flags); 665 } 666 667 static int exynos5_i2c_xfer_msg(struct exynos5_i2c *i2c, 668 struct i2c_msg *msgs, int stop) 669 { 670 unsigned long timeout; 671 int ret; 672 673 i2c->msg = msgs; 674 i2c->msg_ptr = 0; 675 i2c->trans_done = 0; 676 677 reinit_completion(&i2c->msg_complete); 678 679 exynos5_i2c_message_start(i2c, stop); 680 681 timeout = wait_for_completion_timeout(&i2c->msg_complete, 682 EXYNOS5_I2C_TIMEOUT); 683 if (timeout == 0) 684 ret = -ETIMEDOUT; 685 else 686 ret = i2c->state; 687 688 /* 689 * If this is the last message to be transfered (stop == 1) 690 * Then check if the bus can be brought back to idle. 691 */ 692 if (ret == 0 && stop) 693 ret = exynos5_i2c_wait_bus_idle(i2c); 694 695 if (ret < 0) { 696 exynos5_i2c_reset(i2c); 697 if (ret == -ETIMEDOUT) 698 dev_warn(i2c->dev, "%s timeout\n", 699 (msgs->flags & I2C_M_RD) ? "rx" : "tx"); 700 } 701 702 /* Return the state as in interrupt routine */ 703 return ret; 704 } 705 706 static int exynos5_i2c_xfer(struct i2c_adapter *adap, 707 struct i2c_msg *msgs, int num) 708 { 709 struct exynos5_i2c *i2c = adap->algo_data; 710 int i = 0, ret = 0, stop = 0; 711 712 if (i2c->suspended) { 713 dev_err(i2c->dev, "HS-I2C is not initialized.\n"); 714 return -EIO; 715 } 716 717 ret = clk_enable(i2c->clk); 718 if (ret) 719 return ret; 720 721 for (i = 0; i < num; i++, msgs++) { 722 stop = (i == num - 1); 723 724 ret = exynos5_i2c_xfer_msg(i2c, msgs, stop); 725 726 if (ret < 0) 727 goto out; 728 } 729 730 if (i == num) { 731 ret = num; 732 } else { 733 /* Only one message, cannot access the device */ 734 if (i == 1) 735 ret = -EREMOTEIO; 736 else 737 ret = i; 738 739 dev_warn(i2c->dev, "xfer message failed\n"); 740 } 741 742 out: 743 clk_disable(i2c->clk); 744 return ret; 745 } 746 747 static u32 exynos5_i2c_func(struct i2c_adapter *adap) 748 { 749 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 750 } 751 752 static const struct i2c_algorithm exynos5_i2c_algorithm = { 753 .master_xfer = exynos5_i2c_xfer, 754 .functionality = exynos5_i2c_func, 755 }; 756 757 static int exynos5_i2c_probe(struct platform_device *pdev) 758 { 759 struct device_node *np = pdev->dev.of_node; 760 struct exynos5_i2c *i2c; 761 struct resource *mem; 762 int ret; 763 764 i2c = devm_kzalloc(&pdev->dev, sizeof(struct exynos5_i2c), GFP_KERNEL); 765 if (!i2c) 766 return -ENOMEM; 767 768 if (of_property_read_u32(np, "clock-frequency", &i2c->op_clock)) 769 i2c->op_clock = HSI2C_FS_TX_CLOCK; 770 771 strlcpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name)); 772 i2c->adap.owner = THIS_MODULE; 773 i2c->adap.algo = &exynos5_i2c_algorithm; 774 i2c->adap.retries = 3; 775 776 i2c->dev = &pdev->dev; 777 i2c->clk = devm_clk_get(&pdev->dev, "hsi2c"); 778 if (IS_ERR(i2c->clk)) { 779 dev_err(&pdev->dev, "cannot get clock\n"); 780 return -ENOENT; 781 } 782 783 ret = clk_prepare_enable(i2c->clk); 784 if (ret) 785 return ret; 786 787 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 788 i2c->regs = devm_ioremap_resource(&pdev->dev, mem); 789 if (IS_ERR(i2c->regs)) { 790 ret = PTR_ERR(i2c->regs); 791 goto err_clk; 792 } 793 794 i2c->adap.dev.of_node = np; 795 i2c->adap.algo_data = i2c; 796 i2c->adap.dev.parent = &pdev->dev; 797 798 /* Clear pending interrupts from u-boot or misc causes */ 799 exynos5_i2c_clr_pend_irq(i2c); 800 801 spin_lock_init(&i2c->lock); 802 init_completion(&i2c->msg_complete); 803 804 i2c->irq = ret = platform_get_irq(pdev, 0); 805 if (ret <= 0) { 806 dev_err(&pdev->dev, "cannot find HS-I2C IRQ\n"); 807 ret = -EINVAL; 808 goto err_clk; 809 } 810 811 ret = devm_request_irq(&pdev->dev, i2c->irq, exynos5_i2c_irq, 812 IRQF_NO_SUSPEND | IRQF_ONESHOT, 813 dev_name(&pdev->dev), i2c); 814 815 if (ret != 0) { 816 dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n", i2c->irq); 817 goto err_clk; 818 } 819 820 i2c->variant = of_device_get_match_data(&pdev->dev); 821 822 ret = exynos5_hsi2c_clock_setup(i2c); 823 if (ret) 824 goto err_clk; 825 826 exynos5_i2c_reset(i2c); 827 828 ret = i2c_add_adapter(&i2c->adap); 829 if (ret < 0) 830 goto err_clk; 831 832 platform_set_drvdata(pdev, i2c); 833 834 clk_disable(i2c->clk); 835 836 return 0; 837 838 err_clk: 839 clk_disable_unprepare(i2c->clk); 840 return ret; 841 } 842 843 static int exynos5_i2c_remove(struct platform_device *pdev) 844 { 845 struct exynos5_i2c *i2c = platform_get_drvdata(pdev); 846 847 i2c_del_adapter(&i2c->adap); 848 849 clk_unprepare(i2c->clk); 850 851 return 0; 852 } 853 854 #ifdef CONFIG_PM_SLEEP 855 static int exynos5_i2c_suspend_noirq(struct device *dev) 856 { 857 struct exynos5_i2c *i2c = dev_get_drvdata(dev); 858 859 i2c->suspended = 1; 860 861 clk_unprepare(i2c->clk); 862 863 return 0; 864 } 865 866 static int exynos5_i2c_resume_noirq(struct device *dev) 867 { 868 struct exynos5_i2c *i2c = dev_get_drvdata(dev); 869 int ret = 0; 870 871 ret = clk_prepare_enable(i2c->clk); 872 if (ret) 873 return ret; 874 875 ret = exynos5_hsi2c_clock_setup(i2c); 876 if (ret) { 877 clk_disable_unprepare(i2c->clk); 878 return ret; 879 } 880 881 exynos5_i2c_init(i2c); 882 clk_disable(i2c->clk); 883 i2c->suspended = 0; 884 885 return 0; 886 } 887 #endif 888 889 static const struct dev_pm_ops exynos5_i2c_dev_pm_ops = { 890 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(exynos5_i2c_suspend_noirq, 891 exynos5_i2c_resume_noirq) 892 }; 893 894 static struct platform_driver exynos5_i2c_driver = { 895 .probe = exynos5_i2c_probe, 896 .remove = exynos5_i2c_remove, 897 .driver = { 898 .name = "exynos5-hsi2c", 899 .pm = &exynos5_i2c_dev_pm_ops, 900 .of_match_table = exynos5_i2c_match, 901 }, 902 }; 903 904 module_platform_driver(exynos5_i2c_driver); 905 906 MODULE_DESCRIPTION("Exynos5 HS-I2C Bus driver"); 907 MODULE_AUTHOR("Naveen Krishna Chatradhi, <ch.naveen@samsung.com>"); 908 MODULE_AUTHOR("Taekgyun Ko, <taeggyun.ko@samsung.com>"); 909 MODULE_LICENSE("GPL v2"); 910