1 /** 2 * i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver 3 * 4 * Copyright (C) 2013 Samsung Electronics Co., Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 14 #include <linux/i2c.h> 15 #include <linux/init.h> 16 #include <linux/time.h> 17 #include <linux/interrupt.h> 18 #include <linux/delay.h> 19 #include <linux/errno.h> 20 #include <linux/err.h> 21 #include <linux/platform_device.h> 22 #include <linux/clk.h> 23 #include <linux/slab.h> 24 #include <linux/io.h> 25 #include <linux/of_address.h> 26 #include <linux/of_irq.h> 27 #include <linux/spinlock.h> 28 29 /* 30 * HSI2C controller from Samsung supports 2 modes of operation 31 * 1. Auto mode: Where in master automatically controls the whole transaction 32 * 2. Manual mode: Software controls the transaction by issuing commands 33 * START, READ, WRITE, STOP, RESTART in I2C_MANUAL_CMD register. 34 * 35 * Operation mode can be selected by setting AUTO_MODE bit in I2C_CONF register 36 * 37 * Special bits are available for both modes of operation to set commands 38 * and for checking transfer status 39 */ 40 41 /* Register Map */ 42 #define HSI2C_CTL 0x00 43 #define HSI2C_FIFO_CTL 0x04 44 #define HSI2C_TRAILIG_CTL 0x08 45 #define HSI2C_CLK_CTL 0x0C 46 #define HSI2C_CLK_SLOT 0x10 47 #define HSI2C_INT_ENABLE 0x20 48 #define HSI2C_INT_STATUS 0x24 49 #define HSI2C_ERR_STATUS 0x2C 50 #define HSI2C_FIFO_STATUS 0x30 51 #define HSI2C_TX_DATA 0x34 52 #define HSI2C_RX_DATA 0x38 53 #define HSI2C_CONF 0x40 54 #define HSI2C_AUTO_CONF 0x44 55 #define HSI2C_TIMEOUT 0x48 56 #define HSI2C_MANUAL_CMD 0x4C 57 #define HSI2C_TRANS_STATUS 0x50 58 #define HSI2C_TIMING_HS1 0x54 59 #define HSI2C_TIMING_HS2 0x58 60 #define HSI2C_TIMING_HS3 0x5C 61 #define HSI2C_TIMING_FS1 0x60 62 #define HSI2C_TIMING_FS2 0x64 63 #define HSI2C_TIMING_FS3 0x68 64 #define HSI2C_TIMING_SLA 0x6C 65 #define HSI2C_ADDR 0x70 66 67 /* I2C_CTL Register bits */ 68 #define HSI2C_FUNC_MODE_I2C (1u << 0) 69 #define HSI2C_MASTER (1u << 3) 70 #define HSI2C_RXCHON (1u << 6) 71 #define HSI2C_TXCHON (1u << 7) 72 #define HSI2C_SW_RST (1u << 31) 73 74 /* I2C_FIFO_CTL Register bits */ 75 #define HSI2C_RXFIFO_EN (1u << 0) 76 #define HSI2C_TXFIFO_EN (1u << 1) 77 #define HSI2C_RXFIFO_TRIGGER_LEVEL(x) ((x) << 4) 78 #define HSI2C_TXFIFO_TRIGGER_LEVEL(x) ((x) << 16) 79 80 /* As per user manual FIFO max depth is 64bytes */ 81 #define HSI2C_FIFO_MAX 0x40 82 /* default trigger levels for Tx and Rx FIFOs */ 83 #define HSI2C_DEF_TXFIFO_LVL (HSI2C_FIFO_MAX - 0x30) 84 #define HSI2C_DEF_RXFIFO_LVL (HSI2C_FIFO_MAX - 0x10) 85 86 /* I2C_TRAILING_CTL Register bits */ 87 #define HSI2C_TRAILING_COUNT (0xf) 88 89 /* I2C_INT_EN Register bits */ 90 #define HSI2C_INT_TX_ALMOSTEMPTY_EN (1u << 0) 91 #define HSI2C_INT_RX_ALMOSTFULL_EN (1u << 1) 92 #define HSI2C_INT_TRAILING_EN (1u << 6) 93 #define HSI2C_INT_I2C_EN (1u << 9) 94 95 /* I2C_INT_STAT Register bits */ 96 #define HSI2C_INT_TX_ALMOSTEMPTY (1u << 0) 97 #define HSI2C_INT_RX_ALMOSTFULL (1u << 1) 98 #define HSI2C_INT_TX_UNDERRUN (1u << 2) 99 #define HSI2C_INT_TX_OVERRUN (1u << 3) 100 #define HSI2C_INT_RX_UNDERRUN (1u << 4) 101 #define HSI2C_INT_RX_OVERRUN (1u << 5) 102 #define HSI2C_INT_TRAILING (1u << 6) 103 #define HSI2C_INT_I2C (1u << 9) 104 105 /* I2C_FIFO_STAT Register bits */ 106 #define HSI2C_RX_FIFO_EMPTY (1u << 24) 107 #define HSI2C_RX_FIFO_FULL (1u << 23) 108 #define HSI2C_RX_FIFO_LVL(x) ((x >> 16) & 0x7f) 109 #define HSI2C_TX_FIFO_EMPTY (1u << 8) 110 #define HSI2C_TX_FIFO_FULL (1u << 7) 111 #define HSI2C_TX_FIFO_LVL(x) ((x >> 0) & 0x7f) 112 113 /* I2C_CONF Register bits */ 114 #define HSI2C_AUTO_MODE (1u << 31) 115 #define HSI2C_10BIT_ADDR_MODE (1u << 30) 116 #define HSI2C_HS_MODE (1u << 29) 117 118 /* I2C_AUTO_CONF Register bits */ 119 #define HSI2C_READ_WRITE (1u << 16) 120 #define HSI2C_STOP_AFTER_TRANS (1u << 17) 121 #define HSI2C_MASTER_RUN (1u << 31) 122 123 /* I2C_TIMEOUT Register bits */ 124 #define HSI2C_TIMEOUT_EN (1u << 31) 125 #define HSI2C_TIMEOUT_MASK 0xff 126 127 /* I2C_TRANS_STATUS register bits */ 128 #define HSI2C_MASTER_BUSY (1u << 17) 129 #define HSI2C_SLAVE_BUSY (1u << 16) 130 #define HSI2C_TIMEOUT_AUTO (1u << 4) 131 #define HSI2C_NO_DEV (1u << 3) 132 #define HSI2C_NO_DEV_ACK (1u << 2) 133 #define HSI2C_TRANS_ABORT (1u << 1) 134 #define HSI2C_TRANS_DONE (1u << 0) 135 136 /* I2C_ADDR register bits */ 137 #define HSI2C_SLV_ADDR_SLV(x) ((x & 0x3ff) << 0) 138 #define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10) 139 #define HSI2C_MASTER_ID(x) ((x & 0xff) << 24) 140 #define MASTER_ID(x) ((x & 0x7) + 0x08) 141 142 /* 143 * Controller operating frequency, timing values for operation 144 * are calculated against this frequency 145 */ 146 #define HSI2C_HS_TX_CLOCK 1000000 147 #define HSI2C_FS_TX_CLOCK 100000 148 #define HSI2C_HIGH_SPD 1 149 #define HSI2C_FAST_SPD 0 150 151 #define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(1000)) 152 153 struct exynos5_i2c { 154 struct i2c_adapter adap; 155 unsigned int suspended:1; 156 157 struct i2c_msg *msg; 158 struct completion msg_complete; 159 unsigned int msg_ptr; 160 161 unsigned int irq; 162 163 void __iomem *regs; 164 struct clk *clk; 165 struct device *dev; 166 int state; 167 168 spinlock_t lock; /* IRQ synchronization */ 169 170 /* 171 * Since the TRANS_DONE bit is cleared on read, and we may read it 172 * either during an IRQ or after a transaction, keep track of its 173 * state here. 174 */ 175 int trans_done; 176 177 /* Controller operating frequency */ 178 unsigned int fs_clock; 179 unsigned int hs_clock; 180 181 /* 182 * HSI2C Controller can operate in 183 * 1. High speed upto 3.4Mbps 184 * 2. Fast speed upto 1Mbps 185 */ 186 int speed_mode; 187 }; 188 189 static const struct of_device_id exynos5_i2c_match[] = { 190 { .compatible = "samsung,exynos5-hsi2c" }, 191 {}, 192 }; 193 MODULE_DEVICE_TABLE(of, exynos5_i2c_match); 194 195 static void exynos5_i2c_clr_pend_irq(struct exynos5_i2c *i2c) 196 { 197 writel(readl(i2c->regs + HSI2C_INT_STATUS), 198 i2c->regs + HSI2C_INT_STATUS); 199 } 200 201 /* 202 * exynos5_i2c_set_timing: updates the registers with appropriate 203 * timing values calculated 204 * 205 * Returns 0 on success, -EINVAL if the cycle length cannot 206 * be calculated. 207 */ 208 static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, int mode) 209 { 210 u32 i2c_timing_s1; 211 u32 i2c_timing_s2; 212 u32 i2c_timing_s3; 213 u32 i2c_timing_sla; 214 unsigned int t_start_su, t_start_hd; 215 unsigned int t_stop_su; 216 unsigned int t_data_su, t_data_hd; 217 unsigned int t_scl_l, t_scl_h; 218 unsigned int t_sr_release; 219 unsigned int t_ftl_cycle; 220 unsigned int clkin = clk_get_rate(i2c->clk); 221 unsigned int div, utemp0 = 0, utemp1 = 0, clk_cycle; 222 unsigned int op_clk = (mode == HSI2C_HIGH_SPD) ? 223 i2c->hs_clock : i2c->fs_clock; 224 225 /* 226 * FPCLK / FI2C = 227 * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE 228 * utemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) 229 * utemp1 = (TSCLK_L + TSCLK_H + 2) 230 */ 231 t_ftl_cycle = (readl(i2c->regs + HSI2C_CONF) >> 16) & 0x7; 232 utemp0 = (clkin / op_clk) - 8 - 2 * t_ftl_cycle; 233 234 /* CLK_DIV max is 256 */ 235 for (div = 0; div < 256; div++) { 236 utemp1 = utemp0 / (div + 1); 237 238 /* 239 * SCL_L and SCL_H each has max value of 255 240 * Hence, For the clk_cycle to the have right value 241 * utemp1 has to be less then 512 and more than 4. 242 */ 243 if ((utemp1 < 512) && (utemp1 > 4)) { 244 clk_cycle = utemp1 - 2; 245 break; 246 } else if (div == 255) { 247 dev_warn(i2c->dev, "Failed to calculate divisor"); 248 return -EINVAL; 249 } 250 } 251 252 t_scl_l = clk_cycle / 2; 253 t_scl_h = clk_cycle / 2; 254 t_start_su = t_scl_l; 255 t_start_hd = t_scl_l; 256 t_stop_su = t_scl_l; 257 t_data_su = t_scl_l / 2; 258 t_data_hd = t_scl_l / 2; 259 t_sr_release = clk_cycle; 260 261 i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8; 262 i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0; 263 i2c_timing_s3 = div << 16 | t_sr_release << 0; 264 i2c_timing_sla = t_data_hd << 0; 265 266 dev_dbg(i2c->dev, "tSTART_SU: %X, tSTART_HD: %X, tSTOP_SU: %X\n", 267 t_start_su, t_start_hd, t_stop_su); 268 dev_dbg(i2c->dev, "tDATA_SU: %X, tSCL_L: %X, tSCL_H: %X\n", 269 t_data_su, t_scl_l, t_scl_h); 270 dev_dbg(i2c->dev, "nClkDiv: %X, tSR_RELEASE: %X\n", 271 div, t_sr_release); 272 dev_dbg(i2c->dev, "tDATA_HD: %X\n", t_data_hd); 273 274 if (mode == HSI2C_HIGH_SPD) { 275 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_HS1); 276 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_HS2); 277 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3); 278 } else { 279 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_FS1); 280 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_FS2); 281 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3); 282 } 283 writel(i2c_timing_sla, i2c->regs + HSI2C_TIMING_SLA); 284 285 return 0; 286 } 287 288 static int exynos5_hsi2c_clock_setup(struct exynos5_i2c *i2c) 289 { 290 /* 291 * Configure the Fast speed timing values 292 * Even the High Speed mode initially starts with Fast mode 293 */ 294 if (exynos5_i2c_set_timing(i2c, HSI2C_FAST_SPD)) { 295 dev_err(i2c->dev, "HSI2C FS Clock set up failed\n"); 296 return -EINVAL; 297 } 298 299 /* configure the High speed timing values */ 300 if (i2c->speed_mode == HSI2C_HIGH_SPD) { 301 if (exynos5_i2c_set_timing(i2c, HSI2C_HIGH_SPD)) { 302 dev_err(i2c->dev, "HSI2C HS Clock set up failed\n"); 303 return -EINVAL; 304 } 305 } 306 307 return 0; 308 } 309 310 /* 311 * exynos5_i2c_init: configures the controller for I2C functionality 312 * Programs I2C controller for Master mode operation 313 */ 314 static void exynos5_i2c_init(struct exynos5_i2c *i2c) 315 { 316 u32 i2c_conf = readl(i2c->regs + HSI2C_CONF); 317 u32 i2c_timeout = readl(i2c->regs + HSI2C_TIMEOUT); 318 319 /* Clear to disable Timeout */ 320 i2c_timeout &= ~HSI2C_TIMEOUT_EN; 321 writel(i2c_timeout, i2c->regs + HSI2C_TIMEOUT); 322 323 writel((HSI2C_FUNC_MODE_I2C | HSI2C_MASTER), 324 i2c->regs + HSI2C_CTL); 325 writel(HSI2C_TRAILING_COUNT, i2c->regs + HSI2C_TRAILIG_CTL); 326 327 if (i2c->speed_mode == HSI2C_HIGH_SPD) { 328 writel(HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr)), 329 i2c->regs + HSI2C_ADDR); 330 i2c_conf |= HSI2C_HS_MODE; 331 } 332 333 writel(i2c_conf | HSI2C_AUTO_MODE, i2c->regs + HSI2C_CONF); 334 } 335 336 static void exynos5_i2c_reset(struct exynos5_i2c *i2c) 337 { 338 u32 i2c_ctl; 339 340 /* Set and clear the bit for reset */ 341 i2c_ctl = readl(i2c->regs + HSI2C_CTL); 342 i2c_ctl |= HSI2C_SW_RST; 343 writel(i2c_ctl, i2c->regs + HSI2C_CTL); 344 345 i2c_ctl = readl(i2c->regs + HSI2C_CTL); 346 i2c_ctl &= ~HSI2C_SW_RST; 347 writel(i2c_ctl, i2c->regs + HSI2C_CTL); 348 349 /* We don't expect calculations to fail during the run */ 350 exynos5_hsi2c_clock_setup(i2c); 351 /* Initialize the configure registers */ 352 exynos5_i2c_init(i2c); 353 } 354 355 /* 356 * exynos5_i2c_irq: top level IRQ servicing routine 357 * 358 * INT_STATUS registers gives the interrupt details. Further, 359 * FIFO_STATUS or TRANS_STATUS registers are to be check for detailed 360 * state of the bus. 361 */ 362 static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id) 363 { 364 struct exynos5_i2c *i2c = dev_id; 365 u32 fifo_level, int_status, fifo_status, trans_status; 366 unsigned char byte; 367 int len = 0; 368 369 i2c->state = -EINVAL; 370 371 spin_lock(&i2c->lock); 372 373 int_status = readl(i2c->regs + HSI2C_INT_STATUS); 374 writel(int_status, i2c->regs + HSI2C_INT_STATUS); 375 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS); 376 377 /* handle interrupt related to the transfer status */ 378 if (int_status & HSI2C_INT_I2C) { 379 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS); 380 if (trans_status & HSI2C_NO_DEV_ACK) { 381 dev_dbg(i2c->dev, "No ACK from device\n"); 382 i2c->state = -ENXIO; 383 goto stop; 384 } else if (trans_status & HSI2C_NO_DEV) { 385 dev_dbg(i2c->dev, "No device\n"); 386 i2c->state = -ENXIO; 387 goto stop; 388 } else if (trans_status & HSI2C_TRANS_ABORT) { 389 dev_dbg(i2c->dev, "Deal with arbitration lose\n"); 390 i2c->state = -EAGAIN; 391 goto stop; 392 } else if (trans_status & HSI2C_TIMEOUT_AUTO) { 393 dev_dbg(i2c->dev, "Accessing device timed out\n"); 394 i2c->state = -EAGAIN; 395 goto stop; 396 } else if (trans_status & HSI2C_TRANS_DONE) { 397 i2c->trans_done = 1; 398 i2c->state = 0; 399 } 400 } 401 402 if ((i2c->msg->flags & I2C_M_RD) && (int_status & 403 (HSI2C_INT_TRAILING | HSI2C_INT_RX_ALMOSTFULL))) { 404 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS); 405 fifo_level = HSI2C_RX_FIFO_LVL(fifo_status); 406 len = min(fifo_level, i2c->msg->len - i2c->msg_ptr); 407 408 while (len > 0) { 409 byte = (unsigned char) 410 readl(i2c->regs + HSI2C_RX_DATA); 411 i2c->msg->buf[i2c->msg_ptr++] = byte; 412 len--; 413 } 414 i2c->state = 0; 415 } else if (int_status & HSI2C_INT_TX_ALMOSTEMPTY) { 416 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS); 417 fifo_level = HSI2C_TX_FIFO_LVL(fifo_status); 418 419 len = HSI2C_FIFO_MAX - fifo_level; 420 if (len > (i2c->msg->len - i2c->msg_ptr)) 421 len = i2c->msg->len - i2c->msg_ptr; 422 423 while (len > 0) { 424 byte = i2c->msg->buf[i2c->msg_ptr++]; 425 writel(byte, i2c->regs + HSI2C_TX_DATA); 426 len--; 427 } 428 i2c->state = 0; 429 } 430 431 stop: 432 if ((i2c->trans_done && (i2c->msg->len == i2c->msg_ptr)) || 433 (i2c->state < 0)) { 434 writel(0, i2c->regs + HSI2C_INT_ENABLE); 435 exynos5_i2c_clr_pend_irq(i2c); 436 complete(&i2c->msg_complete); 437 } 438 439 spin_unlock(&i2c->lock); 440 441 return IRQ_HANDLED; 442 } 443 444 /* 445 * exynos5_i2c_wait_bus_idle 446 * 447 * Wait for the bus to go idle, indicated by the MASTER_BUSY bit being 448 * cleared. 449 * 450 * Returns -EBUSY if the bus cannot be bought to idle 451 */ 452 static int exynos5_i2c_wait_bus_idle(struct exynos5_i2c *i2c) 453 { 454 unsigned long stop_time; 455 u32 trans_status; 456 457 /* wait for 100 milli seconds for the bus to be idle */ 458 stop_time = jiffies + msecs_to_jiffies(100) + 1; 459 do { 460 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS); 461 if (!(trans_status & HSI2C_MASTER_BUSY)) 462 return 0; 463 464 usleep_range(50, 200); 465 } while (time_before(jiffies, stop_time)); 466 467 return -EBUSY; 468 } 469 470 /* 471 * exynos5_i2c_message_start: Configures the bus and starts the xfer 472 * i2c: struct exynos5_i2c pointer for the current bus 473 * stop: Enables stop after transfer if set. Set for last transfer of 474 * in the list of messages. 475 * 476 * Configures the bus for read/write function 477 * Sets chip address to talk to, message length to be sent. 478 * Enables appropriate interrupts and sends start xfer command. 479 */ 480 static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop) 481 { 482 u32 i2c_ctl; 483 u32 int_en = HSI2C_INT_I2C_EN; 484 u32 i2c_auto_conf = 0; 485 u32 fifo_ctl; 486 unsigned long flags; 487 488 i2c_ctl = readl(i2c->regs + HSI2C_CTL); 489 i2c_ctl &= ~(HSI2C_TXCHON | HSI2C_RXCHON); 490 fifo_ctl = HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN; 491 492 if (i2c->msg->flags & I2C_M_RD) { 493 i2c_ctl |= HSI2C_RXCHON; 494 495 i2c_auto_conf = HSI2C_READ_WRITE; 496 497 fifo_ctl |= HSI2C_RXFIFO_TRIGGER_LEVEL(HSI2C_DEF_TXFIFO_LVL); 498 int_en |= (HSI2C_INT_RX_ALMOSTFULL_EN | 499 HSI2C_INT_TRAILING_EN); 500 } else { 501 i2c_ctl |= HSI2C_TXCHON; 502 503 fifo_ctl |= HSI2C_TXFIFO_TRIGGER_LEVEL(HSI2C_DEF_RXFIFO_LVL); 504 int_en |= HSI2C_INT_TX_ALMOSTEMPTY_EN; 505 } 506 507 writel(HSI2C_SLV_ADDR_MAS(i2c->msg->addr), i2c->regs + HSI2C_ADDR); 508 509 writel(fifo_ctl, i2c->regs + HSI2C_FIFO_CTL); 510 writel(i2c_ctl, i2c->regs + HSI2C_CTL); 511 512 513 /* 514 * Enable interrupts before starting the transfer so that we don't 515 * miss any INT_I2C interrupts. 516 */ 517 spin_lock_irqsave(&i2c->lock, flags); 518 writel(int_en, i2c->regs + HSI2C_INT_ENABLE); 519 520 if (stop == 1) 521 i2c_auto_conf |= HSI2C_STOP_AFTER_TRANS; 522 i2c_auto_conf |= i2c->msg->len; 523 i2c_auto_conf |= HSI2C_MASTER_RUN; 524 writel(i2c_auto_conf, i2c->regs + HSI2C_AUTO_CONF); 525 spin_unlock_irqrestore(&i2c->lock, flags); 526 } 527 528 static int exynos5_i2c_xfer_msg(struct exynos5_i2c *i2c, 529 struct i2c_msg *msgs, int stop) 530 { 531 unsigned long timeout; 532 int ret; 533 534 i2c->msg = msgs; 535 i2c->msg_ptr = 0; 536 i2c->trans_done = 0; 537 538 reinit_completion(&i2c->msg_complete); 539 540 exynos5_i2c_message_start(i2c, stop); 541 542 timeout = wait_for_completion_timeout(&i2c->msg_complete, 543 EXYNOS5_I2C_TIMEOUT); 544 if (timeout == 0) 545 ret = -ETIMEDOUT; 546 else 547 ret = i2c->state; 548 549 /* 550 * If this is the last message to be transfered (stop == 1) 551 * Then check if the bus can be brought back to idle. 552 */ 553 if (ret == 0 && stop) 554 ret = exynos5_i2c_wait_bus_idle(i2c); 555 556 if (ret < 0) { 557 exynos5_i2c_reset(i2c); 558 if (ret == -ETIMEDOUT) 559 dev_warn(i2c->dev, "%s timeout\n", 560 (msgs->flags & I2C_M_RD) ? "rx" : "tx"); 561 } 562 563 /* Return the state as in interrupt routine */ 564 return ret; 565 } 566 567 static int exynos5_i2c_xfer(struct i2c_adapter *adap, 568 struct i2c_msg *msgs, int num) 569 { 570 struct exynos5_i2c *i2c = (struct exynos5_i2c *)adap->algo_data; 571 int i = 0, ret = 0, stop = 0; 572 573 if (i2c->suspended) { 574 dev_err(i2c->dev, "HS-I2C is not initialzed.\n"); 575 return -EIO; 576 } 577 578 clk_prepare_enable(i2c->clk); 579 580 for (i = 0; i < num; i++, msgs++) { 581 stop = (i == num - 1); 582 583 ret = exynos5_i2c_xfer_msg(i2c, msgs, stop); 584 585 if (ret < 0) 586 goto out; 587 } 588 589 if (i == num) { 590 ret = num; 591 } else { 592 /* Only one message, cannot access the device */ 593 if (i == 1) 594 ret = -EREMOTEIO; 595 else 596 ret = i; 597 598 dev_warn(i2c->dev, "xfer message failed\n"); 599 } 600 601 out: 602 clk_disable_unprepare(i2c->clk); 603 return ret; 604 } 605 606 static u32 exynos5_i2c_func(struct i2c_adapter *adap) 607 { 608 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 609 } 610 611 static const struct i2c_algorithm exynos5_i2c_algorithm = { 612 .master_xfer = exynos5_i2c_xfer, 613 .functionality = exynos5_i2c_func, 614 }; 615 616 static int exynos5_i2c_probe(struct platform_device *pdev) 617 { 618 struct device_node *np = pdev->dev.of_node; 619 struct exynos5_i2c *i2c; 620 struct resource *mem; 621 unsigned int op_clock; 622 int ret; 623 624 i2c = devm_kzalloc(&pdev->dev, sizeof(struct exynos5_i2c), GFP_KERNEL); 625 if (!i2c) { 626 dev_err(&pdev->dev, "no memory for state\n"); 627 return -ENOMEM; 628 } 629 630 if (of_property_read_u32(np, "clock-frequency", &op_clock)) { 631 i2c->speed_mode = HSI2C_FAST_SPD; 632 i2c->fs_clock = HSI2C_FS_TX_CLOCK; 633 } else { 634 if (op_clock >= HSI2C_HS_TX_CLOCK) { 635 i2c->speed_mode = HSI2C_HIGH_SPD; 636 i2c->fs_clock = HSI2C_FS_TX_CLOCK; 637 i2c->hs_clock = op_clock; 638 } else { 639 i2c->speed_mode = HSI2C_FAST_SPD; 640 i2c->fs_clock = op_clock; 641 } 642 } 643 644 strlcpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name)); 645 i2c->adap.owner = THIS_MODULE; 646 i2c->adap.algo = &exynos5_i2c_algorithm; 647 i2c->adap.retries = 3; 648 649 i2c->dev = &pdev->dev; 650 i2c->clk = devm_clk_get(&pdev->dev, "hsi2c"); 651 if (IS_ERR(i2c->clk)) { 652 dev_err(&pdev->dev, "cannot get clock\n"); 653 return -ENOENT; 654 } 655 656 clk_prepare_enable(i2c->clk); 657 658 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 659 i2c->regs = devm_ioremap_resource(&pdev->dev, mem); 660 if (IS_ERR(i2c->regs)) { 661 ret = PTR_ERR(i2c->regs); 662 goto err_clk; 663 } 664 665 i2c->adap.dev.of_node = np; 666 i2c->adap.algo_data = i2c; 667 i2c->adap.dev.parent = &pdev->dev; 668 669 /* Clear pending interrupts from u-boot or misc causes */ 670 exynos5_i2c_clr_pend_irq(i2c); 671 672 spin_lock_init(&i2c->lock); 673 init_completion(&i2c->msg_complete); 674 675 i2c->irq = ret = platform_get_irq(pdev, 0); 676 if (ret <= 0) { 677 dev_err(&pdev->dev, "cannot find HS-I2C IRQ\n"); 678 ret = -EINVAL; 679 goto err_clk; 680 } 681 682 ret = devm_request_irq(&pdev->dev, i2c->irq, exynos5_i2c_irq, 683 IRQF_NO_SUSPEND | IRQF_ONESHOT, 684 dev_name(&pdev->dev), i2c); 685 686 if (ret != 0) { 687 dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n", i2c->irq); 688 goto err_clk; 689 } 690 691 ret = exynos5_hsi2c_clock_setup(i2c); 692 if (ret) 693 goto err_clk; 694 695 exynos5_i2c_init(i2c); 696 697 ret = i2c_add_adapter(&i2c->adap); 698 if (ret < 0) { 699 dev_err(&pdev->dev, "failed to add bus to i2c core\n"); 700 goto err_clk; 701 } 702 703 platform_set_drvdata(pdev, i2c); 704 705 err_clk: 706 clk_disable_unprepare(i2c->clk); 707 return ret; 708 } 709 710 static int exynos5_i2c_remove(struct platform_device *pdev) 711 { 712 struct exynos5_i2c *i2c = platform_get_drvdata(pdev); 713 714 i2c_del_adapter(&i2c->adap); 715 716 return 0; 717 } 718 719 static int exynos5_i2c_suspend_noirq(struct device *dev) 720 { 721 struct platform_device *pdev = to_platform_device(dev); 722 struct exynos5_i2c *i2c = platform_get_drvdata(pdev); 723 724 i2c->suspended = 1; 725 726 return 0; 727 } 728 729 static int exynos5_i2c_resume_noirq(struct device *dev) 730 { 731 struct platform_device *pdev = to_platform_device(dev); 732 struct exynos5_i2c *i2c = platform_get_drvdata(pdev); 733 int ret = 0; 734 735 clk_prepare_enable(i2c->clk); 736 737 ret = exynos5_hsi2c_clock_setup(i2c); 738 if (ret) { 739 clk_disable_unprepare(i2c->clk); 740 return ret; 741 } 742 743 exynos5_i2c_init(i2c); 744 clk_disable_unprepare(i2c->clk); 745 i2c->suspended = 0; 746 747 return 0; 748 } 749 750 static SIMPLE_DEV_PM_OPS(exynos5_i2c_dev_pm_ops, exynos5_i2c_suspend_noirq, 751 exynos5_i2c_resume_noirq); 752 753 static struct platform_driver exynos5_i2c_driver = { 754 .probe = exynos5_i2c_probe, 755 .remove = exynos5_i2c_remove, 756 .driver = { 757 .owner = THIS_MODULE, 758 .name = "exynos5-hsi2c", 759 .pm = &exynos5_i2c_dev_pm_ops, 760 .of_match_table = exynos5_i2c_match, 761 }, 762 }; 763 764 module_platform_driver(exynos5_i2c_driver); 765 766 MODULE_DESCRIPTION("Exynos5 HS-I2C Bus driver"); 767 MODULE_AUTHOR("Naveen Krishna Chatradhi, <ch.naveen@samsung.com>"); 768 MODULE_AUTHOR("Taekgyun Ko, <taeggyun.ko@samsung.com>"); 769 MODULE_LICENSE("GPL v2"); 770