1 /** 2 * i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver 3 * 4 * Copyright (C) 2013 Samsung Electronics Co., Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 14 #include <linux/i2c.h> 15 #include <linux/time.h> 16 #include <linux/interrupt.h> 17 #include <linux/delay.h> 18 #include <linux/errno.h> 19 #include <linux/err.h> 20 #include <linux/platform_device.h> 21 #include <linux/clk.h> 22 #include <linux/slab.h> 23 #include <linux/io.h> 24 #include <linux/of_address.h> 25 #include <linux/of_irq.h> 26 #include <linux/spinlock.h> 27 28 /* 29 * HSI2C controller from Samsung supports 2 modes of operation 30 * 1. Auto mode: Where in master automatically controls the whole transaction 31 * 2. Manual mode: Software controls the transaction by issuing commands 32 * START, READ, WRITE, STOP, RESTART in I2C_MANUAL_CMD register. 33 * 34 * Operation mode can be selected by setting AUTO_MODE bit in I2C_CONF register 35 * 36 * Special bits are available for both modes of operation to set commands 37 * and for checking transfer status 38 */ 39 40 /* Register Map */ 41 #define HSI2C_CTL 0x00 42 #define HSI2C_FIFO_CTL 0x04 43 #define HSI2C_TRAILIG_CTL 0x08 44 #define HSI2C_CLK_CTL 0x0C 45 #define HSI2C_CLK_SLOT 0x10 46 #define HSI2C_INT_ENABLE 0x20 47 #define HSI2C_INT_STATUS 0x24 48 #define HSI2C_ERR_STATUS 0x2C 49 #define HSI2C_FIFO_STATUS 0x30 50 #define HSI2C_TX_DATA 0x34 51 #define HSI2C_RX_DATA 0x38 52 #define HSI2C_CONF 0x40 53 #define HSI2C_AUTO_CONF 0x44 54 #define HSI2C_TIMEOUT 0x48 55 #define HSI2C_MANUAL_CMD 0x4C 56 #define HSI2C_TRANS_STATUS 0x50 57 #define HSI2C_TIMING_HS1 0x54 58 #define HSI2C_TIMING_HS2 0x58 59 #define HSI2C_TIMING_HS3 0x5C 60 #define HSI2C_TIMING_FS1 0x60 61 #define HSI2C_TIMING_FS2 0x64 62 #define HSI2C_TIMING_FS3 0x68 63 #define HSI2C_TIMING_SLA 0x6C 64 #define HSI2C_ADDR 0x70 65 66 /* I2C_CTL Register bits */ 67 #define HSI2C_FUNC_MODE_I2C (1u << 0) 68 #define HSI2C_MASTER (1u << 3) 69 #define HSI2C_RXCHON (1u << 6) 70 #define HSI2C_TXCHON (1u << 7) 71 #define HSI2C_SW_RST (1u << 31) 72 73 /* I2C_FIFO_CTL Register bits */ 74 #define HSI2C_RXFIFO_EN (1u << 0) 75 #define HSI2C_TXFIFO_EN (1u << 1) 76 #define HSI2C_RXFIFO_TRIGGER_LEVEL(x) ((x) << 4) 77 #define HSI2C_TXFIFO_TRIGGER_LEVEL(x) ((x) << 16) 78 79 /* I2C_TRAILING_CTL Register bits */ 80 #define HSI2C_TRAILING_COUNT (0xf) 81 82 /* I2C_INT_EN Register bits */ 83 #define HSI2C_INT_TX_ALMOSTEMPTY_EN (1u << 0) 84 #define HSI2C_INT_RX_ALMOSTFULL_EN (1u << 1) 85 #define HSI2C_INT_TRAILING_EN (1u << 6) 86 87 /* I2C_INT_STAT Register bits */ 88 #define HSI2C_INT_TX_ALMOSTEMPTY (1u << 0) 89 #define HSI2C_INT_RX_ALMOSTFULL (1u << 1) 90 #define HSI2C_INT_TX_UNDERRUN (1u << 2) 91 #define HSI2C_INT_TX_OVERRUN (1u << 3) 92 #define HSI2C_INT_RX_UNDERRUN (1u << 4) 93 #define HSI2C_INT_RX_OVERRUN (1u << 5) 94 #define HSI2C_INT_TRAILING (1u << 6) 95 #define HSI2C_INT_I2C (1u << 9) 96 97 #define HSI2C_INT_TRANS_DONE (1u << 7) 98 #define HSI2C_INT_TRANS_ABORT (1u << 8) 99 #define HSI2C_INT_NO_DEV_ACK (1u << 9) 100 #define HSI2C_INT_NO_DEV (1u << 10) 101 #define HSI2C_INT_TIMEOUT (1u << 11) 102 #define HSI2C_INT_I2C_TRANS (HSI2C_INT_TRANS_DONE | \ 103 HSI2C_INT_TRANS_ABORT | \ 104 HSI2C_INT_NO_DEV_ACK | \ 105 HSI2C_INT_NO_DEV | \ 106 HSI2C_INT_TIMEOUT) 107 108 /* I2C_FIFO_STAT Register bits */ 109 #define HSI2C_RX_FIFO_EMPTY (1u << 24) 110 #define HSI2C_RX_FIFO_FULL (1u << 23) 111 #define HSI2C_RX_FIFO_LVL(x) ((x >> 16) & 0x7f) 112 #define HSI2C_TX_FIFO_EMPTY (1u << 8) 113 #define HSI2C_TX_FIFO_FULL (1u << 7) 114 #define HSI2C_TX_FIFO_LVL(x) ((x >> 0) & 0x7f) 115 116 /* I2C_CONF Register bits */ 117 #define HSI2C_AUTO_MODE (1u << 31) 118 #define HSI2C_10BIT_ADDR_MODE (1u << 30) 119 #define HSI2C_HS_MODE (1u << 29) 120 121 /* I2C_AUTO_CONF Register bits */ 122 #define HSI2C_READ_WRITE (1u << 16) 123 #define HSI2C_STOP_AFTER_TRANS (1u << 17) 124 #define HSI2C_MASTER_RUN (1u << 31) 125 126 /* I2C_TIMEOUT Register bits */ 127 #define HSI2C_TIMEOUT_EN (1u << 31) 128 #define HSI2C_TIMEOUT_MASK 0xff 129 130 /* I2C_TRANS_STATUS register bits */ 131 #define HSI2C_MASTER_BUSY (1u << 17) 132 #define HSI2C_SLAVE_BUSY (1u << 16) 133 134 /* I2C_TRANS_STATUS register bits for Exynos5 variant */ 135 #define HSI2C_TIMEOUT_AUTO (1u << 4) 136 #define HSI2C_NO_DEV (1u << 3) 137 #define HSI2C_NO_DEV_ACK (1u << 2) 138 #define HSI2C_TRANS_ABORT (1u << 1) 139 #define HSI2C_TRANS_DONE (1u << 0) 140 141 /* I2C_TRANS_STATUS register bits for Exynos7 variant */ 142 #define HSI2C_MASTER_ST_MASK 0xf 143 #define HSI2C_MASTER_ST_IDLE 0x0 144 #define HSI2C_MASTER_ST_START 0x1 145 #define HSI2C_MASTER_ST_RESTART 0x2 146 #define HSI2C_MASTER_ST_STOP 0x3 147 #define HSI2C_MASTER_ST_MASTER_ID 0x4 148 #define HSI2C_MASTER_ST_ADDR0 0x5 149 #define HSI2C_MASTER_ST_ADDR1 0x6 150 #define HSI2C_MASTER_ST_ADDR2 0x7 151 #define HSI2C_MASTER_ST_ADDR_SR 0x8 152 #define HSI2C_MASTER_ST_READ 0x9 153 #define HSI2C_MASTER_ST_WRITE 0xa 154 #define HSI2C_MASTER_ST_NO_ACK 0xb 155 #define HSI2C_MASTER_ST_LOSE 0xc 156 #define HSI2C_MASTER_ST_WAIT 0xd 157 #define HSI2C_MASTER_ST_WAIT_CMD 0xe 158 159 /* I2C_ADDR register bits */ 160 #define HSI2C_SLV_ADDR_SLV(x) ((x & 0x3ff) << 0) 161 #define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10) 162 #define HSI2C_MASTER_ID(x) ((x & 0xff) << 24) 163 #define MASTER_ID(x) ((x & 0x7) + 0x08) 164 165 /* 166 * Controller operating frequency, timing values for operation 167 * are calculated against this frequency 168 */ 169 #define HSI2C_HS_TX_CLOCK 1000000 170 #define HSI2C_FS_TX_CLOCK 100000 171 #define HSI2C_HIGH_SPD 1 172 #define HSI2C_FAST_SPD 0 173 174 #define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(1000)) 175 176 #define HSI2C_EXYNOS7 BIT(0) 177 178 struct exynos5_i2c { 179 struct i2c_adapter adap; 180 unsigned int suspended:1; 181 182 struct i2c_msg *msg; 183 struct completion msg_complete; 184 unsigned int msg_ptr; 185 186 unsigned int irq; 187 188 void __iomem *regs; 189 struct clk *clk; 190 struct device *dev; 191 int state; 192 193 spinlock_t lock; /* IRQ synchronization */ 194 195 /* 196 * Since the TRANS_DONE bit is cleared on read, and we may read it 197 * either during an IRQ or after a transaction, keep track of its 198 * state here. 199 */ 200 int trans_done; 201 202 /* Controller operating frequency */ 203 unsigned int fs_clock; 204 unsigned int hs_clock; 205 206 /* 207 * HSI2C Controller can operate in 208 * 1. High speed upto 3.4Mbps 209 * 2. Fast speed upto 1Mbps 210 */ 211 int speed_mode; 212 213 /* Version of HS-I2C Hardware */ 214 struct exynos_hsi2c_variant *variant; 215 }; 216 217 /** 218 * struct exynos_hsi2c_variant - platform specific HSI2C driver data 219 * @fifo_depth: the fifo depth supported by the HSI2C module 220 * 221 * Specifies platform specific configuration of HSI2C module. 222 * Note: A structure for driver specific platform data is used for future 223 * expansion of its usage. 224 */ 225 struct exynos_hsi2c_variant { 226 unsigned int fifo_depth; 227 unsigned int hw; 228 }; 229 230 static const struct exynos_hsi2c_variant exynos5250_hsi2c_data = { 231 .fifo_depth = 64, 232 }; 233 234 static const struct exynos_hsi2c_variant exynos5260_hsi2c_data = { 235 .fifo_depth = 16, 236 }; 237 238 static const struct exynos_hsi2c_variant exynos7_hsi2c_data = { 239 .fifo_depth = 16, 240 .hw = HSI2C_EXYNOS7, 241 }; 242 243 static const struct of_device_id exynos5_i2c_match[] = { 244 { 245 .compatible = "samsung,exynos5-hsi2c", 246 .data = &exynos5250_hsi2c_data 247 }, { 248 .compatible = "samsung,exynos5250-hsi2c", 249 .data = &exynos5250_hsi2c_data 250 }, { 251 .compatible = "samsung,exynos5260-hsi2c", 252 .data = &exynos5260_hsi2c_data 253 }, { 254 .compatible = "samsung,exynos7-hsi2c", 255 .data = &exynos7_hsi2c_data 256 }, {}, 257 }; 258 MODULE_DEVICE_TABLE(of, exynos5_i2c_match); 259 260 static inline struct exynos_hsi2c_variant *exynos5_i2c_get_variant 261 (struct platform_device *pdev) 262 { 263 const struct of_device_id *match; 264 265 match = of_match_node(exynos5_i2c_match, pdev->dev.of_node); 266 return (struct exynos_hsi2c_variant *)match->data; 267 } 268 269 static void exynos5_i2c_clr_pend_irq(struct exynos5_i2c *i2c) 270 { 271 writel(readl(i2c->regs + HSI2C_INT_STATUS), 272 i2c->regs + HSI2C_INT_STATUS); 273 } 274 275 /* 276 * exynos5_i2c_set_timing: updates the registers with appropriate 277 * timing values calculated 278 * 279 * Returns 0 on success, -EINVAL if the cycle length cannot 280 * be calculated. 281 */ 282 static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, int mode) 283 { 284 u32 i2c_timing_s1; 285 u32 i2c_timing_s2; 286 u32 i2c_timing_s3; 287 u32 i2c_timing_sla; 288 unsigned int t_start_su, t_start_hd; 289 unsigned int t_stop_su; 290 unsigned int t_data_su, t_data_hd; 291 unsigned int t_scl_l, t_scl_h; 292 unsigned int t_sr_release; 293 unsigned int t_ftl_cycle; 294 unsigned int clkin = clk_get_rate(i2c->clk); 295 unsigned int div, utemp0 = 0, utemp1 = 0, clk_cycle; 296 unsigned int op_clk = (mode == HSI2C_HIGH_SPD) ? 297 i2c->hs_clock : i2c->fs_clock; 298 299 /* 300 * In case of HSI2C controller in Exynos5 series 301 * FPCLK / FI2C = 302 * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE 303 * 304 * In case of HSI2C controllers in Exynos7 series 305 * FPCLK / FI2C = 306 * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + FLT_CYCLE 307 * 308 * utemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) 309 * utemp1 = (TSCLK_L + TSCLK_H + 2) 310 */ 311 t_ftl_cycle = (readl(i2c->regs + HSI2C_CONF) >> 16) & 0x7; 312 utemp0 = (clkin / op_clk) - 8; 313 314 if (i2c->variant->hw == HSI2C_EXYNOS7) 315 utemp0 -= t_ftl_cycle; 316 else 317 utemp0 -= 2 * t_ftl_cycle; 318 319 /* CLK_DIV max is 256 */ 320 for (div = 0; div < 256; div++) { 321 utemp1 = utemp0 / (div + 1); 322 323 /* 324 * SCL_L and SCL_H each has max value of 255 325 * Hence, For the clk_cycle to the have right value 326 * utemp1 has to be less then 512 and more than 4. 327 */ 328 if ((utemp1 < 512) && (utemp1 > 4)) { 329 clk_cycle = utemp1 - 2; 330 break; 331 } else if (div == 255) { 332 dev_warn(i2c->dev, "Failed to calculate divisor"); 333 return -EINVAL; 334 } 335 } 336 337 t_scl_l = clk_cycle / 2; 338 t_scl_h = clk_cycle / 2; 339 t_start_su = t_scl_l; 340 t_start_hd = t_scl_l; 341 t_stop_su = t_scl_l; 342 t_data_su = t_scl_l / 2; 343 t_data_hd = t_scl_l / 2; 344 t_sr_release = clk_cycle; 345 346 i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8; 347 i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0; 348 i2c_timing_s3 = div << 16 | t_sr_release << 0; 349 i2c_timing_sla = t_data_hd << 0; 350 351 dev_dbg(i2c->dev, "tSTART_SU: %X, tSTART_HD: %X, tSTOP_SU: %X\n", 352 t_start_su, t_start_hd, t_stop_su); 353 dev_dbg(i2c->dev, "tDATA_SU: %X, tSCL_L: %X, tSCL_H: %X\n", 354 t_data_su, t_scl_l, t_scl_h); 355 dev_dbg(i2c->dev, "nClkDiv: %X, tSR_RELEASE: %X\n", 356 div, t_sr_release); 357 dev_dbg(i2c->dev, "tDATA_HD: %X\n", t_data_hd); 358 359 if (mode == HSI2C_HIGH_SPD) { 360 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_HS1); 361 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_HS2); 362 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3); 363 } else { 364 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_FS1); 365 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_FS2); 366 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3); 367 } 368 writel(i2c_timing_sla, i2c->regs + HSI2C_TIMING_SLA); 369 370 return 0; 371 } 372 373 static int exynos5_hsi2c_clock_setup(struct exynos5_i2c *i2c) 374 { 375 /* 376 * Configure the Fast speed timing values 377 * Even the High Speed mode initially starts with Fast mode 378 */ 379 if (exynos5_i2c_set_timing(i2c, HSI2C_FAST_SPD)) { 380 dev_err(i2c->dev, "HSI2C FS Clock set up failed\n"); 381 return -EINVAL; 382 } 383 384 /* configure the High speed timing values */ 385 if (i2c->speed_mode == HSI2C_HIGH_SPD) { 386 if (exynos5_i2c_set_timing(i2c, HSI2C_HIGH_SPD)) { 387 dev_err(i2c->dev, "HSI2C HS Clock set up failed\n"); 388 return -EINVAL; 389 } 390 } 391 392 return 0; 393 } 394 395 /* 396 * exynos5_i2c_init: configures the controller for I2C functionality 397 * Programs I2C controller for Master mode operation 398 */ 399 static void exynos5_i2c_init(struct exynos5_i2c *i2c) 400 { 401 u32 i2c_conf = readl(i2c->regs + HSI2C_CONF); 402 u32 i2c_timeout = readl(i2c->regs + HSI2C_TIMEOUT); 403 404 /* Clear to disable Timeout */ 405 i2c_timeout &= ~HSI2C_TIMEOUT_EN; 406 writel(i2c_timeout, i2c->regs + HSI2C_TIMEOUT); 407 408 writel((HSI2C_FUNC_MODE_I2C | HSI2C_MASTER), 409 i2c->regs + HSI2C_CTL); 410 writel(HSI2C_TRAILING_COUNT, i2c->regs + HSI2C_TRAILIG_CTL); 411 412 if (i2c->speed_mode == HSI2C_HIGH_SPD) { 413 writel(HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr)), 414 i2c->regs + HSI2C_ADDR); 415 i2c_conf |= HSI2C_HS_MODE; 416 } 417 418 writel(i2c_conf | HSI2C_AUTO_MODE, i2c->regs + HSI2C_CONF); 419 } 420 421 static void exynos5_i2c_reset(struct exynos5_i2c *i2c) 422 { 423 u32 i2c_ctl; 424 425 /* Set and clear the bit for reset */ 426 i2c_ctl = readl(i2c->regs + HSI2C_CTL); 427 i2c_ctl |= HSI2C_SW_RST; 428 writel(i2c_ctl, i2c->regs + HSI2C_CTL); 429 430 i2c_ctl = readl(i2c->regs + HSI2C_CTL); 431 i2c_ctl &= ~HSI2C_SW_RST; 432 writel(i2c_ctl, i2c->regs + HSI2C_CTL); 433 434 /* We don't expect calculations to fail during the run */ 435 exynos5_hsi2c_clock_setup(i2c); 436 /* Initialize the configure registers */ 437 exynos5_i2c_init(i2c); 438 } 439 440 /* 441 * exynos5_i2c_irq: top level IRQ servicing routine 442 * 443 * INT_STATUS registers gives the interrupt details. Further, 444 * FIFO_STATUS or TRANS_STATUS registers are to be check for detailed 445 * state of the bus. 446 */ 447 static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id) 448 { 449 struct exynos5_i2c *i2c = dev_id; 450 u32 fifo_level, int_status, fifo_status, trans_status; 451 unsigned char byte; 452 int len = 0; 453 454 i2c->state = -EINVAL; 455 456 spin_lock(&i2c->lock); 457 458 int_status = readl(i2c->regs + HSI2C_INT_STATUS); 459 writel(int_status, i2c->regs + HSI2C_INT_STATUS); 460 461 /* handle interrupt related to the transfer status */ 462 if (i2c->variant->hw == HSI2C_EXYNOS7) { 463 if (int_status & HSI2C_INT_TRANS_DONE) { 464 i2c->trans_done = 1; 465 i2c->state = 0; 466 } else if (int_status & HSI2C_INT_TRANS_ABORT) { 467 dev_dbg(i2c->dev, "Deal with arbitration lose\n"); 468 i2c->state = -EAGAIN; 469 goto stop; 470 } else if (int_status & HSI2C_INT_NO_DEV_ACK) { 471 dev_dbg(i2c->dev, "No ACK from device\n"); 472 i2c->state = -ENXIO; 473 goto stop; 474 } else if (int_status & HSI2C_INT_NO_DEV) { 475 dev_dbg(i2c->dev, "No device\n"); 476 i2c->state = -ENXIO; 477 goto stop; 478 } else if (int_status & HSI2C_INT_TIMEOUT) { 479 dev_dbg(i2c->dev, "Accessing device timed out\n"); 480 i2c->state = -ETIMEDOUT; 481 goto stop; 482 } 483 484 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS); 485 if ((trans_status & HSI2C_MASTER_ST_MASK) == HSI2C_MASTER_ST_LOSE) { 486 i2c->state = -EAGAIN; 487 goto stop; 488 } 489 } else if (int_status & HSI2C_INT_I2C) { 490 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS); 491 if (trans_status & HSI2C_NO_DEV_ACK) { 492 dev_dbg(i2c->dev, "No ACK from device\n"); 493 i2c->state = -ENXIO; 494 goto stop; 495 } else if (trans_status & HSI2C_NO_DEV) { 496 dev_dbg(i2c->dev, "No device\n"); 497 i2c->state = -ENXIO; 498 goto stop; 499 } else if (trans_status & HSI2C_TRANS_ABORT) { 500 dev_dbg(i2c->dev, "Deal with arbitration lose\n"); 501 i2c->state = -EAGAIN; 502 goto stop; 503 } else if (trans_status & HSI2C_TIMEOUT_AUTO) { 504 dev_dbg(i2c->dev, "Accessing device timed out\n"); 505 i2c->state = -ETIMEDOUT; 506 goto stop; 507 } else if (trans_status & HSI2C_TRANS_DONE) { 508 i2c->trans_done = 1; 509 i2c->state = 0; 510 } 511 } 512 513 if ((i2c->msg->flags & I2C_M_RD) && (int_status & 514 (HSI2C_INT_TRAILING | HSI2C_INT_RX_ALMOSTFULL))) { 515 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS); 516 fifo_level = HSI2C_RX_FIFO_LVL(fifo_status); 517 len = min(fifo_level, i2c->msg->len - i2c->msg_ptr); 518 519 while (len > 0) { 520 byte = (unsigned char) 521 readl(i2c->regs + HSI2C_RX_DATA); 522 i2c->msg->buf[i2c->msg_ptr++] = byte; 523 len--; 524 } 525 i2c->state = 0; 526 } else if (int_status & HSI2C_INT_TX_ALMOSTEMPTY) { 527 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS); 528 fifo_level = HSI2C_TX_FIFO_LVL(fifo_status); 529 530 len = i2c->variant->fifo_depth - fifo_level; 531 if (len > (i2c->msg->len - i2c->msg_ptr)) { 532 u32 int_en = readl(i2c->regs + HSI2C_INT_ENABLE); 533 534 int_en &= ~HSI2C_INT_TX_ALMOSTEMPTY_EN; 535 writel(int_en, i2c->regs + HSI2C_INT_ENABLE); 536 len = i2c->msg->len - i2c->msg_ptr; 537 } 538 539 while (len > 0) { 540 byte = i2c->msg->buf[i2c->msg_ptr++]; 541 writel(byte, i2c->regs + HSI2C_TX_DATA); 542 len--; 543 } 544 i2c->state = 0; 545 } 546 547 stop: 548 if ((i2c->trans_done && (i2c->msg->len == i2c->msg_ptr)) || 549 (i2c->state < 0)) { 550 writel(0, i2c->regs + HSI2C_INT_ENABLE); 551 exynos5_i2c_clr_pend_irq(i2c); 552 complete(&i2c->msg_complete); 553 } 554 555 spin_unlock(&i2c->lock); 556 557 return IRQ_HANDLED; 558 } 559 560 /* 561 * exynos5_i2c_wait_bus_idle 562 * 563 * Wait for the bus to go idle, indicated by the MASTER_BUSY bit being 564 * cleared. 565 * 566 * Returns -EBUSY if the bus cannot be bought to idle 567 */ 568 static int exynos5_i2c_wait_bus_idle(struct exynos5_i2c *i2c) 569 { 570 unsigned long stop_time; 571 u32 trans_status; 572 573 /* wait for 100 milli seconds for the bus to be idle */ 574 stop_time = jiffies + msecs_to_jiffies(100) + 1; 575 do { 576 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS); 577 if (!(trans_status & HSI2C_MASTER_BUSY)) 578 return 0; 579 580 usleep_range(50, 200); 581 } while (time_before(jiffies, stop_time)); 582 583 return -EBUSY; 584 } 585 586 /* 587 * exynos5_i2c_message_start: Configures the bus and starts the xfer 588 * i2c: struct exynos5_i2c pointer for the current bus 589 * stop: Enables stop after transfer if set. Set for last transfer of 590 * in the list of messages. 591 * 592 * Configures the bus for read/write function 593 * Sets chip address to talk to, message length to be sent. 594 * Enables appropriate interrupts and sends start xfer command. 595 */ 596 static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop) 597 { 598 u32 i2c_ctl; 599 u32 int_en = 0; 600 u32 i2c_auto_conf = 0; 601 u32 fifo_ctl; 602 unsigned long flags; 603 unsigned short trig_lvl; 604 605 if (i2c->variant->hw == HSI2C_EXYNOS7) 606 int_en |= HSI2C_INT_I2C_TRANS; 607 else 608 int_en |= HSI2C_INT_I2C; 609 610 i2c_ctl = readl(i2c->regs + HSI2C_CTL); 611 i2c_ctl &= ~(HSI2C_TXCHON | HSI2C_RXCHON); 612 fifo_ctl = HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN; 613 614 if (i2c->msg->flags & I2C_M_RD) { 615 i2c_ctl |= HSI2C_RXCHON; 616 617 i2c_auto_conf |= HSI2C_READ_WRITE; 618 619 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ? 620 (i2c->variant->fifo_depth * 3 / 4) : i2c->msg->len; 621 fifo_ctl |= HSI2C_RXFIFO_TRIGGER_LEVEL(trig_lvl); 622 623 int_en |= (HSI2C_INT_RX_ALMOSTFULL_EN | 624 HSI2C_INT_TRAILING_EN); 625 } else { 626 i2c_ctl |= HSI2C_TXCHON; 627 628 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ? 629 (i2c->variant->fifo_depth * 1 / 4) : i2c->msg->len; 630 fifo_ctl |= HSI2C_TXFIFO_TRIGGER_LEVEL(trig_lvl); 631 632 int_en |= HSI2C_INT_TX_ALMOSTEMPTY_EN; 633 } 634 635 writel(HSI2C_SLV_ADDR_MAS(i2c->msg->addr), i2c->regs + HSI2C_ADDR); 636 637 writel(fifo_ctl, i2c->regs + HSI2C_FIFO_CTL); 638 writel(i2c_ctl, i2c->regs + HSI2C_CTL); 639 640 /* 641 * Enable interrupts before starting the transfer so that we don't 642 * miss any INT_I2C interrupts. 643 */ 644 spin_lock_irqsave(&i2c->lock, flags); 645 writel(int_en, i2c->regs + HSI2C_INT_ENABLE); 646 647 if (stop == 1) 648 i2c_auto_conf |= HSI2C_STOP_AFTER_TRANS; 649 i2c_auto_conf |= i2c->msg->len; 650 i2c_auto_conf |= HSI2C_MASTER_RUN; 651 writel(i2c_auto_conf, i2c->regs + HSI2C_AUTO_CONF); 652 spin_unlock_irqrestore(&i2c->lock, flags); 653 } 654 655 static int exynos5_i2c_xfer_msg(struct exynos5_i2c *i2c, 656 struct i2c_msg *msgs, int stop) 657 { 658 unsigned long timeout; 659 int ret; 660 661 i2c->msg = msgs; 662 i2c->msg_ptr = 0; 663 i2c->trans_done = 0; 664 665 reinit_completion(&i2c->msg_complete); 666 667 exynos5_i2c_message_start(i2c, stop); 668 669 timeout = wait_for_completion_timeout(&i2c->msg_complete, 670 EXYNOS5_I2C_TIMEOUT); 671 if (timeout == 0) 672 ret = -ETIMEDOUT; 673 else 674 ret = i2c->state; 675 676 /* 677 * If this is the last message to be transfered (stop == 1) 678 * Then check if the bus can be brought back to idle. 679 */ 680 if (ret == 0 && stop) 681 ret = exynos5_i2c_wait_bus_idle(i2c); 682 683 if (ret < 0) { 684 exynos5_i2c_reset(i2c); 685 if (ret == -ETIMEDOUT) 686 dev_warn(i2c->dev, "%s timeout\n", 687 (msgs->flags & I2C_M_RD) ? "rx" : "tx"); 688 } 689 690 /* Return the state as in interrupt routine */ 691 return ret; 692 } 693 694 static int exynos5_i2c_xfer(struct i2c_adapter *adap, 695 struct i2c_msg *msgs, int num) 696 { 697 struct exynos5_i2c *i2c = adap->algo_data; 698 int i = 0, ret = 0, stop = 0; 699 700 if (i2c->suspended) { 701 dev_err(i2c->dev, "HS-I2C is not initialized.\n"); 702 return -EIO; 703 } 704 705 ret = clk_enable(i2c->clk); 706 if (ret) 707 return ret; 708 709 for (i = 0; i < num; i++, msgs++) { 710 stop = (i == num - 1); 711 712 ret = exynos5_i2c_xfer_msg(i2c, msgs, stop); 713 714 if (ret < 0) 715 goto out; 716 } 717 718 if (i == num) { 719 ret = num; 720 } else { 721 /* Only one message, cannot access the device */ 722 if (i == 1) 723 ret = -EREMOTEIO; 724 else 725 ret = i; 726 727 dev_warn(i2c->dev, "xfer message failed\n"); 728 } 729 730 out: 731 clk_disable(i2c->clk); 732 return ret; 733 } 734 735 static u32 exynos5_i2c_func(struct i2c_adapter *adap) 736 { 737 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 738 } 739 740 static const struct i2c_algorithm exynos5_i2c_algorithm = { 741 .master_xfer = exynos5_i2c_xfer, 742 .functionality = exynos5_i2c_func, 743 }; 744 745 static int exynos5_i2c_probe(struct platform_device *pdev) 746 { 747 struct device_node *np = pdev->dev.of_node; 748 struct exynos5_i2c *i2c; 749 struct resource *mem; 750 unsigned int op_clock; 751 int ret; 752 753 i2c = devm_kzalloc(&pdev->dev, sizeof(struct exynos5_i2c), GFP_KERNEL); 754 if (!i2c) 755 return -ENOMEM; 756 757 if (of_property_read_u32(np, "clock-frequency", &op_clock)) { 758 i2c->speed_mode = HSI2C_FAST_SPD; 759 i2c->fs_clock = HSI2C_FS_TX_CLOCK; 760 } else { 761 if (op_clock >= HSI2C_HS_TX_CLOCK) { 762 i2c->speed_mode = HSI2C_HIGH_SPD; 763 i2c->fs_clock = HSI2C_FS_TX_CLOCK; 764 i2c->hs_clock = op_clock; 765 } else { 766 i2c->speed_mode = HSI2C_FAST_SPD; 767 i2c->fs_clock = op_clock; 768 } 769 } 770 771 strlcpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name)); 772 i2c->adap.owner = THIS_MODULE; 773 i2c->adap.algo = &exynos5_i2c_algorithm; 774 i2c->adap.retries = 3; 775 776 i2c->dev = &pdev->dev; 777 i2c->clk = devm_clk_get(&pdev->dev, "hsi2c"); 778 if (IS_ERR(i2c->clk)) { 779 dev_err(&pdev->dev, "cannot get clock\n"); 780 return -ENOENT; 781 } 782 783 ret = clk_prepare_enable(i2c->clk); 784 if (ret) 785 return ret; 786 787 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 788 i2c->regs = devm_ioremap_resource(&pdev->dev, mem); 789 if (IS_ERR(i2c->regs)) { 790 ret = PTR_ERR(i2c->regs); 791 goto err_clk; 792 } 793 794 i2c->adap.dev.of_node = np; 795 i2c->adap.algo_data = i2c; 796 i2c->adap.dev.parent = &pdev->dev; 797 798 /* Clear pending interrupts from u-boot or misc causes */ 799 exynos5_i2c_clr_pend_irq(i2c); 800 801 spin_lock_init(&i2c->lock); 802 init_completion(&i2c->msg_complete); 803 804 i2c->irq = ret = platform_get_irq(pdev, 0); 805 if (ret <= 0) { 806 dev_err(&pdev->dev, "cannot find HS-I2C IRQ\n"); 807 ret = -EINVAL; 808 goto err_clk; 809 } 810 811 ret = devm_request_irq(&pdev->dev, i2c->irq, exynos5_i2c_irq, 812 IRQF_NO_SUSPEND | IRQF_ONESHOT, 813 dev_name(&pdev->dev), i2c); 814 815 if (ret != 0) { 816 dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n", i2c->irq); 817 goto err_clk; 818 } 819 820 /* Need to check the variant before setting up. */ 821 i2c->variant = exynos5_i2c_get_variant(pdev); 822 823 ret = exynos5_hsi2c_clock_setup(i2c); 824 if (ret) 825 goto err_clk; 826 827 exynos5_i2c_reset(i2c); 828 829 ret = i2c_add_adapter(&i2c->adap); 830 if (ret < 0) 831 goto err_clk; 832 833 platform_set_drvdata(pdev, i2c); 834 835 clk_disable(i2c->clk); 836 837 return 0; 838 839 err_clk: 840 clk_disable_unprepare(i2c->clk); 841 return ret; 842 } 843 844 static int exynos5_i2c_remove(struct platform_device *pdev) 845 { 846 struct exynos5_i2c *i2c = platform_get_drvdata(pdev); 847 848 i2c_del_adapter(&i2c->adap); 849 850 clk_unprepare(i2c->clk); 851 852 return 0; 853 } 854 855 #ifdef CONFIG_PM_SLEEP 856 static int exynos5_i2c_suspend_noirq(struct device *dev) 857 { 858 struct platform_device *pdev = to_platform_device(dev); 859 struct exynos5_i2c *i2c = platform_get_drvdata(pdev); 860 861 i2c->suspended = 1; 862 863 clk_unprepare(i2c->clk); 864 865 return 0; 866 } 867 868 static int exynos5_i2c_resume_noirq(struct device *dev) 869 { 870 struct platform_device *pdev = to_platform_device(dev); 871 struct exynos5_i2c *i2c = platform_get_drvdata(pdev); 872 int ret = 0; 873 874 ret = clk_prepare_enable(i2c->clk); 875 if (ret) 876 return ret; 877 878 ret = exynos5_hsi2c_clock_setup(i2c); 879 if (ret) { 880 clk_disable_unprepare(i2c->clk); 881 return ret; 882 } 883 884 exynos5_i2c_init(i2c); 885 clk_disable(i2c->clk); 886 i2c->suspended = 0; 887 888 return 0; 889 } 890 #endif 891 892 static const struct dev_pm_ops exynos5_i2c_dev_pm_ops = { 893 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(exynos5_i2c_suspend_noirq, 894 exynos5_i2c_resume_noirq) 895 }; 896 897 static struct platform_driver exynos5_i2c_driver = { 898 .probe = exynos5_i2c_probe, 899 .remove = exynos5_i2c_remove, 900 .driver = { 901 .name = "exynos5-hsi2c", 902 .pm = &exynos5_i2c_dev_pm_ops, 903 .of_match_table = exynos5_i2c_match, 904 }, 905 }; 906 907 module_platform_driver(exynos5_i2c_driver); 908 909 MODULE_DESCRIPTION("Exynos5 HS-I2C Bus driver"); 910 MODULE_AUTHOR("Naveen Krishna Chatradhi, <ch.naveen@samsung.com>"); 911 MODULE_AUTHOR("Taekgyun Ko, <taeggyun.ko@samsung.com>"); 912 MODULE_LICENSE("GPL v2"); 913