1 /** 2 * i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver 3 * 4 * Copyright (C) 2013 Samsung Electronics Co., Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 14 #include <linux/i2c.h> 15 #include <linux/time.h> 16 #include <linux/interrupt.h> 17 #include <linux/delay.h> 18 #include <linux/errno.h> 19 #include <linux/err.h> 20 #include <linux/platform_device.h> 21 #include <linux/clk.h> 22 #include <linux/slab.h> 23 #include <linux/io.h> 24 #include <linux/of_address.h> 25 #include <linux/of_device.h> 26 #include <linux/of_irq.h> 27 #include <linux/spinlock.h> 28 29 /* 30 * HSI2C controller from Samsung supports 2 modes of operation 31 * 1. Auto mode: Where in master automatically controls the whole transaction 32 * 2. Manual mode: Software controls the transaction by issuing commands 33 * START, READ, WRITE, STOP, RESTART in I2C_MANUAL_CMD register. 34 * 35 * Operation mode can be selected by setting AUTO_MODE bit in I2C_CONF register 36 * 37 * Special bits are available for both modes of operation to set commands 38 * and for checking transfer status 39 */ 40 41 /* Register Map */ 42 #define HSI2C_CTL 0x00 43 #define HSI2C_FIFO_CTL 0x04 44 #define HSI2C_TRAILIG_CTL 0x08 45 #define HSI2C_CLK_CTL 0x0C 46 #define HSI2C_CLK_SLOT 0x10 47 #define HSI2C_INT_ENABLE 0x20 48 #define HSI2C_INT_STATUS 0x24 49 #define HSI2C_ERR_STATUS 0x2C 50 #define HSI2C_FIFO_STATUS 0x30 51 #define HSI2C_TX_DATA 0x34 52 #define HSI2C_RX_DATA 0x38 53 #define HSI2C_CONF 0x40 54 #define HSI2C_AUTO_CONF 0x44 55 #define HSI2C_TIMEOUT 0x48 56 #define HSI2C_MANUAL_CMD 0x4C 57 #define HSI2C_TRANS_STATUS 0x50 58 #define HSI2C_TIMING_HS1 0x54 59 #define HSI2C_TIMING_HS2 0x58 60 #define HSI2C_TIMING_HS3 0x5C 61 #define HSI2C_TIMING_FS1 0x60 62 #define HSI2C_TIMING_FS2 0x64 63 #define HSI2C_TIMING_FS3 0x68 64 #define HSI2C_TIMING_SLA 0x6C 65 #define HSI2C_ADDR 0x70 66 67 /* I2C_CTL Register bits */ 68 #define HSI2C_FUNC_MODE_I2C (1u << 0) 69 #define HSI2C_MASTER (1u << 3) 70 #define HSI2C_RXCHON (1u << 6) 71 #define HSI2C_TXCHON (1u << 7) 72 #define HSI2C_SW_RST (1u << 31) 73 74 /* I2C_FIFO_CTL Register bits */ 75 #define HSI2C_RXFIFO_EN (1u << 0) 76 #define HSI2C_TXFIFO_EN (1u << 1) 77 #define HSI2C_RXFIFO_TRIGGER_LEVEL(x) ((x) << 4) 78 #define HSI2C_TXFIFO_TRIGGER_LEVEL(x) ((x) << 16) 79 80 /* I2C_TRAILING_CTL Register bits */ 81 #define HSI2C_TRAILING_COUNT (0xf) 82 83 /* I2C_INT_EN Register bits */ 84 #define HSI2C_INT_TX_ALMOSTEMPTY_EN (1u << 0) 85 #define HSI2C_INT_RX_ALMOSTFULL_EN (1u << 1) 86 #define HSI2C_INT_TRAILING_EN (1u << 6) 87 88 /* I2C_INT_STAT Register bits */ 89 #define HSI2C_INT_TX_ALMOSTEMPTY (1u << 0) 90 #define HSI2C_INT_RX_ALMOSTFULL (1u << 1) 91 #define HSI2C_INT_TX_UNDERRUN (1u << 2) 92 #define HSI2C_INT_TX_OVERRUN (1u << 3) 93 #define HSI2C_INT_RX_UNDERRUN (1u << 4) 94 #define HSI2C_INT_RX_OVERRUN (1u << 5) 95 #define HSI2C_INT_TRAILING (1u << 6) 96 #define HSI2C_INT_I2C (1u << 9) 97 98 #define HSI2C_INT_TRANS_DONE (1u << 7) 99 #define HSI2C_INT_TRANS_ABORT (1u << 8) 100 #define HSI2C_INT_NO_DEV_ACK (1u << 9) 101 #define HSI2C_INT_NO_DEV (1u << 10) 102 #define HSI2C_INT_TIMEOUT (1u << 11) 103 #define HSI2C_INT_I2C_TRANS (HSI2C_INT_TRANS_DONE | \ 104 HSI2C_INT_TRANS_ABORT | \ 105 HSI2C_INT_NO_DEV_ACK | \ 106 HSI2C_INT_NO_DEV | \ 107 HSI2C_INT_TIMEOUT) 108 109 /* I2C_FIFO_STAT Register bits */ 110 #define HSI2C_RX_FIFO_EMPTY (1u << 24) 111 #define HSI2C_RX_FIFO_FULL (1u << 23) 112 #define HSI2C_RX_FIFO_LVL(x) ((x >> 16) & 0x7f) 113 #define HSI2C_TX_FIFO_EMPTY (1u << 8) 114 #define HSI2C_TX_FIFO_FULL (1u << 7) 115 #define HSI2C_TX_FIFO_LVL(x) ((x >> 0) & 0x7f) 116 117 /* I2C_CONF Register bits */ 118 #define HSI2C_AUTO_MODE (1u << 31) 119 #define HSI2C_10BIT_ADDR_MODE (1u << 30) 120 #define HSI2C_HS_MODE (1u << 29) 121 122 /* I2C_AUTO_CONF Register bits */ 123 #define HSI2C_READ_WRITE (1u << 16) 124 #define HSI2C_STOP_AFTER_TRANS (1u << 17) 125 #define HSI2C_MASTER_RUN (1u << 31) 126 127 /* I2C_TIMEOUT Register bits */ 128 #define HSI2C_TIMEOUT_EN (1u << 31) 129 #define HSI2C_TIMEOUT_MASK 0xff 130 131 /* I2C_MANUAL_CMD register bits */ 132 #define HSI2C_CMD_READ_DATA (1u << 4) 133 #define HSI2C_CMD_SEND_STOP (1u << 2) 134 135 /* I2C_TRANS_STATUS register bits */ 136 #define HSI2C_MASTER_BUSY (1u << 17) 137 #define HSI2C_SLAVE_BUSY (1u << 16) 138 139 /* I2C_TRANS_STATUS register bits for Exynos5 variant */ 140 #define HSI2C_TIMEOUT_AUTO (1u << 4) 141 #define HSI2C_NO_DEV (1u << 3) 142 #define HSI2C_NO_DEV_ACK (1u << 2) 143 #define HSI2C_TRANS_ABORT (1u << 1) 144 #define HSI2C_TRANS_DONE (1u << 0) 145 146 /* I2C_TRANS_STATUS register bits for Exynos7 variant */ 147 #define HSI2C_MASTER_ST_MASK 0xf 148 #define HSI2C_MASTER_ST_IDLE 0x0 149 #define HSI2C_MASTER_ST_START 0x1 150 #define HSI2C_MASTER_ST_RESTART 0x2 151 #define HSI2C_MASTER_ST_STOP 0x3 152 #define HSI2C_MASTER_ST_MASTER_ID 0x4 153 #define HSI2C_MASTER_ST_ADDR0 0x5 154 #define HSI2C_MASTER_ST_ADDR1 0x6 155 #define HSI2C_MASTER_ST_ADDR2 0x7 156 #define HSI2C_MASTER_ST_ADDR_SR 0x8 157 #define HSI2C_MASTER_ST_READ 0x9 158 #define HSI2C_MASTER_ST_WRITE 0xa 159 #define HSI2C_MASTER_ST_NO_ACK 0xb 160 #define HSI2C_MASTER_ST_LOSE 0xc 161 #define HSI2C_MASTER_ST_WAIT 0xd 162 #define HSI2C_MASTER_ST_WAIT_CMD 0xe 163 164 /* I2C_ADDR register bits */ 165 #define HSI2C_SLV_ADDR_SLV(x) ((x & 0x3ff) << 0) 166 #define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10) 167 #define HSI2C_MASTER_ID(x) ((x & 0xff) << 24) 168 #define MASTER_ID(x) ((x & 0x7) + 0x08) 169 170 /* 171 * Controller operating frequency, timing values for operation 172 * are calculated against this frequency 173 */ 174 #define HSI2C_HS_TX_CLOCK 1000000 175 #define HSI2C_FS_TX_CLOCK 100000 176 177 #define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(100)) 178 179 enum i2c_type_exynos { 180 I2C_TYPE_EXYNOS5, 181 I2C_TYPE_EXYNOS7, 182 }; 183 184 struct exynos5_i2c { 185 struct i2c_adapter adap; 186 unsigned int suspended:1; 187 188 struct i2c_msg *msg; 189 struct completion msg_complete; 190 unsigned int msg_ptr; 191 192 unsigned int irq; 193 194 void __iomem *regs; 195 struct clk *clk; 196 struct device *dev; 197 int state; 198 199 spinlock_t lock; /* IRQ synchronization */ 200 201 /* 202 * Since the TRANS_DONE bit is cleared on read, and we may read it 203 * either during an IRQ or after a transaction, keep track of its 204 * state here. 205 */ 206 int trans_done; 207 208 /* Controller operating frequency */ 209 unsigned int op_clock; 210 211 /* Version of HS-I2C Hardware */ 212 const struct exynos_hsi2c_variant *variant; 213 }; 214 215 /** 216 * struct exynos_hsi2c_variant - platform specific HSI2C driver data 217 * @fifo_depth: the fifo depth supported by the HSI2C module 218 * @hw: the hardware variant of Exynos I2C controller 219 * 220 * Specifies platform specific configuration of HSI2C module. 221 * Note: A structure for driver specific platform data is used for future 222 * expansion of its usage. 223 */ 224 struct exynos_hsi2c_variant { 225 unsigned int fifo_depth; 226 enum i2c_type_exynos hw; 227 }; 228 229 static const struct exynos_hsi2c_variant exynos5250_hsi2c_data = { 230 .fifo_depth = 64, 231 .hw = I2C_TYPE_EXYNOS5, 232 }; 233 234 static const struct exynos_hsi2c_variant exynos5260_hsi2c_data = { 235 .fifo_depth = 16, 236 .hw = I2C_TYPE_EXYNOS5, 237 }; 238 239 static const struct exynos_hsi2c_variant exynos7_hsi2c_data = { 240 .fifo_depth = 16, 241 .hw = I2C_TYPE_EXYNOS7, 242 }; 243 244 static const struct of_device_id exynos5_i2c_match[] = { 245 { 246 .compatible = "samsung,exynos5-hsi2c", 247 .data = &exynos5250_hsi2c_data 248 }, { 249 .compatible = "samsung,exynos5250-hsi2c", 250 .data = &exynos5250_hsi2c_data 251 }, { 252 .compatible = "samsung,exynos5260-hsi2c", 253 .data = &exynos5260_hsi2c_data 254 }, { 255 .compatible = "samsung,exynos7-hsi2c", 256 .data = &exynos7_hsi2c_data 257 }, {}, 258 }; 259 MODULE_DEVICE_TABLE(of, exynos5_i2c_match); 260 261 static void exynos5_i2c_clr_pend_irq(struct exynos5_i2c *i2c) 262 { 263 writel(readl(i2c->regs + HSI2C_INT_STATUS), 264 i2c->regs + HSI2C_INT_STATUS); 265 } 266 267 /* 268 * exynos5_i2c_set_timing: updates the registers with appropriate 269 * timing values calculated 270 * 271 * Returns 0 on success, -EINVAL if the cycle length cannot 272 * be calculated. 273 */ 274 static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, bool hs_timings) 275 { 276 u32 i2c_timing_s1; 277 u32 i2c_timing_s2; 278 u32 i2c_timing_s3; 279 u32 i2c_timing_sla; 280 unsigned int t_start_su, t_start_hd; 281 unsigned int t_stop_su; 282 unsigned int t_data_su, t_data_hd; 283 unsigned int t_scl_l, t_scl_h; 284 unsigned int t_sr_release; 285 unsigned int t_ftl_cycle; 286 unsigned int clkin = clk_get_rate(i2c->clk); 287 unsigned int op_clk = hs_timings ? i2c->op_clock : 288 (i2c->op_clock >= HSI2C_HS_TX_CLOCK) ? HSI2C_FS_TX_CLOCK : 289 i2c->op_clock; 290 int div, clk_cycle, temp; 291 292 /* 293 * In case of HSI2C controller in Exynos5 series 294 * FPCLK / FI2C = 295 * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE 296 * 297 * In case of HSI2C controllers in Exynos7 series 298 * FPCLK / FI2C = 299 * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + FLT_CYCLE 300 * 301 * clk_cycle := TSCLK_L + TSCLK_H 302 * temp := (CLK_DIV + 1) * (clk_cycle + 2) 303 * 304 * Constraints: 4 <= temp, 0 <= CLK_DIV < 256, 2 <= clk_cycle <= 510 305 * 306 */ 307 t_ftl_cycle = (readl(i2c->regs + HSI2C_CONF) >> 16) & 0x7; 308 temp = clkin / op_clk - 8 - t_ftl_cycle; 309 if (i2c->variant->hw != I2C_TYPE_EXYNOS7) 310 temp -= t_ftl_cycle; 311 div = temp / 512; 312 clk_cycle = temp / (div + 1) - 2; 313 if (temp < 4 || div >= 256 || clk_cycle < 2) { 314 dev_err(i2c->dev, "%s clock set-up failed\n", 315 hs_timings ? "HS" : "FS"); 316 return -EINVAL; 317 } 318 319 t_scl_l = clk_cycle / 2; 320 t_scl_h = clk_cycle / 2; 321 t_start_su = t_scl_l; 322 t_start_hd = t_scl_l; 323 t_stop_su = t_scl_l; 324 t_data_su = t_scl_l / 2; 325 t_data_hd = t_scl_l / 2; 326 t_sr_release = clk_cycle; 327 328 i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8; 329 i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0; 330 i2c_timing_s3 = div << 16 | t_sr_release << 0; 331 i2c_timing_sla = t_data_hd << 0; 332 333 dev_dbg(i2c->dev, "tSTART_SU: %X, tSTART_HD: %X, tSTOP_SU: %X\n", 334 t_start_su, t_start_hd, t_stop_su); 335 dev_dbg(i2c->dev, "tDATA_SU: %X, tSCL_L: %X, tSCL_H: %X\n", 336 t_data_su, t_scl_l, t_scl_h); 337 dev_dbg(i2c->dev, "nClkDiv: %X, tSR_RELEASE: %X\n", 338 div, t_sr_release); 339 dev_dbg(i2c->dev, "tDATA_HD: %X\n", t_data_hd); 340 341 if (hs_timings) { 342 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_HS1); 343 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_HS2); 344 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3); 345 } else { 346 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_FS1); 347 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_FS2); 348 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3); 349 } 350 writel(i2c_timing_sla, i2c->regs + HSI2C_TIMING_SLA); 351 352 return 0; 353 } 354 355 static int exynos5_hsi2c_clock_setup(struct exynos5_i2c *i2c) 356 { 357 /* always set Fast Speed timings */ 358 int ret = exynos5_i2c_set_timing(i2c, false); 359 360 if (ret < 0 || i2c->op_clock < HSI2C_HS_TX_CLOCK) 361 return ret; 362 363 return exynos5_i2c_set_timing(i2c, true); 364 } 365 366 /* 367 * exynos5_i2c_init: configures the controller for I2C functionality 368 * Programs I2C controller for Master mode operation 369 */ 370 static void exynos5_i2c_init(struct exynos5_i2c *i2c) 371 { 372 u32 i2c_conf = readl(i2c->regs + HSI2C_CONF); 373 u32 i2c_timeout = readl(i2c->regs + HSI2C_TIMEOUT); 374 375 /* Clear to disable Timeout */ 376 i2c_timeout &= ~HSI2C_TIMEOUT_EN; 377 writel(i2c_timeout, i2c->regs + HSI2C_TIMEOUT); 378 379 writel((HSI2C_FUNC_MODE_I2C | HSI2C_MASTER), 380 i2c->regs + HSI2C_CTL); 381 writel(HSI2C_TRAILING_COUNT, i2c->regs + HSI2C_TRAILIG_CTL); 382 383 if (i2c->op_clock >= HSI2C_HS_TX_CLOCK) { 384 writel(HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr)), 385 i2c->regs + HSI2C_ADDR); 386 i2c_conf |= HSI2C_HS_MODE; 387 } 388 389 writel(i2c_conf | HSI2C_AUTO_MODE, i2c->regs + HSI2C_CONF); 390 } 391 392 static void exynos5_i2c_reset(struct exynos5_i2c *i2c) 393 { 394 u32 i2c_ctl; 395 396 /* Set and clear the bit for reset */ 397 i2c_ctl = readl(i2c->regs + HSI2C_CTL); 398 i2c_ctl |= HSI2C_SW_RST; 399 writel(i2c_ctl, i2c->regs + HSI2C_CTL); 400 401 i2c_ctl = readl(i2c->regs + HSI2C_CTL); 402 i2c_ctl &= ~HSI2C_SW_RST; 403 writel(i2c_ctl, i2c->regs + HSI2C_CTL); 404 405 /* We don't expect calculations to fail during the run */ 406 exynos5_hsi2c_clock_setup(i2c); 407 /* Initialize the configure registers */ 408 exynos5_i2c_init(i2c); 409 } 410 411 /* 412 * exynos5_i2c_irq: top level IRQ servicing routine 413 * 414 * INT_STATUS registers gives the interrupt details. Further, 415 * FIFO_STATUS or TRANS_STATUS registers are to be check for detailed 416 * state of the bus. 417 */ 418 static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id) 419 { 420 struct exynos5_i2c *i2c = dev_id; 421 u32 fifo_level, int_status, fifo_status, trans_status; 422 unsigned char byte; 423 int len = 0; 424 425 i2c->state = -EINVAL; 426 427 spin_lock(&i2c->lock); 428 429 int_status = readl(i2c->regs + HSI2C_INT_STATUS); 430 writel(int_status, i2c->regs + HSI2C_INT_STATUS); 431 432 /* handle interrupt related to the transfer status */ 433 if (i2c->variant->hw == I2C_TYPE_EXYNOS7) { 434 if (int_status & HSI2C_INT_TRANS_DONE) { 435 i2c->trans_done = 1; 436 i2c->state = 0; 437 } else if (int_status & HSI2C_INT_TRANS_ABORT) { 438 dev_dbg(i2c->dev, "Deal with arbitration lose\n"); 439 i2c->state = -EAGAIN; 440 goto stop; 441 } else if (int_status & HSI2C_INT_NO_DEV_ACK) { 442 dev_dbg(i2c->dev, "No ACK from device\n"); 443 i2c->state = -ENXIO; 444 goto stop; 445 } else if (int_status & HSI2C_INT_NO_DEV) { 446 dev_dbg(i2c->dev, "No device\n"); 447 i2c->state = -ENXIO; 448 goto stop; 449 } else if (int_status & HSI2C_INT_TIMEOUT) { 450 dev_dbg(i2c->dev, "Accessing device timed out\n"); 451 i2c->state = -ETIMEDOUT; 452 goto stop; 453 } 454 } else if (int_status & HSI2C_INT_I2C) { 455 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS); 456 if (trans_status & HSI2C_NO_DEV_ACK) { 457 dev_dbg(i2c->dev, "No ACK from device\n"); 458 i2c->state = -ENXIO; 459 goto stop; 460 } else if (trans_status & HSI2C_NO_DEV) { 461 dev_dbg(i2c->dev, "No device\n"); 462 i2c->state = -ENXIO; 463 goto stop; 464 } else if (trans_status & HSI2C_TRANS_ABORT) { 465 dev_dbg(i2c->dev, "Deal with arbitration lose\n"); 466 i2c->state = -EAGAIN; 467 goto stop; 468 } else if (trans_status & HSI2C_TIMEOUT_AUTO) { 469 dev_dbg(i2c->dev, "Accessing device timed out\n"); 470 i2c->state = -ETIMEDOUT; 471 goto stop; 472 } else if (trans_status & HSI2C_TRANS_DONE) { 473 i2c->trans_done = 1; 474 i2c->state = 0; 475 } 476 } 477 478 if ((i2c->msg->flags & I2C_M_RD) && (int_status & 479 (HSI2C_INT_TRAILING | HSI2C_INT_RX_ALMOSTFULL))) { 480 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS); 481 fifo_level = HSI2C_RX_FIFO_LVL(fifo_status); 482 len = min(fifo_level, i2c->msg->len - i2c->msg_ptr); 483 484 while (len > 0) { 485 byte = (unsigned char) 486 readl(i2c->regs + HSI2C_RX_DATA); 487 i2c->msg->buf[i2c->msg_ptr++] = byte; 488 len--; 489 } 490 i2c->state = 0; 491 } else if (int_status & HSI2C_INT_TX_ALMOSTEMPTY) { 492 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS); 493 fifo_level = HSI2C_TX_FIFO_LVL(fifo_status); 494 495 len = i2c->variant->fifo_depth - fifo_level; 496 if (len > (i2c->msg->len - i2c->msg_ptr)) { 497 u32 int_en = readl(i2c->regs + HSI2C_INT_ENABLE); 498 499 int_en &= ~HSI2C_INT_TX_ALMOSTEMPTY_EN; 500 writel(int_en, i2c->regs + HSI2C_INT_ENABLE); 501 len = i2c->msg->len - i2c->msg_ptr; 502 } 503 504 while (len > 0) { 505 byte = i2c->msg->buf[i2c->msg_ptr++]; 506 writel(byte, i2c->regs + HSI2C_TX_DATA); 507 len--; 508 } 509 i2c->state = 0; 510 } 511 512 stop: 513 if ((i2c->trans_done && (i2c->msg->len == i2c->msg_ptr)) || 514 (i2c->state < 0)) { 515 writel(0, i2c->regs + HSI2C_INT_ENABLE); 516 exynos5_i2c_clr_pend_irq(i2c); 517 complete(&i2c->msg_complete); 518 } 519 520 spin_unlock(&i2c->lock); 521 522 return IRQ_HANDLED; 523 } 524 525 /* 526 * exynos5_i2c_wait_bus_idle 527 * 528 * Wait for the bus to go idle, indicated by the MASTER_BUSY bit being 529 * cleared. 530 * 531 * Returns -EBUSY if the bus cannot be bought to idle 532 */ 533 static int exynos5_i2c_wait_bus_idle(struct exynos5_i2c *i2c) 534 { 535 unsigned long stop_time; 536 u32 trans_status; 537 538 /* wait for 100 milli seconds for the bus to be idle */ 539 stop_time = jiffies + msecs_to_jiffies(100) + 1; 540 do { 541 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS); 542 if (!(trans_status & HSI2C_MASTER_BUSY)) 543 return 0; 544 545 usleep_range(50, 200); 546 } while (time_before(jiffies, stop_time)); 547 548 return -EBUSY; 549 } 550 551 static void exynos5_i2c_bus_recover(struct exynos5_i2c *i2c) 552 { 553 u32 val; 554 555 val = readl(i2c->regs + HSI2C_CTL) | HSI2C_RXCHON; 556 writel(val, i2c->regs + HSI2C_CTL); 557 val = readl(i2c->regs + HSI2C_CONF) & ~HSI2C_AUTO_MODE; 558 writel(val, i2c->regs + HSI2C_CONF); 559 560 /* 561 * Specification says master should send nine clock pulses. It can be 562 * emulated by sending manual read command (nine pulses for read eight 563 * bits + one pulse for NACK). 564 */ 565 writel(HSI2C_CMD_READ_DATA, i2c->regs + HSI2C_MANUAL_CMD); 566 exynos5_i2c_wait_bus_idle(i2c); 567 writel(HSI2C_CMD_SEND_STOP, i2c->regs + HSI2C_MANUAL_CMD); 568 exynos5_i2c_wait_bus_idle(i2c); 569 570 val = readl(i2c->regs + HSI2C_CTL) & ~HSI2C_RXCHON; 571 writel(val, i2c->regs + HSI2C_CTL); 572 val = readl(i2c->regs + HSI2C_CONF) | HSI2C_AUTO_MODE; 573 writel(val, i2c->regs + HSI2C_CONF); 574 } 575 576 static void exynos5_i2c_bus_check(struct exynos5_i2c *i2c) 577 { 578 unsigned long timeout; 579 580 if (i2c->variant->hw != I2C_TYPE_EXYNOS7) 581 return; 582 583 /* 584 * HSI2C_MASTER_ST_LOSE state in EXYNOS7 variant before transaction 585 * indicates that bus is stuck (SDA is low). In such case bus recovery 586 * can be performed. 587 */ 588 timeout = jiffies + msecs_to_jiffies(100); 589 for (;;) { 590 u32 st = readl(i2c->regs + HSI2C_TRANS_STATUS); 591 592 if ((st & HSI2C_MASTER_ST_MASK) != HSI2C_MASTER_ST_LOSE) 593 return; 594 595 if (time_is_before_jiffies(timeout)) 596 return; 597 598 exynos5_i2c_bus_recover(i2c); 599 } 600 } 601 602 /* 603 * exynos5_i2c_message_start: Configures the bus and starts the xfer 604 * i2c: struct exynos5_i2c pointer for the current bus 605 * stop: Enables stop after transfer if set. Set for last transfer of 606 * in the list of messages. 607 * 608 * Configures the bus for read/write function 609 * Sets chip address to talk to, message length to be sent. 610 * Enables appropriate interrupts and sends start xfer command. 611 */ 612 static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop) 613 { 614 u32 i2c_ctl; 615 u32 int_en = 0; 616 u32 i2c_auto_conf = 0; 617 u32 fifo_ctl; 618 unsigned long flags; 619 unsigned short trig_lvl; 620 621 if (i2c->variant->hw == I2C_TYPE_EXYNOS7) 622 int_en |= HSI2C_INT_I2C_TRANS; 623 else 624 int_en |= HSI2C_INT_I2C; 625 626 i2c_ctl = readl(i2c->regs + HSI2C_CTL); 627 i2c_ctl &= ~(HSI2C_TXCHON | HSI2C_RXCHON); 628 fifo_ctl = HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN; 629 630 if (i2c->msg->flags & I2C_M_RD) { 631 i2c_ctl |= HSI2C_RXCHON; 632 633 i2c_auto_conf |= HSI2C_READ_WRITE; 634 635 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ? 636 (i2c->variant->fifo_depth * 3 / 4) : i2c->msg->len; 637 fifo_ctl |= HSI2C_RXFIFO_TRIGGER_LEVEL(trig_lvl); 638 639 int_en |= (HSI2C_INT_RX_ALMOSTFULL_EN | 640 HSI2C_INT_TRAILING_EN); 641 } else { 642 i2c_ctl |= HSI2C_TXCHON; 643 644 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ? 645 (i2c->variant->fifo_depth * 1 / 4) : i2c->msg->len; 646 fifo_ctl |= HSI2C_TXFIFO_TRIGGER_LEVEL(trig_lvl); 647 648 int_en |= HSI2C_INT_TX_ALMOSTEMPTY_EN; 649 } 650 651 writel(HSI2C_SLV_ADDR_MAS(i2c->msg->addr), i2c->regs + HSI2C_ADDR); 652 653 writel(fifo_ctl, i2c->regs + HSI2C_FIFO_CTL); 654 writel(i2c_ctl, i2c->regs + HSI2C_CTL); 655 656 exynos5_i2c_bus_check(i2c); 657 658 /* 659 * Enable interrupts before starting the transfer so that we don't 660 * miss any INT_I2C interrupts. 661 */ 662 spin_lock_irqsave(&i2c->lock, flags); 663 writel(int_en, i2c->regs + HSI2C_INT_ENABLE); 664 665 if (stop == 1) 666 i2c_auto_conf |= HSI2C_STOP_AFTER_TRANS; 667 i2c_auto_conf |= i2c->msg->len; 668 i2c_auto_conf |= HSI2C_MASTER_RUN; 669 writel(i2c_auto_conf, i2c->regs + HSI2C_AUTO_CONF); 670 spin_unlock_irqrestore(&i2c->lock, flags); 671 } 672 673 static int exynos5_i2c_xfer_msg(struct exynos5_i2c *i2c, 674 struct i2c_msg *msgs, int stop) 675 { 676 unsigned long timeout; 677 int ret; 678 679 i2c->msg = msgs; 680 i2c->msg_ptr = 0; 681 i2c->trans_done = 0; 682 683 reinit_completion(&i2c->msg_complete); 684 685 exynos5_i2c_message_start(i2c, stop); 686 687 timeout = wait_for_completion_timeout(&i2c->msg_complete, 688 EXYNOS5_I2C_TIMEOUT); 689 if (timeout == 0) 690 ret = -ETIMEDOUT; 691 else 692 ret = i2c->state; 693 694 /* 695 * If this is the last message to be transfered (stop == 1) 696 * Then check if the bus can be brought back to idle. 697 */ 698 if (ret == 0 && stop) 699 ret = exynos5_i2c_wait_bus_idle(i2c); 700 701 if (ret < 0) { 702 exynos5_i2c_reset(i2c); 703 if (ret == -ETIMEDOUT) 704 dev_warn(i2c->dev, "%s timeout\n", 705 (msgs->flags & I2C_M_RD) ? "rx" : "tx"); 706 } 707 708 /* Return the state as in interrupt routine */ 709 return ret; 710 } 711 712 static int exynos5_i2c_xfer(struct i2c_adapter *adap, 713 struct i2c_msg *msgs, int num) 714 { 715 struct exynos5_i2c *i2c = adap->algo_data; 716 int i, ret; 717 718 if (i2c->suspended) { 719 dev_err(i2c->dev, "HS-I2C is not initialized.\n"); 720 return -EIO; 721 } 722 723 ret = clk_enable(i2c->clk); 724 if (ret) 725 return ret; 726 727 for (i = 0; i < num; ++i) { 728 ret = exynos5_i2c_xfer_msg(i2c, msgs + i, i + 1 == num); 729 if (ret) 730 break; 731 } 732 733 clk_disable(i2c->clk); 734 735 return ret ?: num; 736 } 737 738 static u32 exynos5_i2c_func(struct i2c_adapter *adap) 739 { 740 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 741 } 742 743 static const struct i2c_algorithm exynos5_i2c_algorithm = { 744 .master_xfer = exynos5_i2c_xfer, 745 .functionality = exynos5_i2c_func, 746 }; 747 748 static int exynos5_i2c_probe(struct platform_device *pdev) 749 { 750 struct device_node *np = pdev->dev.of_node; 751 struct exynos5_i2c *i2c; 752 struct resource *mem; 753 int ret; 754 755 i2c = devm_kzalloc(&pdev->dev, sizeof(struct exynos5_i2c), GFP_KERNEL); 756 if (!i2c) 757 return -ENOMEM; 758 759 if (of_property_read_u32(np, "clock-frequency", &i2c->op_clock)) 760 i2c->op_clock = HSI2C_FS_TX_CLOCK; 761 762 strlcpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name)); 763 i2c->adap.owner = THIS_MODULE; 764 i2c->adap.algo = &exynos5_i2c_algorithm; 765 i2c->adap.retries = 3; 766 767 i2c->dev = &pdev->dev; 768 i2c->clk = devm_clk_get(&pdev->dev, "hsi2c"); 769 if (IS_ERR(i2c->clk)) { 770 dev_err(&pdev->dev, "cannot get clock\n"); 771 return -ENOENT; 772 } 773 774 ret = clk_prepare_enable(i2c->clk); 775 if (ret) 776 return ret; 777 778 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 779 i2c->regs = devm_ioremap_resource(&pdev->dev, mem); 780 if (IS_ERR(i2c->regs)) { 781 ret = PTR_ERR(i2c->regs); 782 goto err_clk; 783 } 784 785 i2c->adap.dev.of_node = np; 786 i2c->adap.algo_data = i2c; 787 i2c->adap.dev.parent = &pdev->dev; 788 789 /* Clear pending interrupts from u-boot or misc causes */ 790 exynos5_i2c_clr_pend_irq(i2c); 791 792 spin_lock_init(&i2c->lock); 793 init_completion(&i2c->msg_complete); 794 795 i2c->irq = ret = platform_get_irq(pdev, 0); 796 if (ret <= 0) { 797 dev_err(&pdev->dev, "cannot find HS-I2C IRQ\n"); 798 ret = -EINVAL; 799 goto err_clk; 800 } 801 802 ret = devm_request_irq(&pdev->dev, i2c->irq, exynos5_i2c_irq, 803 IRQF_NO_SUSPEND | IRQF_ONESHOT, 804 dev_name(&pdev->dev), i2c); 805 806 if (ret != 0) { 807 dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n", i2c->irq); 808 goto err_clk; 809 } 810 811 i2c->variant = of_device_get_match_data(&pdev->dev); 812 813 ret = exynos5_hsi2c_clock_setup(i2c); 814 if (ret) 815 goto err_clk; 816 817 exynos5_i2c_reset(i2c); 818 819 ret = i2c_add_adapter(&i2c->adap); 820 if (ret < 0) 821 goto err_clk; 822 823 platform_set_drvdata(pdev, i2c); 824 825 clk_disable(i2c->clk); 826 827 return 0; 828 829 err_clk: 830 clk_disable_unprepare(i2c->clk); 831 return ret; 832 } 833 834 static int exynos5_i2c_remove(struct platform_device *pdev) 835 { 836 struct exynos5_i2c *i2c = platform_get_drvdata(pdev); 837 838 i2c_del_adapter(&i2c->adap); 839 840 clk_unprepare(i2c->clk); 841 842 return 0; 843 } 844 845 #ifdef CONFIG_PM_SLEEP 846 static int exynos5_i2c_suspend_noirq(struct device *dev) 847 { 848 struct exynos5_i2c *i2c = dev_get_drvdata(dev); 849 850 i2c->suspended = 1; 851 852 clk_unprepare(i2c->clk); 853 854 return 0; 855 } 856 857 static int exynos5_i2c_resume_noirq(struct device *dev) 858 { 859 struct exynos5_i2c *i2c = dev_get_drvdata(dev); 860 int ret = 0; 861 862 ret = clk_prepare_enable(i2c->clk); 863 if (ret) 864 return ret; 865 866 ret = exynos5_hsi2c_clock_setup(i2c); 867 if (ret) { 868 clk_disable_unprepare(i2c->clk); 869 return ret; 870 } 871 872 exynos5_i2c_init(i2c); 873 clk_disable(i2c->clk); 874 i2c->suspended = 0; 875 876 return 0; 877 } 878 #endif 879 880 static const struct dev_pm_ops exynos5_i2c_dev_pm_ops = { 881 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(exynos5_i2c_suspend_noirq, 882 exynos5_i2c_resume_noirq) 883 }; 884 885 static struct platform_driver exynos5_i2c_driver = { 886 .probe = exynos5_i2c_probe, 887 .remove = exynos5_i2c_remove, 888 .driver = { 889 .name = "exynos5-hsi2c", 890 .pm = &exynos5_i2c_dev_pm_ops, 891 .of_match_table = exynos5_i2c_match, 892 }, 893 }; 894 895 module_platform_driver(exynos5_i2c_driver); 896 897 MODULE_DESCRIPTION("Exynos5 HS-I2C Bus driver"); 898 MODULE_AUTHOR("Naveen Krishna Chatradhi, <ch.naveen@samsung.com>"); 899 MODULE_AUTHOR("Taekgyun Ko, <taeggyun.ko@samsung.com>"); 900 MODULE_LICENSE("GPL v2"); 901