1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver
4 *
5 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
6 */
7
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10
11 #include <linux/i2c.h>
12 #include <linux/time.h>
13 #include <linux/interrupt.h>
14 #include <linux/delay.h>
15 #include <linux/errno.h>
16 #include <linux/err.h>
17 #include <linux/platform_device.h>
18 #include <linux/clk.h>
19 #include <linux/slab.h>
20 #include <linux/io.h>
21 #include <linux/of.h>
22 #include <linux/spinlock.h>
23
24 /*
25 * HSI2C controller from Samsung supports 2 modes of operation
26 * 1. Auto mode: Where in master automatically controls the whole transaction
27 * 2. Manual mode: Software controls the transaction by issuing commands
28 * START, READ, WRITE, STOP, RESTART in I2C_MANUAL_CMD register.
29 *
30 * Operation mode can be selected by setting AUTO_MODE bit in I2C_CONF register
31 *
32 * Special bits are available for both modes of operation to set commands
33 * and for checking transfer status
34 */
35
36 /* Register Map */
37 #define HSI2C_CTL 0x00
38 #define HSI2C_FIFO_CTL 0x04
39 #define HSI2C_TRAILIG_CTL 0x08
40 #define HSI2C_CLK_CTL 0x0C
41 #define HSI2C_CLK_SLOT 0x10
42 #define HSI2C_INT_ENABLE 0x20
43 #define HSI2C_INT_STATUS 0x24
44 #define HSI2C_ERR_STATUS 0x2C
45 #define HSI2C_FIFO_STATUS 0x30
46 #define HSI2C_TX_DATA 0x34
47 #define HSI2C_RX_DATA 0x38
48 #define HSI2C_CONF 0x40
49 #define HSI2C_AUTO_CONF 0x44
50 #define HSI2C_TIMEOUT 0x48
51 #define HSI2C_MANUAL_CMD 0x4C
52 #define HSI2C_TRANS_STATUS 0x50
53 #define HSI2C_TIMING_HS1 0x54
54 #define HSI2C_TIMING_HS2 0x58
55 #define HSI2C_TIMING_HS3 0x5C
56 #define HSI2C_TIMING_FS1 0x60
57 #define HSI2C_TIMING_FS2 0x64
58 #define HSI2C_TIMING_FS3 0x68
59 #define HSI2C_TIMING_SLA 0x6C
60 #define HSI2C_ADDR 0x70
61
62 /* I2C_CTL Register bits */
63 #define HSI2C_FUNC_MODE_I2C (1u << 0)
64 #define HSI2C_MASTER (1u << 3)
65 #define HSI2C_RXCHON (1u << 6)
66 #define HSI2C_TXCHON (1u << 7)
67 #define HSI2C_SW_RST (1u << 31)
68
69 /* I2C_FIFO_CTL Register bits */
70 #define HSI2C_RXFIFO_EN (1u << 0)
71 #define HSI2C_TXFIFO_EN (1u << 1)
72 #define HSI2C_RXFIFO_TRIGGER_LEVEL(x) ((x) << 4)
73 #define HSI2C_TXFIFO_TRIGGER_LEVEL(x) ((x) << 16)
74
75 /* I2C_TRAILING_CTL Register bits */
76 #define HSI2C_TRAILING_COUNT (0xf)
77
78 /* I2C_INT_EN Register bits */
79 #define HSI2C_INT_TX_ALMOSTEMPTY_EN (1u << 0)
80 #define HSI2C_INT_RX_ALMOSTFULL_EN (1u << 1)
81 #define HSI2C_INT_TRAILING_EN (1u << 6)
82
83 /* I2C_INT_STAT Register bits */
84 #define HSI2C_INT_TX_ALMOSTEMPTY (1u << 0)
85 #define HSI2C_INT_RX_ALMOSTFULL (1u << 1)
86 #define HSI2C_INT_TX_UNDERRUN (1u << 2)
87 #define HSI2C_INT_TX_OVERRUN (1u << 3)
88 #define HSI2C_INT_RX_UNDERRUN (1u << 4)
89 #define HSI2C_INT_RX_OVERRUN (1u << 5)
90 #define HSI2C_INT_TRAILING (1u << 6)
91 #define HSI2C_INT_I2C (1u << 9)
92
93 #define HSI2C_INT_TRANS_DONE (1u << 7)
94 #define HSI2C_INT_TRANS_ABORT (1u << 8)
95 #define HSI2C_INT_NO_DEV_ACK (1u << 9)
96 #define HSI2C_INT_NO_DEV (1u << 10)
97 #define HSI2C_INT_TIMEOUT (1u << 11)
98 #define HSI2C_INT_I2C_TRANS (HSI2C_INT_TRANS_DONE | \
99 HSI2C_INT_TRANS_ABORT | \
100 HSI2C_INT_NO_DEV_ACK | \
101 HSI2C_INT_NO_DEV | \
102 HSI2C_INT_TIMEOUT)
103
104 /* I2C_FIFO_STAT Register bits */
105 #define HSI2C_RX_FIFO_EMPTY (1u << 24)
106 #define HSI2C_RX_FIFO_FULL (1u << 23)
107 #define HSI2C_RX_FIFO_LVL(x) ((x >> 16) & 0x7f)
108 #define HSI2C_TX_FIFO_EMPTY (1u << 8)
109 #define HSI2C_TX_FIFO_FULL (1u << 7)
110 #define HSI2C_TX_FIFO_LVL(x) ((x >> 0) & 0x7f)
111
112 /* I2C_CONF Register bits */
113 #define HSI2C_AUTO_MODE (1u << 31)
114 #define HSI2C_10BIT_ADDR_MODE (1u << 30)
115 #define HSI2C_HS_MODE (1u << 29)
116
117 /* I2C_AUTO_CONF Register bits */
118 #define HSI2C_READ_WRITE (1u << 16)
119 #define HSI2C_STOP_AFTER_TRANS (1u << 17)
120 #define HSI2C_MASTER_RUN (1u << 31)
121
122 /* I2C_TIMEOUT Register bits */
123 #define HSI2C_TIMEOUT_EN (1u << 31)
124 #define HSI2C_TIMEOUT_MASK 0xff
125
126 /* I2C_MANUAL_CMD register bits */
127 #define HSI2C_CMD_READ_DATA (1u << 4)
128 #define HSI2C_CMD_SEND_STOP (1u << 2)
129
130 /* I2C_TRANS_STATUS register bits */
131 #define HSI2C_MASTER_BUSY (1u << 17)
132 #define HSI2C_SLAVE_BUSY (1u << 16)
133
134 /* I2C_TRANS_STATUS register bits for Exynos5 variant */
135 #define HSI2C_TIMEOUT_AUTO (1u << 4)
136 #define HSI2C_NO_DEV (1u << 3)
137 #define HSI2C_NO_DEV_ACK (1u << 2)
138 #define HSI2C_TRANS_ABORT (1u << 1)
139 #define HSI2C_TRANS_DONE (1u << 0)
140
141 /* I2C_TRANS_STATUS register bits for Exynos7 variant */
142 #define HSI2C_MASTER_ST_MASK 0xf
143 #define HSI2C_MASTER_ST_IDLE 0x0
144 #define HSI2C_MASTER_ST_START 0x1
145 #define HSI2C_MASTER_ST_RESTART 0x2
146 #define HSI2C_MASTER_ST_STOP 0x3
147 #define HSI2C_MASTER_ST_MASTER_ID 0x4
148 #define HSI2C_MASTER_ST_ADDR0 0x5
149 #define HSI2C_MASTER_ST_ADDR1 0x6
150 #define HSI2C_MASTER_ST_ADDR2 0x7
151 #define HSI2C_MASTER_ST_ADDR_SR 0x8
152 #define HSI2C_MASTER_ST_READ 0x9
153 #define HSI2C_MASTER_ST_WRITE 0xa
154 #define HSI2C_MASTER_ST_NO_ACK 0xb
155 #define HSI2C_MASTER_ST_LOSE 0xc
156 #define HSI2C_MASTER_ST_WAIT 0xd
157 #define HSI2C_MASTER_ST_WAIT_CMD 0xe
158
159 /* I2C_ADDR register bits */
160 #define HSI2C_SLV_ADDR_SLV(x) ((x & 0x3ff) << 0)
161 #define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10)
162 #define HSI2C_MASTER_ID(x) ((x & 0xff) << 24)
163 #define MASTER_ID(x) ((x & 0x7) + 0x08)
164
165 #define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(100))
166
167 enum i2c_type_exynos {
168 I2C_TYPE_EXYNOS5,
169 I2C_TYPE_EXYNOS7,
170 I2C_TYPE_EXYNOSAUTOV9,
171 };
172
173 struct exynos5_i2c {
174 struct i2c_adapter adap;
175
176 struct i2c_msg *msg;
177 struct completion msg_complete;
178 unsigned int msg_ptr;
179
180 unsigned int irq;
181
182 void __iomem *regs;
183 struct clk *clk; /* operating clock */
184 struct clk *pclk; /* bus clock */
185 struct device *dev;
186 int state;
187
188 spinlock_t lock; /* IRQ synchronization */
189
190 /*
191 * Since the TRANS_DONE bit is cleared on read, and we may read it
192 * either during an IRQ or after a transaction, keep track of its
193 * state here.
194 */
195 int trans_done;
196
197 /* Controller operating frequency */
198 unsigned int op_clock;
199
200 /* Version of HS-I2C Hardware */
201 const struct exynos_hsi2c_variant *variant;
202 };
203
204 /**
205 * struct exynos_hsi2c_variant - platform specific HSI2C driver data
206 * @fifo_depth: the fifo depth supported by the HSI2C module
207 * @hw: the hardware variant of Exynos I2C controller
208 *
209 * Specifies platform specific configuration of HSI2C module.
210 * Note: A structure for driver specific platform data is used for future
211 * expansion of its usage.
212 */
213 struct exynos_hsi2c_variant {
214 unsigned int fifo_depth;
215 enum i2c_type_exynos hw;
216 };
217
218 static const struct exynos_hsi2c_variant exynos5250_hsi2c_data = {
219 .fifo_depth = 64,
220 .hw = I2C_TYPE_EXYNOS5,
221 };
222
223 static const struct exynos_hsi2c_variant exynos5260_hsi2c_data = {
224 .fifo_depth = 16,
225 .hw = I2C_TYPE_EXYNOS5,
226 };
227
228 static const struct exynos_hsi2c_variant exynos7_hsi2c_data = {
229 .fifo_depth = 16,
230 .hw = I2C_TYPE_EXYNOS7,
231 };
232
233 static const struct exynos_hsi2c_variant exynosautov9_hsi2c_data = {
234 .fifo_depth = 64,
235 .hw = I2C_TYPE_EXYNOSAUTOV9,
236 };
237
238 static const struct of_device_id exynos5_i2c_match[] = {
239 {
240 .compatible = "samsung,exynos5-hsi2c",
241 .data = &exynos5250_hsi2c_data
242 }, {
243 .compatible = "samsung,exynos5250-hsi2c",
244 .data = &exynos5250_hsi2c_data
245 }, {
246 .compatible = "samsung,exynos5260-hsi2c",
247 .data = &exynos5260_hsi2c_data
248 }, {
249 .compatible = "samsung,exynos7-hsi2c",
250 .data = &exynos7_hsi2c_data
251 }, {
252 .compatible = "samsung,exynosautov9-hsi2c",
253 .data = &exynosautov9_hsi2c_data
254 }, {},
255 };
256 MODULE_DEVICE_TABLE(of, exynos5_i2c_match);
257
exynos5_i2c_clr_pend_irq(struct exynos5_i2c * i2c)258 static void exynos5_i2c_clr_pend_irq(struct exynos5_i2c *i2c)
259 {
260 writel(readl(i2c->regs + HSI2C_INT_STATUS),
261 i2c->regs + HSI2C_INT_STATUS);
262 }
263
264 /*
265 * exynos5_i2c_set_timing: updates the registers with appropriate
266 * timing values calculated
267 *
268 * Timing values for operation are calculated against either 100kHz
269 * or 1MHz controller operating frequency.
270 *
271 * Returns 0 on success, -EINVAL if the cycle length cannot
272 * be calculated.
273 */
exynos5_i2c_set_timing(struct exynos5_i2c * i2c,bool hs_timings)274 static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, bool hs_timings)
275 {
276 u32 i2c_timing_s1;
277 u32 i2c_timing_s2;
278 u32 i2c_timing_s3;
279 u32 i2c_timing_sla;
280 unsigned int t_start_su, t_start_hd;
281 unsigned int t_stop_su;
282 unsigned int t_data_su, t_data_hd;
283 unsigned int t_scl_l, t_scl_h;
284 unsigned int t_sr_release;
285 unsigned int t_ftl_cycle;
286 unsigned int clkin = clk_get_rate(i2c->clk);
287 unsigned int op_clk = hs_timings ? i2c->op_clock :
288 (i2c->op_clock >= I2C_MAX_FAST_MODE_PLUS_FREQ) ? I2C_MAX_STANDARD_MODE_FREQ :
289 i2c->op_clock;
290 int div, clk_cycle, temp;
291
292 /*
293 * In case of HSI2C controllers in ExynosAutoV9:
294 *
295 * FSCL = IPCLK / ((CLK_DIV + 1) * 16)
296 * T_SCL_LOW = IPCLK * (CLK_DIV + 1) * (N + M)
297 * [N : number of 0's in the TSCL_H_HS]
298 * [M : number of 0's in the TSCL_L_HS]
299 * T_SCL_HIGH = IPCLK * (CLK_DIV + 1) * (N + M)
300 * [N : number of 1's in the TSCL_H_HS]
301 * [M : number of 1's in the TSCL_L_HS]
302 *
303 * Result of (N + M) is always 8.
304 * In general case, we don't need to control timing_s1 and timing_s2.
305 */
306 if (i2c->variant->hw == I2C_TYPE_EXYNOSAUTOV9) {
307 div = ((clkin / (16 * i2c->op_clock)) - 1);
308 i2c_timing_s3 = div << 16;
309 if (hs_timings)
310 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3);
311 else
312 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3);
313
314 return 0;
315 }
316
317 /*
318 * In case of HSI2C controller in Exynos5 series
319 * FPCLK / FI2C =
320 * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE
321 *
322 * In case of HSI2C controllers in Exynos7 series
323 * FPCLK / FI2C =
324 * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + FLT_CYCLE
325 *
326 * clk_cycle := TSCLK_L + TSCLK_H
327 * temp := (CLK_DIV + 1) * (clk_cycle + 2)
328 *
329 * Constraints: 4 <= temp, 0 <= CLK_DIV < 256, 2 <= clk_cycle <= 510
330 *
331 */
332 t_ftl_cycle = (readl(i2c->regs + HSI2C_CONF) >> 16) & 0x7;
333 temp = clkin / op_clk - 8 - t_ftl_cycle;
334 if (i2c->variant->hw != I2C_TYPE_EXYNOS7)
335 temp -= t_ftl_cycle;
336 div = temp / 512;
337 clk_cycle = temp / (div + 1) - 2;
338 if (temp < 4 || div >= 256 || clk_cycle < 2) {
339 dev_err(i2c->dev, "%s clock set-up failed\n",
340 hs_timings ? "HS" : "FS");
341 return -EINVAL;
342 }
343
344 t_scl_l = clk_cycle / 2;
345 t_scl_h = clk_cycle / 2;
346 t_start_su = t_scl_l;
347 t_start_hd = t_scl_l;
348 t_stop_su = t_scl_l;
349 t_data_su = t_scl_l / 2;
350 t_data_hd = t_scl_l / 2;
351 t_sr_release = clk_cycle;
352
353 i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8;
354 i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0;
355 i2c_timing_s3 = div << 16 | t_sr_release << 0;
356 i2c_timing_sla = t_data_hd << 0;
357
358 dev_dbg(i2c->dev, "tSTART_SU: %X, tSTART_HD: %X, tSTOP_SU: %X\n",
359 t_start_su, t_start_hd, t_stop_su);
360 dev_dbg(i2c->dev, "tDATA_SU: %X, tSCL_L: %X, tSCL_H: %X\n",
361 t_data_su, t_scl_l, t_scl_h);
362 dev_dbg(i2c->dev, "nClkDiv: %X, tSR_RELEASE: %X\n",
363 div, t_sr_release);
364 dev_dbg(i2c->dev, "tDATA_HD: %X\n", t_data_hd);
365
366 if (hs_timings) {
367 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_HS1);
368 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_HS2);
369 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3);
370 } else {
371 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_FS1);
372 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_FS2);
373 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3);
374 }
375 writel(i2c_timing_sla, i2c->regs + HSI2C_TIMING_SLA);
376
377 return 0;
378 }
379
exynos5_hsi2c_clock_setup(struct exynos5_i2c * i2c)380 static int exynos5_hsi2c_clock_setup(struct exynos5_i2c *i2c)
381 {
382 /* always set Fast Speed timings */
383 int ret = exynos5_i2c_set_timing(i2c, false);
384
385 if (ret < 0 || i2c->op_clock < I2C_MAX_FAST_MODE_PLUS_FREQ)
386 return ret;
387
388 return exynos5_i2c_set_timing(i2c, true);
389 }
390
391 /*
392 * exynos5_i2c_init: configures the controller for I2C functionality
393 * Programs I2C controller for Master mode operation
394 */
exynos5_i2c_init(struct exynos5_i2c * i2c)395 static void exynos5_i2c_init(struct exynos5_i2c *i2c)
396 {
397 u32 i2c_conf = readl(i2c->regs + HSI2C_CONF);
398 u32 i2c_timeout = readl(i2c->regs + HSI2C_TIMEOUT);
399
400 /* Clear to disable Timeout */
401 i2c_timeout &= ~HSI2C_TIMEOUT_EN;
402 writel(i2c_timeout, i2c->regs + HSI2C_TIMEOUT);
403
404 writel((HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
405 i2c->regs + HSI2C_CTL);
406 writel(HSI2C_TRAILING_COUNT, i2c->regs + HSI2C_TRAILIG_CTL);
407
408 if (i2c->op_clock >= I2C_MAX_FAST_MODE_PLUS_FREQ) {
409 writel(HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr)),
410 i2c->regs + HSI2C_ADDR);
411 i2c_conf |= HSI2C_HS_MODE;
412 }
413
414 writel(i2c_conf | HSI2C_AUTO_MODE, i2c->regs + HSI2C_CONF);
415 }
416
exynos5_i2c_reset(struct exynos5_i2c * i2c)417 static void exynos5_i2c_reset(struct exynos5_i2c *i2c)
418 {
419 u32 i2c_ctl;
420
421 /* Set and clear the bit for reset */
422 i2c_ctl = readl(i2c->regs + HSI2C_CTL);
423 i2c_ctl |= HSI2C_SW_RST;
424 writel(i2c_ctl, i2c->regs + HSI2C_CTL);
425
426 i2c_ctl = readl(i2c->regs + HSI2C_CTL);
427 i2c_ctl &= ~HSI2C_SW_RST;
428 writel(i2c_ctl, i2c->regs + HSI2C_CTL);
429
430 /* We don't expect calculations to fail during the run */
431 exynos5_hsi2c_clock_setup(i2c);
432 /* Initialize the configure registers */
433 exynos5_i2c_init(i2c);
434 }
435
436 /*
437 * exynos5_i2c_irq: top level IRQ servicing routine
438 *
439 * INT_STATUS registers gives the interrupt details. Further,
440 * FIFO_STATUS or TRANS_STATUS registers are to be check for detailed
441 * state of the bus.
442 */
exynos5_i2c_irq(int irqno,void * dev_id)443 static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id)
444 {
445 struct exynos5_i2c *i2c = dev_id;
446 u32 fifo_level, int_status, fifo_status, trans_status;
447 unsigned char byte;
448 int len = 0;
449
450 i2c->state = -EINVAL;
451
452 spin_lock(&i2c->lock);
453
454 int_status = readl(i2c->regs + HSI2C_INT_STATUS);
455 writel(int_status, i2c->regs + HSI2C_INT_STATUS);
456
457 /* handle interrupt related to the transfer status */
458 switch (i2c->variant->hw) {
459 case I2C_TYPE_EXYNOSAUTOV9:
460 fallthrough;
461 case I2C_TYPE_EXYNOS7:
462 if (int_status & HSI2C_INT_TRANS_DONE) {
463 i2c->trans_done = 1;
464 i2c->state = 0;
465 } else if (int_status & HSI2C_INT_TRANS_ABORT) {
466 dev_dbg(i2c->dev, "Deal with arbitration lose\n");
467 i2c->state = -EAGAIN;
468 goto stop;
469 } else if (int_status & HSI2C_INT_NO_DEV_ACK) {
470 dev_dbg(i2c->dev, "No ACK from device\n");
471 i2c->state = -ENXIO;
472 goto stop;
473 } else if (int_status & HSI2C_INT_NO_DEV) {
474 dev_dbg(i2c->dev, "No device\n");
475 i2c->state = -ENXIO;
476 goto stop;
477 } else if (int_status & HSI2C_INT_TIMEOUT) {
478 dev_dbg(i2c->dev, "Accessing device timed out\n");
479 i2c->state = -ETIMEDOUT;
480 goto stop;
481 }
482
483 break;
484 case I2C_TYPE_EXYNOS5:
485 if (!(int_status & HSI2C_INT_I2C))
486 break;
487
488 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
489 if (trans_status & HSI2C_NO_DEV_ACK) {
490 dev_dbg(i2c->dev, "No ACK from device\n");
491 i2c->state = -ENXIO;
492 goto stop;
493 } else if (trans_status & HSI2C_NO_DEV) {
494 dev_dbg(i2c->dev, "No device\n");
495 i2c->state = -ENXIO;
496 goto stop;
497 } else if (trans_status & HSI2C_TRANS_ABORT) {
498 dev_dbg(i2c->dev, "Deal with arbitration lose\n");
499 i2c->state = -EAGAIN;
500 goto stop;
501 } else if (trans_status & HSI2C_TIMEOUT_AUTO) {
502 dev_dbg(i2c->dev, "Accessing device timed out\n");
503 i2c->state = -ETIMEDOUT;
504 goto stop;
505 } else if (trans_status & HSI2C_TRANS_DONE) {
506 i2c->trans_done = 1;
507 i2c->state = 0;
508 }
509
510 break;
511 }
512
513 if ((i2c->msg->flags & I2C_M_RD) && (int_status &
514 (HSI2C_INT_TRAILING | HSI2C_INT_RX_ALMOSTFULL))) {
515 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);
516 fifo_level = HSI2C_RX_FIFO_LVL(fifo_status);
517 len = min(fifo_level, i2c->msg->len - i2c->msg_ptr);
518
519 while (len > 0) {
520 byte = (unsigned char)
521 readl(i2c->regs + HSI2C_RX_DATA);
522 i2c->msg->buf[i2c->msg_ptr++] = byte;
523 len--;
524 }
525 i2c->state = 0;
526 } else if (int_status & HSI2C_INT_TX_ALMOSTEMPTY) {
527 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);
528 fifo_level = HSI2C_TX_FIFO_LVL(fifo_status);
529
530 len = i2c->variant->fifo_depth - fifo_level;
531 if (len > (i2c->msg->len - i2c->msg_ptr)) {
532 u32 int_en = readl(i2c->regs + HSI2C_INT_ENABLE);
533
534 int_en &= ~HSI2C_INT_TX_ALMOSTEMPTY_EN;
535 writel(int_en, i2c->regs + HSI2C_INT_ENABLE);
536 len = i2c->msg->len - i2c->msg_ptr;
537 }
538
539 while (len > 0) {
540 byte = i2c->msg->buf[i2c->msg_ptr++];
541 writel(byte, i2c->regs + HSI2C_TX_DATA);
542 len--;
543 }
544 i2c->state = 0;
545 }
546
547 stop:
548 if ((i2c->trans_done && (i2c->msg->len == i2c->msg_ptr)) ||
549 (i2c->state < 0)) {
550 writel(0, i2c->regs + HSI2C_INT_ENABLE);
551 exynos5_i2c_clr_pend_irq(i2c);
552 complete(&i2c->msg_complete);
553 }
554
555 spin_unlock(&i2c->lock);
556
557 return IRQ_HANDLED;
558 }
559
560 /*
561 * exynos5_i2c_wait_bus_idle
562 *
563 * Wait for the bus to go idle, indicated by the MASTER_BUSY bit being
564 * cleared.
565 *
566 * Returns -EBUSY if the bus cannot be bought to idle
567 */
exynos5_i2c_wait_bus_idle(struct exynos5_i2c * i2c)568 static int exynos5_i2c_wait_bus_idle(struct exynos5_i2c *i2c)
569 {
570 unsigned long stop_time;
571 u32 trans_status;
572
573 /* wait for 100 milli seconds for the bus to be idle */
574 stop_time = jiffies + msecs_to_jiffies(100) + 1;
575 do {
576 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
577 if (!(trans_status & HSI2C_MASTER_BUSY))
578 return 0;
579
580 usleep_range(50, 200);
581 } while (time_before(jiffies, stop_time));
582
583 return -EBUSY;
584 }
585
exynos5_i2c_bus_recover(struct exynos5_i2c * i2c)586 static void exynos5_i2c_bus_recover(struct exynos5_i2c *i2c)
587 {
588 u32 val;
589
590 val = readl(i2c->regs + HSI2C_CTL) | HSI2C_RXCHON;
591 writel(val, i2c->regs + HSI2C_CTL);
592 val = readl(i2c->regs + HSI2C_CONF) & ~HSI2C_AUTO_MODE;
593 writel(val, i2c->regs + HSI2C_CONF);
594
595 /*
596 * Specification says master should send nine clock pulses. It can be
597 * emulated by sending manual read command (nine pulses for read eight
598 * bits + one pulse for NACK).
599 */
600 writel(HSI2C_CMD_READ_DATA, i2c->regs + HSI2C_MANUAL_CMD);
601 exynos5_i2c_wait_bus_idle(i2c);
602 writel(HSI2C_CMD_SEND_STOP, i2c->regs + HSI2C_MANUAL_CMD);
603 exynos5_i2c_wait_bus_idle(i2c);
604
605 val = readl(i2c->regs + HSI2C_CTL) & ~HSI2C_RXCHON;
606 writel(val, i2c->regs + HSI2C_CTL);
607 val = readl(i2c->regs + HSI2C_CONF) | HSI2C_AUTO_MODE;
608 writel(val, i2c->regs + HSI2C_CONF);
609 }
610
exynos5_i2c_bus_check(struct exynos5_i2c * i2c)611 static void exynos5_i2c_bus_check(struct exynos5_i2c *i2c)
612 {
613 unsigned long timeout;
614
615 if (i2c->variant->hw == I2C_TYPE_EXYNOS5)
616 return;
617
618 /*
619 * HSI2C_MASTER_ST_LOSE state (in Exynos7 and ExynosAutoV9 variants)
620 * before transaction indicates that bus is stuck (SDA is low).
621 * In such case bus recovery can be performed.
622 */
623 timeout = jiffies + msecs_to_jiffies(100);
624 for (;;) {
625 u32 st = readl(i2c->regs + HSI2C_TRANS_STATUS);
626
627 if ((st & HSI2C_MASTER_ST_MASK) != HSI2C_MASTER_ST_LOSE)
628 return;
629
630 if (time_is_before_jiffies(timeout))
631 return;
632
633 exynos5_i2c_bus_recover(i2c);
634 }
635 }
636
637 /*
638 * exynos5_i2c_message_start: Configures the bus and starts the xfer
639 * i2c: struct exynos5_i2c pointer for the current bus
640 * stop: Enables stop after transfer if set. Set for last transfer of
641 * in the list of messages.
642 *
643 * Configures the bus for read/write function
644 * Sets chip address to talk to, message length to be sent.
645 * Enables appropriate interrupts and sends start xfer command.
646 */
exynos5_i2c_message_start(struct exynos5_i2c * i2c,int stop)647 static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop)
648 {
649 u32 i2c_ctl;
650 u32 int_en = 0;
651 u32 i2c_auto_conf = 0;
652 u32 i2c_addr = 0;
653 u32 fifo_ctl;
654 unsigned long flags;
655 unsigned short trig_lvl;
656
657 if (i2c->variant->hw == I2C_TYPE_EXYNOS5)
658 int_en |= HSI2C_INT_I2C;
659 else
660 int_en |= HSI2C_INT_I2C_TRANS;
661
662 i2c_ctl = readl(i2c->regs + HSI2C_CTL);
663 i2c_ctl &= ~(HSI2C_TXCHON | HSI2C_RXCHON);
664 fifo_ctl = HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN;
665
666 if (i2c->msg->flags & I2C_M_RD) {
667 i2c_ctl |= HSI2C_RXCHON;
668
669 i2c_auto_conf |= HSI2C_READ_WRITE;
670
671 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ?
672 (i2c->variant->fifo_depth * 3 / 4) : i2c->msg->len;
673 fifo_ctl |= HSI2C_RXFIFO_TRIGGER_LEVEL(trig_lvl);
674
675 int_en |= (HSI2C_INT_RX_ALMOSTFULL_EN |
676 HSI2C_INT_TRAILING_EN);
677 } else {
678 i2c_ctl |= HSI2C_TXCHON;
679
680 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ?
681 (i2c->variant->fifo_depth * 1 / 4) : i2c->msg->len;
682 fifo_ctl |= HSI2C_TXFIFO_TRIGGER_LEVEL(trig_lvl);
683
684 int_en |= HSI2C_INT_TX_ALMOSTEMPTY_EN;
685 }
686
687 i2c_addr = HSI2C_SLV_ADDR_MAS(i2c->msg->addr);
688
689 if (i2c->op_clock >= I2C_MAX_FAST_MODE_PLUS_FREQ)
690 i2c_addr |= HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr));
691
692 writel(i2c_addr, i2c->regs + HSI2C_ADDR);
693
694 writel(fifo_ctl, i2c->regs + HSI2C_FIFO_CTL);
695 writel(i2c_ctl, i2c->regs + HSI2C_CTL);
696
697 exynos5_i2c_bus_check(i2c);
698
699 /*
700 * Enable interrupts before starting the transfer so that we don't
701 * miss any INT_I2C interrupts.
702 */
703 spin_lock_irqsave(&i2c->lock, flags);
704 writel(int_en, i2c->regs + HSI2C_INT_ENABLE);
705
706 if (stop == 1)
707 i2c_auto_conf |= HSI2C_STOP_AFTER_TRANS;
708 i2c_auto_conf |= i2c->msg->len;
709 i2c_auto_conf |= HSI2C_MASTER_RUN;
710 writel(i2c_auto_conf, i2c->regs + HSI2C_AUTO_CONF);
711 spin_unlock_irqrestore(&i2c->lock, flags);
712 }
713
exynos5_i2c_xfer_msg(struct exynos5_i2c * i2c,struct i2c_msg * msgs,int stop)714 static int exynos5_i2c_xfer_msg(struct exynos5_i2c *i2c,
715 struct i2c_msg *msgs, int stop)
716 {
717 unsigned long timeout;
718 int ret;
719
720 i2c->msg = msgs;
721 i2c->msg_ptr = 0;
722 i2c->trans_done = 0;
723
724 reinit_completion(&i2c->msg_complete);
725
726 exynos5_i2c_message_start(i2c, stop);
727
728 timeout = wait_for_completion_timeout(&i2c->msg_complete,
729 EXYNOS5_I2C_TIMEOUT);
730 if (timeout == 0)
731 ret = -ETIMEDOUT;
732 else
733 ret = i2c->state;
734
735 /*
736 * If this is the last message to be transfered (stop == 1)
737 * Then check if the bus can be brought back to idle.
738 */
739 if (ret == 0 && stop)
740 ret = exynos5_i2c_wait_bus_idle(i2c);
741
742 if (ret < 0) {
743 exynos5_i2c_reset(i2c);
744 if (ret == -ETIMEDOUT)
745 dev_warn(i2c->dev, "%s timeout\n",
746 (msgs->flags & I2C_M_RD) ? "rx" : "tx");
747 }
748
749 /* Return the state as in interrupt routine */
750 return ret;
751 }
752
exynos5_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)753 static int exynos5_i2c_xfer(struct i2c_adapter *adap,
754 struct i2c_msg *msgs, int num)
755 {
756 struct exynos5_i2c *i2c = adap->algo_data;
757 int i, ret;
758
759 ret = clk_enable(i2c->pclk);
760 if (ret)
761 return ret;
762
763 ret = clk_enable(i2c->clk);
764 if (ret)
765 goto err_pclk;
766
767 for (i = 0; i < num; ++i) {
768 ret = exynos5_i2c_xfer_msg(i2c, msgs + i, i + 1 == num);
769 if (ret)
770 break;
771 }
772
773 clk_disable(i2c->clk);
774 err_pclk:
775 clk_disable(i2c->pclk);
776
777 return ret ?: num;
778 }
779
exynos5_i2c_func(struct i2c_adapter * adap)780 static u32 exynos5_i2c_func(struct i2c_adapter *adap)
781 {
782 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
783 }
784
785 static const struct i2c_algorithm exynos5_i2c_algorithm = {
786 .master_xfer = exynos5_i2c_xfer,
787 .functionality = exynos5_i2c_func,
788 };
789
exynos5_i2c_probe(struct platform_device * pdev)790 static int exynos5_i2c_probe(struct platform_device *pdev)
791 {
792 struct device_node *np = pdev->dev.of_node;
793 struct exynos5_i2c *i2c;
794 int ret;
795
796 i2c = devm_kzalloc(&pdev->dev, sizeof(struct exynos5_i2c), GFP_KERNEL);
797 if (!i2c)
798 return -ENOMEM;
799
800 if (of_property_read_u32(np, "clock-frequency", &i2c->op_clock))
801 i2c->op_clock = I2C_MAX_STANDARD_MODE_FREQ;
802
803 strscpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name));
804 i2c->adap.owner = THIS_MODULE;
805 i2c->adap.algo = &exynos5_i2c_algorithm;
806 i2c->adap.retries = 3;
807
808 i2c->dev = &pdev->dev;
809 i2c->clk = devm_clk_get(&pdev->dev, "hsi2c");
810 if (IS_ERR(i2c->clk)) {
811 dev_err(&pdev->dev, "cannot get clock\n");
812 return -ENOENT;
813 }
814
815 i2c->pclk = devm_clk_get_optional(&pdev->dev, "hsi2c_pclk");
816 if (IS_ERR(i2c->pclk)) {
817 return dev_err_probe(&pdev->dev, PTR_ERR(i2c->pclk),
818 "cannot get pclk");
819 }
820
821 ret = clk_prepare_enable(i2c->pclk);
822 if (ret)
823 return ret;
824
825 ret = clk_prepare_enable(i2c->clk);
826 if (ret)
827 goto err_pclk;
828
829 i2c->regs = devm_platform_ioremap_resource(pdev, 0);
830 if (IS_ERR(i2c->regs)) {
831 ret = PTR_ERR(i2c->regs);
832 goto err_clk;
833 }
834
835 i2c->adap.dev.of_node = np;
836 i2c->adap.algo_data = i2c;
837 i2c->adap.dev.parent = &pdev->dev;
838
839 /* Clear pending interrupts from u-boot or misc causes */
840 exynos5_i2c_clr_pend_irq(i2c);
841
842 spin_lock_init(&i2c->lock);
843 init_completion(&i2c->msg_complete);
844
845 i2c->irq = ret = platform_get_irq(pdev, 0);
846 if (ret < 0)
847 goto err_clk;
848
849 ret = devm_request_irq(&pdev->dev, i2c->irq, exynos5_i2c_irq,
850 IRQF_NO_SUSPEND, dev_name(&pdev->dev), i2c);
851 if (ret != 0) {
852 dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n", i2c->irq);
853 goto err_clk;
854 }
855
856 i2c->variant = of_device_get_match_data(&pdev->dev);
857
858 ret = exynos5_hsi2c_clock_setup(i2c);
859 if (ret)
860 goto err_clk;
861
862 exynos5_i2c_reset(i2c);
863
864 ret = i2c_add_adapter(&i2c->adap);
865 if (ret < 0)
866 goto err_clk;
867
868 platform_set_drvdata(pdev, i2c);
869
870 clk_disable(i2c->clk);
871 clk_disable(i2c->pclk);
872
873 return 0;
874
875 err_clk:
876 clk_disable_unprepare(i2c->clk);
877
878 err_pclk:
879 clk_disable_unprepare(i2c->pclk);
880 return ret;
881 }
882
exynos5_i2c_remove(struct platform_device * pdev)883 static void exynos5_i2c_remove(struct platform_device *pdev)
884 {
885 struct exynos5_i2c *i2c = platform_get_drvdata(pdev);
886
887 i2c_del_adapter(&i2c->adap);
888
889 clk_unprepare(i2c->clk);
890 clk_unprepare(i2c->pclk);
891 }
892
exynos5_i2c_suspend_noirq(struct device * dev)893 static int exynos5_i2c_suspend_noirq(struct device *dev)
894 {
895 struct exynos5_i2c *i2c = dev_get_drvdata(dev);
896
897 i2c_mark_adapter_suspended(&i2c->adap);
898 clk_unprepare(i2c->clk);
899 clk_unprepare(i2c->pclk);
900
901 return 0;
902 }
903
exynos5_i2c_resume_noirq(struct device * dev)904 static int exynos5_i2c_resume_noirq(struct device *dev)
905 {
906 struct exynos5_i2c *i2c = dev_get_drvdata(dev);
907 int ret = 0;
908
909 ret = clk_prepare_enable(i2c->pclk);
910 if (ret)
911 return ret;
912
913 ret = clk_prepare_enable(i2c->clk);
914 if (ret)
915 goto err_pclk;
916
917 ret = exynos5_hsi2c_clock_setup(i2c);
918 if (ret)
919 goto err_clk;
920
921 exynos5_i2c_init(i2c);
922 clk_disable(i2c->clk);
923 clk_disable(i2c->pclk);
924 i2c_mark_adapter_resumed(&i2c->adap);
925
926 return 0;
927
928 err_clk:
929 clk_disable_unprepare(i2c->clk);
930 err_pclk:
931 clk_disable_unprepare(i2c->pclk);
932 return ret;
933 }
934
935 static const struct dev_pm_ops exynos5_i2c_dev_pm_ops = {
936 NOIRQ_SYSTEM_SLEEP_PM_OPS(exynos5_i2c_suspend_noirq,
937 exynos5_i2c_resume_noirq)
938 };
939
940 static struct platform_driver exynos5_i2c_driver = {
941 .probe = exynos5_i2c_probe,
942 .remove_new = exynos5_i2c_remove,
943 .driver = {
944 .name = "exynos5-hsi2c",
945 .pm = pm_sleep_ptr(&exynos5_i2c_dev_pm_ops),
946 .of_match_table = exynos5_i2c_match,
947 },
948 };
949
950 module_platform_driver(exynos5_i2c_driver);
951
952 MODULE_DESCRIPTION("Exynos5 HS-I2C Bus driver");
953 MODULE_AUTHOR("Naveen Krishna Chatradhi <ch.naveen@samsung.com>");
954 MODULE_AUTHOR("Taekgyun Ko <taeggyun.ko@samsung.com>");
955 MODULE_LICENSE("GPL v2");
956