1 /*
2  * Synopsys DesignWare I2C adapter driver (master only).
3  *
4  * Based on the TI DAVINCI I2C adapter driver.
5  *
6  * Copyright (C) 2006 Texas Instruments.
7  * Copyright (C) 2007 MontaVista Software Inc.
8  * Copyright (C) 2009 Provigent Ltd.
9  * Copyright (C) 2011 Intel corporation.
10  *
11  * ----------------------------------------------------------------------------
12  *
13  * This program is free software; you can redistribute it and/or modify
14  * it under the terms of the GNU General Public License as published by
15  * the Free Software Foundation; either version 2 of the License, or
16  * (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software
25  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26  * ----------------------------------------------------------------------------
27  *
28  */
29 
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/delay.h>
33 #include <linux/i2c.h>
34 #include <linux/errno.h>
35 #include <linux/sched.h>
36 #include <linux/err.h>
37 #include <linux/interrupt.h>
38 #include <linux/io.h>
39 #include <linux/slab.h>
40 #include <linux/pci.h>
41 #include <linux/pm_runtime.h>
42 #include "i2c-designware-core.h"
43 
44 #define DRIVER_NAME "i2c-designware-pci"
45 
46 enum dw_pci_ctl_id_t {
47 	moorestown_0,
48 	moorestown_1,
49 	moorestown_2,
50 
51 	medfield_0,
52 	medfield_1,
53 	medfield_2,
54 	medfield_3,
55 	medfield_4,
56 	medfield_5,
57 
58 	baytrail,
59 };
60 
61 struct dw_scl_sda_cfg {
62 	u32 ss_hcnt;
63 	u32 fs_hcnt;
64 	u32 ss_lcnt;
65 	u32 fs_lcnt;
66 	u32 sda_hold;
67 };
68 
69 struct dw_pci_controller {
70 	u32 bus_num;
71 	u32 bus_cfg;
72 	u32 tx_fifo_depth;
73 	u32 rx_fifo_depth;
74 	u32 clk_khz;
75 	u32 functionality;
76 	struct dw_scl_sda_cfg *scl_sda_cfg;
77 };
78 
79 #define INTEL_MID_STD_CFG  (DW_IC_CON_MASTER |			\
80 				DW_IC_CON_SLAVE_DISABLE |	\
81 				DW_IC_CON_RESTART_EN)
82 
83 #define DW_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C |			\
84 					I2C_FUNC_SMBUS_BYTE |		\
85 					I2C_FUNC_SMBUS_BYTE_DATA |	\
86 					I2C_FUNC_SMBUS_WORD_DATA |	\
87 					I2C_FUNC_SMBUS_I2C_BLOCK)
88 
89 /* BayTrail HCNT/LCNT/SDA hold time */
90 static struct dw_scl_sda_cfg byt_config = {
91 	.ss_hcnt = 0x200,
92 	.fs_hcnt = 0x55,
93 	.ss_lcnt = 0x200,
94 	.fs_lcnt = 0x99,
95 	.sda_hold = 0x6,
96 };
97 
98 static struct  dw_pci_controller  dw_pci_controllers[] = {
99 	[moorestown_0] = {
100 		.bus_num     = 0,
101 		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
102 		.tx_fifo_depth = 32,
103 		.rx_fifo_depth = 32,
104 		.clk_khz      = 25000,
105 	},
106 	[moorestown_1] = {
107 		.bus_num     = 1,
108 		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
109 		.tx_fifo_depth = 32,
110 		.rx_fifo_depth = 32,
111 		.clk_khz      = 25000,
112 	},
113 	[moorestown_2] = {
114 		.bus_num     = 2,
115 		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
116 		.tx_fifo_depth = 32,
117 		.rx_fifo_depth = 32,
118 		.clk_khz      = 25000,
119 	},
120 	[medfield_0] = {
121 		.bus_num     = 0,
122 		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
123 		.tx_fifo_depth = 32,
124 		.rx_fifo_depth = 32,
125 		.clk_khz      = 25000,
126 	},
127 	[medfield_1] = {
128 		.bus_num     = 1,
129 		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
130 		.tx_fifo_depth = 32,
131 		.rx_fifo_depth = 32,
132 		.clk_khz      = 25000,
133 	},
134 	[medfield_2] = {
135 		.bus_num     = 2,
136 		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
137 		.tx_fifo_depth = 32,
138 		.rx_fifo_depth = 32,
139 		.clk_khz      = 25000,
140 	},
141 	[medfield_3] = {
142 		.bus_num     = 3,
143 		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_STD,
144 		.tx_fifo_depth = 32,
145 		.rx_fifo_depth = 32,
146 		.clk_khz      = 25000,
147 	},
148 	[medfield_4] = {
149 		.bus_num     = 4,
150 		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
151 		.tx_fifo_depth = 32,
152 		.rx_fifo_depth = 32,
153 		.clk_khz      = 25000,
154 	},
155 	[medfield_5] = {
156 		.bus_num     = 5,
157 		.bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
158 		.tx_fifo_depth = 32,
159 		.rx_fifo_depth = 32,
160 		.clk_khz      = 25000,
161 	},
162 	[baytrail] = {
163 		.bus_num = -1,
164 		.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
165 		.tx_fifo_depth = 32,
166 		.rx_fifo_depth = 32,
167 		.clk_khz = 100000,
168 		.functionality = I2C_FUNC_10BIT_ADDR,
169 		.scl_sda_cfg = &byt_config,
170 	},
171 };
172 static struct i2c_algorithm i2c_dw_algo = {
173 	.master_xfer	= i2c_dw_xfer,
174 	.functionality	= i2c_dw_func,
175 };
176 
177 #ifdef CONFIG_PM
178 static int i2c_dw_pci_suspend(struct device *dev)
179 {
180 	struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
181 
182 	i2c_dw_disable(pci_get_drvdata(pdev));
183 	return 0;
184 }
185 
186 static int i2c_dw_pci_resume(struct device *dev)
187 {
188 	struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
189 
190 	return i2c_dw_init(pci_get_drvdata(pdev));
191 }
192 #endif
193 
194 static UNIVERSAL_DEV_PM_OPS(i2c_dw_pm_ops, i2c_dw_pci_suspend,
195 			    i2c_dw_pci_resume, NULL);
196 
197 static u32 i2c_dw_get_clk_rate_khz(struct dw_i2c_dev *dev)
198 {
199 	return dev->controller->clk_khz;
200 }
201 
202 static int i2c_dw_pci_probe(struct pci_dev *pdev,
203 			    const struct pci_device_id *id)
204 {
205 	struct dw_i2c_dev *dev;
206 	struct i2c_adapter *adap;
207 	int r;
208 	struct  dw_pci_controller *controller;
209 	struct dw_scl_sda_cfg *cfg;
210 
211 	if (id->driver_data >= ARRAY_SIZE(dw_pci_controllers)) {
212 		dev_err(&pdev->dev, "%s: invalid driver data %ld\n", __func__,
213 			id->driver_data);
214 		return -EINVAL;
215 	}
216 
217 	controller = &dw_pci_controllers[id->driver_data];
218 
219 	r = pcim_enable_device(pdev);
220 	if (r) {
221 		dev_err(&pdev->dev, "Failed to enable I2C PCI device (%d)\n",
222 			r);
223 		return r;
224 	}
225 
226 	r = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
227 	if (r) {
228 		dev_err(&pdev->dev, "I/O memory remapping failed\n");
229 		return r;
230 	}
231 
232 	dev = devm_kzalloc(&pdev->dev, sizeof(struct dw_i2c_dev), GFP_KERNEL);
233 	if (!dev)
234 		return -ENOMEM;
235 
236 	init_completion(&dev->cmd_complete);
237 	mutex_init(&dev->lock);
238 	dev->clk = NULL;
239 	dev->controller = controller;
240 	dev->get_clk_rate_khz = i2c_dw_get_clk_rate_khz;
241 	dev->base = pcim_iomap_table(pdev)[0];
242 	dev->dev = &pdev->dev;
243 	dev->functionality = controller->functionality |
244 				DW_DEFAULT_FUNCTIONALITY;
245 
246 	dev->master_cfg =  controller->bus_cfg;
247 	if (controller->scl_sda_cfg) {
248 		cfg = controller->scl_sda_cfg;
249 		dev->ss_hcnt = cfg->ss_hcnt;
250 		dev->fs_hcnt = cfg->fs_hcnt;
251 		dev->ss_lcnt = cfg->ss_lcnt;
252 		dev->fs_lcnt = cfg->fs_lcnt;
253 		dev->sda_hold_time = cfg->sda_hold;
254 	}
255 
256 	pci_set_drvdata(pdev, dev);
257 
258 	dev->tx_fifo_depth = controller->tx_fifo_depth;
259 	dev->rx_fifo_depth = controller->rx_fifo_depth;
260 	r = i2c_dw_init(dev);
261 	if (r)
262 		return r;
263 
264 	adap = &dev->adapter;
265 	i2c_set_adapdata(adap, dev);
266 	adap->owner = THIS_MODULE;
267 	adap->class = 0;
268 	adap->algo = &i2c_dw_algo;
269 	adap->dev.parent = &pdev->dev;
270 	adap->nr = controller->bus_num;
271 
272 	snprintf(adap->name, sizeof(adap->name), "i2c-designware-pci");
273 
274 	r = devm_request_irq(&pdev->dev, pdev->irq, i2c_dw_isr, IRQF_SHARED,
275 			adap->name, dev);
276 	if (r) {
277 		dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
278 		return r;
279 	}
280 
281 	i2c_dw_disable_int(dev);
282 	i2c_dw_clear_int(dev);
283 	r = i2c_add_numbered_adapter(adap);
284 	if (r) {
285 		dev_err(&pdev->dev, "failure adding adapter\n");
286 		return r;
287 	}
288 
289 	pm_runtime_set_autosuspend_delay(&pdev->dev, 1000);
290 	pm_runtime_use_autosuspend(&pdev->dev);
291 	pm_runtime_put_autosuspend(&pdev->dev);
292 	pm_runtime_allow(&pdev->dev);
293 
294 	return 0;
295 }
296 
297 static void i2c_dw_pci_remove(struct pci_dev *pdev)
298 {
299 	struct dw_i2c_dev *dev = pci_get_drvdata(pdev);
300 
301 	i2c_dw_disable(dev);
302 	pm_runtime_forbid(&pdev->dev);
303 	pm_runtime_get_noresume(&pdev->dev);
304 
305 	i2c_del_adapter(&dev->adapter);
306 }
307 
308 /* work with hotplug and coldplug */
309 MODULE_ALIAS("i2c_designware-pci");
310 
311 static const struct pci_device_id i2_designware_pci_ids[] = {
312 	/* Moorestown */
313 	{ PCI_VDEVICE(INTEL, 0x0802), moorestown_0 },
314 	{ PCI_VDEVICE(INTEL, 0x0803), moorestown_1 },
315 	{ PCI_VDEVICE(INTEL, 0x0804), moorestown_2 },
316 	/* Medfield */
317 	{ PCI_VDEVICE(INTEL, 0x0817), medfield_3,},
318 	{ PCI_VDEVICE(INTEL, 0x0818), medfield_4 },
319 	{ PCI_VDEVICE(INTEL, 0x0819), medfield_5 },
320 	{ PCI_VDEVICE(INTEL, 0x082C), medfield_0 },
321 	{ PCI_VDEVICE(INTEL, 0x082D), medfield_1 },
322 	{ PCI_VDEVICE(INTEL, 0x082E), medfield_2 },
323 	/* Baytrail */
324 	{ PCI_VDEVICE(INTEL, 0x0F41), baytrail },
325 	{ PCI_VDEVICE(INTEL, 0x0F42), baytrail },
326 	{ PCI_VDEVICE(INTEL, 0x0F43), baytrail },
327 	{ PCI_VDEVICE(INTEL, 0x0F44), baytrail },
328 	{ PCI_VDEVICE(INTEL, 0x0F45), baytrail },
329 	{ PCI_VDEVICE(INTEL, 0x0F46), baytrail },
330 	{ PCI_VDEVICE(INTEL, 0x0F47), baytrail },
331 	{ 0,}
332 };
333 MODULE_DEVICE_TABLE(pci, i2_designware_pci_ids);
334 
335 static struct pci_driver dw_i2c_driver = {
336 	.name		= DRIVER_NAME,
337 	.id_table	= i2_designware_pci_ids,
338 	.probe		= i2c_dw_pci_probe,
339 	.remove		= i2c_dw_pci_remove,
340 	.driver         = {
341 		.pm     = &i2c_dw_pm_ops,
342 	},
343 };
344 
345 module_pci_driver(dw_i2c_driver);
346 
347 MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
348 MODULE_DESCRIPTION("Synopsys DesignWare PCI I2C bus adapter");
349 MODULE_LICENSE("GPL");
350