1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Synopsys DesignWare I2C adapter driver (master only). 4 * 5 * Based on the TI DAVINCI I2C adapter driver. 6 * 7 * Copyright (C) 2006 Texas Instruments. 8 * Copyright (C) 2007 MontaVista Software Inc. 9 * Copyright (C) 2009 Provigent Ltd. 10 * Copyright (C) 2011, 2015, 2016 Intel Corporation. 11 */ 12 #include <linux/acpi.h> 13 #include <linux/delay.h> 14 #include <linux/err.h> 15 #include <linux/errno.h> 16 #include <linux/i2c.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/pci.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/sched.h> 24 #include <linux/slab.h> 25 26 #include "i2c-designware-core.h" 27 28 #define DRIVER_NAME "i2c-designware-pci" 29 30 enum dw_pci_ctl_id_t { 31 medfield, 32 merrifield, 33 baytrail, 34 cherrytrail, 35 haswell, 36 }; 37 38 struct dw_scl_sda_cfg { 39 u32 ss_hcnt; 40 u32 fs_hcnt; 41 u32 ss_lcnt; 42 u32 fs_lcnt; 43 u32 sda_hold; 44 }; 45 46 struct dw_pci_controller { 47 u32 bus_num; 48 u32 bus_cfg; 49 u32 tx_fifo_depth; 50 u32 rx_fifo_depth; 51 u32 clk_khz; 52 u32 functionality; 53 u32 flags; 54 struct dw_scl_sda_cfg *scl_sda_cfg; 55 int (*setup)(struct pci_dev *pdev, struct dw_pci_controller *c); 56 }; 57 58 #define INTEL_MID_STD_CFG (DW_IC_CON_MASTER | \ 59 DW_IC_CON_SLAVE_DISABLE | \ 60 DW_IC_CON_RESTART_EN) 61 62 /* Merrifield HCNT/LCNT/SDA hold time */ 63 static struct dw_scl_sda_cfg mrfld_config = { 64 .ss_hcnt = 0x2f8, 65 .fs_hcnt = 0x87, 66 .ss_lcnt = 0x37b, 67 .fs_lcnt = 0x10a, 68 }; 69 70 /* BayTrail HCNT/LCNT/SDA hold time */ 71 static struct dw_scl_sda_cfg byt_config = { 72 .ss_hcnt = 0x200, 73 .fs_hcnt = 0x55, 74 .ss_lcnt = 0x200, 75 .fs_lcnt = 0x99, 76 .sda_hold = 0x6, 77 }; 78 79 /* Haswell HCNT/LCNT/SDA hold time */ 80 static struct dw_scl_sda_cfg hsw_config = { 81 .ss_hcnt = 0x01b0, 82 .fs_hcnt = 0x48, 83 .ss_lcnt = 0x01fb, 84 .fs_lcnt = 0xa0, 85 .sda_hold = 0x9, 86 }; 87 88 static int mfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c) 89 { 90 switch (pdev->device) { 91 case 0x0817: 92 c->bus_cfg &= ~DW_IC_CON_SPEED_MASK; 93 c->bus_cfg |= DW_IC_CON_SPEED_STD; 94 /* fall through */ 95 case 0x0818: 96 case 0x0819: 97 c->bus_num = pdev->device - 0x817 + 3; 98 return 0; 99 case 0x082C: 100 case 0x082D: 101 case 0x082E: 102 c->bus_num = pdev->device - 0x82C + 0; 103 return 0; 104 } 105 return -ENODEV; 106 } 107 108 static int mrfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c) 109 { 110 /* 111 * On Intel Merrifield the user visible i2c busses are enumerated 112 * [1..7]. So, we add 1 to shift the default range. Besides that the 113 * first PCI slot provides 4 functions, that's why we have to add 0 to 114 * the first slot and 4 to the next one. 115 */ 116 switch (PCI_SLOT(pdev->devfn)) { 117 case 8: 118 c->bus_num = PCI_FUNC(pdev->devfn) + 0 + 1; 119 return 0; 120 case 9: 121 c->bus_num = PCI_FUNC(pdev->devfn) + 4 + 1; 122 return 0; 123 } 124 return -ENODEV; 125 } 126 127 static struct dw_pci_controller dw_pci_controllers[] = { 128 [medfield] = { 129 .bus_num = -1, 130 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST, 131 .tx_fifo_depth = 32, 132 .rx_fifo_depth = 32, 133 .functionality = I2C_FUNC_10BIT_ADDR, 134 .clk_khz = 25000, 135 .setup = mfld_setup, 136 }, 137 [merrifield] = { 138 .bus_num = -1, 139 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST, 140 .tx_fifo_depth = 64, 141 .rx_fifo_depth = 64, 142 .functionality = I2C_FUNC_10BIT_ADDR, 143 .scl_sda_cfg = &mrfld_config, 144 .setup = mrfld_setup, 145 }, 146 [baytrail] = { 147 .bus_num = -1, 148 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST, 149 .tx_fifo_depth = 32, 150 .rx_fifo_depth = 32, 151 .functionality = I2C_FUNC_10BIT_ADDR, 152 .scl_sda_cfg = &byt_config, 153 }, 154 [haswell] = { 155 .bus_num = -1, 156 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST, 157 .tx_fifo_depth = 32, 158 .rx_fifo_depth = 32, 159 .functionality = I2C_FUNC_10BIT_ADDR, 160 .scl_sda_cfg = &hsw_config, 161 }, 162 [cherrytrail] = { 163 .bus_num = -1, 164 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST, 165 .tx_fifo_depth = 32, 166 .rx_fifo_depth = 32, 167 .functionality = I2C_FUNC_10BIT_ADDR, 168 .flags = MODEL_CHERRYTRAIL, 169 .scl_sda_cfg = &byt_config, 170 }, 171 }; 172 173 #ifdef CONFIG_PM 174 static int i2c_dw_pci_suspend(struct device *dev) 175 { 176 struct pci_dev *pdev = to_pci_dev(dev); 177 struct dw_i2c_dev *i_dev = pci_get_drvdata(pdev); 178 179 i_dev->suspended = true; 180 i_dev->disable(i_dev); 181 182 return 0; 183 } 184 185 static int i2c_dw_pci_resume(struct device *dev) 186 { 187 struct pci_dev *pdev = to_pci_dev(dev); 188 struct dw_i2c_dev *i_dev = pci_get_drvdata(pdev); 189 int ret; 190 191 ret = i_dev->init(i_dev); 192 i_dev->suspended = false; 193 194 return ret; 195 } 196 #endif 197 198 static UNIVERSAL_DEV_PM_OPS(i2c_dw_pm_ops, i2c_dw_pci_suspend, 199 i2c_dw_pci_resume, NULL); 200 201 static u32 i2c_dw_get_clk_rate_khz(struct dw_i2c_dev *dev) 202 { 203 return dev->controller->clk_khz; 204 } 205 206 static int i2c_dw_pci_probe(struct pci_dev *pdev, 207 const struct pci_device_id *id) 208 { 209 struct dw_i2c_dev *dev; 210 struct i2c_adapter *adap; 211 int r; 212 struct dw_pci_controller *controller; 213 struct dw_scl_sda_cfg *cfg; 214 215 if (id->driver_data >= ARRAY_SIZE(dw_pci_controllers)) { 216 dev_err(&pdev->dev, "%s: invalid driver data %ld\n", __func__, 217 id->driver_data); 218 return -EINVAL; 219 } 220 221 controller = &dw_pci_controllers[id->driver_data]; 222 223 r = pcim_enable_device(pdev); 224 if (r) { 225 dev_err(&pdev->dev, "Failed to enable I2C PCI device (%d)\n", 226 r); 227 return r; 228 } 229 230 r = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev)); 231 if (r) { 232 dev_err(&pdev->dev, "I/O memory remapping failed\n"); 233 return r; 234 } 235 236 dev = devm_kzalloc(&pdev->dev, sizeof(struct dw_i2c_dev), GFP_KERNEL); 237 if (!dev) 238 return -ENOMEM; 239 240 dev->clk = NULL; 241 dev->controller = controller; 242 dev->get_clk_rate_khz = i2c_dw_get_clk_rate_khz; 243 dev->base = pcim_iomap_table(pdev)[0]; 244 dev->dev = &pdev->dev; 245 dev->irq = pdev->irq; 246 dev->flags |= controller->flags; 247 248 if (controller->setup) { 249 r = controller->setup(pdev, controller); 250 if (r) 251 return r; 252 } 253 254 dev->functionality = controller->functionality | 255 DW_IC_DEFAULT_FUNCTIONALITY; 256 257 dev->master_cfg = controller->bus_cfg; 258 if (controller->scl_sda_cfg) { 259 cfg = controller->scl_sda_cfg; 260 dev->ss_hcnt = cfg->ss_hcnt; 261 dev->fs_hcnt = cfg->fs_hcnt; 262 dev->ss_lcnt = cfg->ss_lcnt; 263 dev->fs_lcnt = cfg->fs_lcnt; 264 dev->sda_hold_time = cfg->sda_hold; 265 } 266 267 pci_set_drvdata(pdev, dev); 268 269 dev->tx_fifo_depth = controller->tx_fifo_depth; 270 dev->rx_fifo_depth = controller->rx_fifo_depth; 271 272 adap = &dev->adapter; 273 adap->owner = THIS_MODULE; 274 adap->class = 0; 275 ACPI_COMPANION_SET(&adap->dev, ACPI_COMPANION(&pdev->dev)); 276 adap->nr = controller->bus_num; 277 278 r = i2c_dw_probe(dev); 279 if (r) 280 return r; 281 282 pm_runtime_set_autosuspend_delay(&pdev->dev, 1000); 283 pm_runtime_use_autosuspend(&pdev->dev); 284 pm_runtime_put_autosuspend(&pdev->dev); 285 pm_runtime_allow(&pdev->dev); 286 287 return 0; 288 } 289 290 static void i2c_dw_pci_remove(struct pci_dev *pdev) 291 { 292 struct dw_i2c_dev *dev = pci_get_drvdata(pdev); 293 294 dev->disable(dev); 295 pm_runtime_forbid(&pdev->dev); 296 pm_runtime_get_noresume(&pdev->dev); 297 298 i2c_del_adapter(&dev->adapter); 299 } 300 301 /* work with hotplug and coldplug */ 302 MODULE_ALIAS("i2c_designware-pci"); 303 304 static const struct pci_device_id i2_designware_pci_ids[] = { 305 /* Medfield */ 306 { PCI_VDEVICE(INTEL, 0x0817), medfield }, 307 { PCI_VDEVICE(INTEL, 0x0818), medfield }, 308 { PCI_VDEVICE(INTEL, 0x0819), medfield }, 309 { PCI_VDEVICE(INTEL, 0x082C), medfield }, 310 { PCI_VDEVICE(INTEL, 0x082D), medfield }, 311 { PCI_VDEVICE(INTEL, 0x082E), medfield }, 312 /* Merrifield */ 313 { PCI_VDEVICE(INTEL, 0x1195), merrifield }, 314 { PCI_VDEVICE(INTEL, 0x1196), merrifield }, 315 /* Baytrail */ 316 { PCI_VDEVICE(INTEL, 0x0F41), baytrail }, 317 { PCI_VDEVICE(INTEL, 0x0F42), baytrail }, 318 { PCI_VDEVICE(INTEL, 0x0F43), baytrail }, 319 { PCI_VDEVICE(INTEL, 0x0F44), baytrail }, 320 { PCI_VDEVICE(INTEL, 0x0F45), baytrail }, 321 { PCI_VDEVICE(INTEL, 0x0F46), baytrail }, 322 { PCI_VDEVICE(INTEL, 0x0F47), baytrail }, 323 /* Haswell */ 324 { PCI_VDEVICE(INTEL, 0x9c61), haswell }, 325 { PCI_VDEVICE(INTEL, 0x9c62), haswell }, 326 /* Braswell / Cherrytrail */ 327 { PCI_VDEVICE(INTEL, 0x22C1), cherrytrail }, 328 { PCI_VDEVICE(INTEL, 0x22C2), cherrytrail }, 329 { PCI_VDEVICE(INTEL, 0x22C3), cherrytrail }, 330 { PCI_VDEVICE(INTEL, 0x22C4), cherrytrail }, 331 { PCI_VDEVICE(INTEL, 0x22C5), cherrytrail }, 332 { PCI_VDEVICE(INTEL, 0x22C6), cherrytrail }, 333 { PCI_VDEVICE(INTEL, 0x22C7), cherrytrail }, 334 { 0,} 335 }; 336 MODULE_DEVICE_TABLE(pci, i2_designware_pci_ids); 337 338 static struct pci_driver dw_i2c_driver = { 339 .name = DRIVER_NAME, 340 .id_table = i2_designware_pci_ids, 341 .probe = i2c_dw_pci_probe, 342 .remove = i2c_dw_pci_remove, 343 .driver = { 344 .pm = &i2c_dw_pm_ops, 345 }, 346 }; 347 348 module_pci_driver(dw_i2c_driver); 349 350 MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>"); 351 MODULE_DESCRIPTION("Synopsys DesignWare PCI I2C bus adapter"); 352 MODULE_LICENSE("GPL"); 353