1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Synopsys DesignWare I2C adapter driver (master only).
4  *
5  * Based on the TI DAVINCI I2C adapter driver.
6  *
7  * Copyright (C) 2006 Texas Instruments.
8  * Copyright (C) 2007 MontaVista Software Inc.
9  * Copyright (C) 2009 Provigent Ltd.
10  * Copyright (C) 2011, 2015, 2016 Intel Corporation.
11  */
12 #include <linux/acpi.h>
13 #include <linux/delay.h>
14 #include <linux/err.h>
15 #include <linux/errno.h>
16 #include <linux/i2c.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/sched.h>
24 #include <linux/slab.h>
25 
26 #include "i2c-designware-core.h"
27 #include "i2c-ccgx-ucsi.h"
28 
29 #define DRIVER_NAME "i2c-designware-pci"
30 
31 enum dw_pci_ctl_id_t {
32 	medfield,
33 	merrifield,
34 	baytrail,
35 	cherrytrail,
36 	haswell,
37 	elkhartlake,
38 	navi_amd,
39 };
40 
41 /*
42  * This is a legacy structure to describe the hardware counters
43  * to configure signal timings on the bus. For Device Tree platforms
44  * one should use the respective properties and for ACPI there is
45  * a set of ACPI methods that provide these counters. No new
46  * platform should use this structure.
47  */
48 struct dw_scl_sda_cfg {
49 	u16 ss_hcnt;
50 	u16 fs_hcnt;
51 	u16 ss_lcnt;
52 	u16 fs_lcnt;
53 	u32 sda_hold;
54 };
55 
56 struct dw_pci_controller {
57 	u32 bus_num;
58 	u32 flags;
59 	struct dw_scl_sda_cfg *scl_sda_cfg;
60 	int (*setup)(struct pci_dev *pdev, struct dw_pci_controller *c);
61 	u32 (*get_clk_rate_khz)(struct dw_i2c_dev *dev);
62 };
63 
64 /* Merrifield HCNT/LCNT/SDA hold time */
65 static struct dw_scl_sda_cfg mrfld_config = {
66 	.ss_hcnt = 0x2f8,
67 	.fs_hcnt = 0x87,
68 	.ss_lcnt = 0x37b,
69 	.fs_lcnt = 0x10a,
70 };
71 
72 /* BayTrail HCNT/LCNT/SDA hold time */
73 static struct dw_scl_sda_cfg byt_config = {
74 	.ss_hcnt = 0x200,
75 	.fs_hcnt = 0x55,
76 	.ss_lcnt = 0x200,
77 	.fs_lcnt = 0x99,
78 	.sda_hold = 0x6,
79 };
80 
81 /* Haswell HCNT/LCNT/SDA hold time */
82 static struct dw_scl_sda_cfg hsw_config = {
83 	.ss_hcnt = 0x01b0,
84 	.fs_hcnt = 0x48,
85 	.ss_lcnt = 0x01fb,
86 	.fs_lcnt = 0xa0,
87 	.sda_hold = 0x9,
88 };
89 
90 /* NAVI-AMD HCNT/LCNT/SDA hold time */
91 static struct dw_scl_sda_cfg navi_amd_config = {
92 	.ss_hcnt = 0x1ae,
93 	.ss_lcnt = 0x23a,
94 	.sda_hold = 0x9,
95 };
96 
97 static u32 mfld_get_clk_rate_khz(struct dw_i2c_dev *dev)
98 {
99 	return 25000;
100 }
101 
102 static int mfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c)
103 {
104 	struct dw_i2c_dev *dev = dev_get_drvdata(&pdev->dev);
105 
106 	switch (pdev->device) {
107 	case 0x0817:
108 		dev->timings.bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
109 		fallthrough;
110 	case 0x0818:
111 	case 0x0819:
112 		c->bus_num = pdev->device - 0x817 + 3;
113 		return 0;
114 	case 0x082C:
115 	case 0x082D:
116 	case 0x082E:
117 		c->bus_num = pdev->device - 0x82C + 0;
118 		return 0;
119 	}
120 	return -ENODEV;
121 }
122 
123 static int mrfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c)
124 {
125 	/*
126 	 * On Intel Merrifield the user visible i2c buses are enumerated
127 	 * [1..7]. So, we add 1 to shift the default range. Besides that the
128 	 * first PCI slot provides 4 functions, that's why we have to add 0 to
129 	 * the first slot and 4 to the next one.
130 	 */
131 	switch (PCI_SLOT(pdev->devfn)) {
132 	case 8:
133 		c->bus_num = PCI_FUNC(pdev->devfn) + 0 + 1;
134 		return 0;
135 	case 9:
136 		c->bus_num = PCI_FUNC(pdev->devfn) + 4 + 1;
137 		return 0;
138 	}
139 	return -ENODEV;
140 }
141 
142 static u32 ehl_get_clk_rate_khz(struct dw_i2c_dev *dev)
143 {
144 	return 100000;
145 }
146 
147 static u32 navi_amd_get_clk_rate_khz(struct dw_i2c_dev *dev)
148 {
149 	return 100000;
150 }
151 
152 static int navi_amd_setup(struct pci_dev *pdev, struct dw_pci_controller *c)
153 {
154 	struct dw_i2c_dev *dev = dev_get_drvdata(&pdev->dev);
155 
156 	dev->flags |= MODEL_AMD_NAVI_GPU;
157 	dev->timings.bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
158 	return 0;
159 }
160 
161 static struct dw_pci_controller dw_pci_controllers[] = {
162 	[medfield] = {
163 		.bus_num = -1,
164 		.setup = mfld_setup,
165 		.get_clk_rate_khz = mfld_get_clk_rate_khz,
166 	},
167 	[merrifield] = {
168 		.bus_num = -1,
169 		.scl_sda_cfg = &mrfld_config,
170 		.setup = mrfld_setup,
171 	},
172 	[baytrail] = {
173 		.bus_num = -1,
174 		.scl_sda_cfg = &byt_config,
175 	},
176 	[haswell] = {
177 		.bus_num = -1,
178 		.scl_sda_cfg = &hsw_config,
179 	},
180 	[cherrytrail] = {
181 		.bus_num = -1,
182 		.scl_sda_cfg = &byt_config,
183 	},
184 	[elkhartlake] = {
185 		.bus_num = -1,
186 		.get_clk_rate_khz = ehl_get_clk_rate_khz,
187 	},
188 	[navi_amd] = {
189 		.bus_num = -1,
190 		.scl_sda_cfg = &navi_amd_config,
191 		.setup =  navi_amd_setup,
192 		.get_clk_rate_khz = navi_amd_get_clk_rate_khz,
193 	},
194 };
195 
196 static int __maybe_unused i2c_dw_pci_runtime_suspend(struct device *dev)
197 {
198 	struct dw_i2c_dev *i_dev = dev_get_drvdata(dev);
199 
200 	i_dev->disable(i_dev);
201 	return 0;
202 }
203 
204 static int __maybe_unused i2c_dw_pci_suspend(struct device *dev)
205 {
206 	struct dw_i2c_dev *i_dev = dev_get_drvdata(dev);
207 
208 	i2c_mark_adapter_suspended(&i_dev->adapter);
209 
210 	return i2c_dw_pci_runtime_suspend(dev);
211 }
212 
213 static int __maybe_unused i2c_dw_pci_runtime_resume(struct device *dev)
214 {
215 	struct dw_i2c_dev *i_dev = dev_get_drvdata(dev);
216 
217 	return i_dev->init(i_dev);
218 }
219 
220 static int __maybe_unused i2c_dw_pci_resume(struct device *dev)
221 {
222 	struct dw_i2c_dev *i_dev = dev_get_drvdata(dev);
223 	int ret;
224 
225 	ret = i2c_dw_pci_runtime_resume(dev);
226 
227 	i2c_mark_adapter_resumed(&i_dev->adapter);
228 
229 	return ret;
230 }
231 
232 static const struct dev_pm_ops i2c_dw_pm_ops = {
233 	SET_SYSTEM_SLEEP_PM_OPS(i2c_dw_pci_suspend, i2c_dw_pci_resume)
234 	SET_RUNTIME_PM_OPS(i2c_dw_pci_runtime_suspend, i2c_dw_pci_runtime_resume, NULL)
235 };
236 
237 static int i2c_dw_pci_probe(struct pci_dev *pdev,
238 			    const struct pci_device_id *id)
239 {
240 	struct dw_i2c_dev *dev;
241 	struct i2c_adapter *adap;
242 	int r;
243 	struct dw_pci_controller *controller;
244 	struct dw_scl_sda_cfg *cfg;
245 	struct i2c_timings *t;
246 
247 	if (id->driver_data >= ARRAY_SIZE(dw_pci_controllers))
248 		return dev_err_probe(&pdev->dev, -EINVAL,
249 				     "Invalid driver data %ld\n",
250 				     id->driver_data);
251 
252 	controller = &dw_pci_controllers[id->driver_data];
253 
254 	r = pcim_enable_device(pdev);
255 	if (r)
256 		return dev_err_probe(&pdev->dev, r,
257 				     "Failed to enable I2C PCI device\n");
258 
259 	pci_set_master(pdev);
260 
261 	r = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
262 	if (r)
263 		return dev_err_probe(&pdev->dev, r,
264 				     "I/O memory remapping failed\n");
265 
266 	dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
267 	if (!dev)
268 		return -ENOMEM;
269 
270 	r = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
271 	if (r < 0)
272 		return r;
273 
274 	dev->get_clk_rate_khz = controller->get_clk_rate_khz;
275 	dev->base = pcim_iomap_table(pdev)[0];
276 	dev->dev = &pdev->dev;
277 	dev->irq = pci_irq_vector(pdev, 0);
278 	dev->flags |= controller->flags;
279 
280 	t = &dev->timings;
281 	i2c_parse_fw_timings(&pdev->dev, t, false);
282 
283 	pci_set_drvdata(pdev, dev);
284 
285 	if (controller->setup) {
286 		r = controller->setup(pdev, controller);
287 		if (r) {
288 			pci_free_irq_vectors(pdev);
289 			return r;
290 		}
291 	}
292 
293 	i2c_dw_adjust_bus_speed(dev);
294 
295 	if (has_acpi_companion(&pdev->dev))
296 		i2c_dw_acpi_configure(&pdev->dev);
297 
298 	r = i2c_dw_validate_speed(dev);
299 	if (r) {
300 		pci_free_irq_vectors(pdev);
301 		return r;
302 	}
303 
304 	i2c_dw_configure(dev);
305 
306 	if (controller->scl_sda_cfg) {
307 		cfg = controller->scl_sda_cfg;
308 		dev->ss_hcnt = cfg->ss_hcnt;
309 		dev->fs_hcnt = cfg->fs_hcnt;
310 		dev->ss_lcnt = cfg->ss_lcnt;
311 		dev->fs_lcnt = cfg->fs_lcnt;
312 		dev->sda_hold_time = cfg->sda_hold;
313 	}
314 
315 	adap = &dev->adapter;
316 	adap->owner = THIS_MODULE;
317 	adap->class = 0;
318 	ACPI_COMPANION_SET(&adap->dev, ACPI_COMPANION(&pdev->dev));
319 	adap->nr = controller->bus_num;
320 
321 	r = i2c_dw_probe(dev);
322 	if (r) {
323 		pci_free_irq_vectors(pdev);
324 		return r;
325 	}
326 
327 	if ((dev->flags & MODEL_MASK) == MODEL_AMD_NAVI_GPU) {
328 		dev->slave = i2c_new_ccgx_ucsi(&dev->adapter, dev->irq, NULL);
329 		if (IS_ERR(dev->slave))
330 			return dev_err_probe(dev->dev, PTR_ERR(dev->slave),
331 					     "register UCSI failed\n");
332 	}
333 
334 	pm_runtime_set_autosuspend_delay(&pdev->dev, 1000);
335 	pm_runtime_use_autosuspend(&pdev->dev);
336 	pm_runtime_put_autosuspend(&pdev->dev);
337 	pm_runtime_allow(&pdev->dev);
338 
339 	return 0;
340 }
341 
342 static void i2c_dw_pci_remove(struct pci_dev *pdev)
343 {
344 	struct dw_i2c_dev *dev = pci_get_drvdata(pdev);
345 
346 	dev->disable(dev);
347 	pm_runtime_forbid(&pdev->dev);
348 	pm_runtime_get_noresume(&pdev->dev);
349 
350 	i2c_del_adapter(&dev->adapter);
351 	devm_free_irq(&pdev->dev, dev->irq, dev);
352 	pci_free_irq_vectors(pdev);
353 }
354 
355 static const struct pci_device_id i2_designware_pci_ids[] = {
356 	/* Medfield */
357 	{ PCI_VDEVICE(INTEL, 0x0817), medfield },
358 	{ PCI_VDEVICE(INTEL, 0x0818), medfield },
359 	{ PCI_VDEVICE(INTEL, 0x0819), medfield },
360 	{ PCI_VDEVICE(INTEL, 0x082C), medfield },
361 	{ PCI_VDEVICE(INTEL, 0x082D), medfield },
362 	{ PCI_VDEVICE(INTEL, 0x082E), medfield },
363 	/* Merrifield */
364 	{ PCI_VDEVICE(INTEL, 0x1195), merrifield },
365 	{ PCI_VDEVICE(INTEL, 0x1196), merrifield },
366 	/* Baytrail */
367 	{ PCI_VDEVICE(INTEL, 0x0F41), baytrail },
368 	{ PCI_VDEVICE(INTEL, 0x0F42), baytrail },
369 	{ PCI_VDEVICE(INTEL, 0x0F43), baytrail },
370 	{ PCI_VDEVICE(INTEL, 0x0F44), baytrail },
371 	{ PCI_VDEVICE(INTEL, 0x0F45), baytrail },
372 	{ PCI_VDEVICE(INTEL, 0x0F46), baytrail },
373 	{ PCI_VDEVICE(INTEL, 0x0F47), baytrail },
374 	/* Haswell */
375 	{ PCI_VDEVICE(INTEL, 0x9c61), haswell },
376 	{ PCI_VDEVICE(INTEL, 0x9c62), haswell },
377 	/* Braswell / Cherrytrail */
378 	{ PCI_VDEVICE(INTEL, 0x22C1), cherrytrail },
379 	{ PCI_VDEVICE(INTEL, 0x22C2), cherrytrail },
380 	{ PCI_VDEVICE(INTEL, 0x22C3), cherrytrail },
381 	{ PCI_VDEVICE(INTEL, 0x22C4), cherrytrail },
382 	{ PCI_VDEVICE(INTEL, 0x22C5), cherrytrail },
383 	{ PCI_VDEVICE(INTEL, 0x22C6), cherrytrail },
384 	{ PCI_VDEVICE(INTEL, 0x22C7), cherrytrail },
385 	/* Elkhart Lake (PSE I2C) */
386 	{ PCI_VDEVICE(INTEL, 0x4bb9), elkhartlake },
387 	{ PCI_VDEVICE(INTEL, 0x4bba), elkhartlake },
388 	{ PCI_VDEVICE(INTEL, 0x4bbb), elkhartlake },
389 	{ PCI_VDEVICE(INTEL, 0x4bbc), elkhartlake },
390 	{ PCI_VDEVICE(INTEL, 0x4bbd), elkhartlake },
391 	{ PCI_VDEVICE(INTEL, 0x4bbe), elkhartlake },
392 	{ PCI_VDEVICE(INTEL, 0x4bbf), elkhartlake },
393 	{ PCI_VDEVICE(INTEL, 0x4bc0), elkhartlake },
394 	/* AMD NAVI */
395 	{ PCI_VDEVICE(ATI,  0x7314), navi_amd },
396 	{ PCI_VDEVICE(ATI,  0x73a4), navi_amd },
397 	{ PCI_VDEVICE(ATI,  0x73e4), navi_amd },
398 	{ PCI_VDEVICE(ATI,  0x73c4), navi_amd },
399 	{ PCI_VDEVICE(ATI,  0x7444), navi_amd },
400 	{ PCI_VDEVICE(ATI,  0x7464), navi_amd },
401 	{ 0,}
402 };
403 MODULE_DEVICE_TABLE(pci, i2_designware_pci_ids);
404 
405 static struct pci_driver dw_i2c_driver = {
406 	.name		= DRIVER_NAME,
407 	.id_table	= i2_designware_pci_ids,
408 	.probe		= i2c_dw_pci_probe,
409 	.remove		= i2c_dw_pci_remove,
410 	.driver         = {
411 		.pm     = &i2c_dw_pm_ops,
412 	},
413 };
414 module_pci_driver(dw_i2c_driver);
415 
416 /* Work with hotplug and coldplug */
417 MODULE_ALIAS("i2c_designware-pci");
418 MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
419 MODULE_DESCRIPTION("Synopsys DesignWare PCI I2C bus adapter");
420 MODULE_LICENSE("GPL");
421