1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Synopsys DesignWare I2C adapter driver (master only). 4 * 5 * Based on the TI DAVINCI I2C adapter driver. 6 * 7 * Copyright (C) 2006 Texas Instruments. 8 * Copyright (C) 2007 MontaVista Software Inc. 9 * Copyright (C) 2009 Provigent Ltd. 10 */ 11 #include <linux/delay.h> 12 #include <linux/err.h> 13 #include <linux/errno.h> 14 #include <linux/export.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/i2c.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/module.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/regmap.h> 22 #include <linux/reset.h> 23 24 #include "i2c-designware-core.h" 25 26 static void i2c_dw_configure_fifo_master(struct dw_i2c_dev *dev) 27 { 28 /* Configure Tx/Rx FIFO threshold levels */ 29 regmap_write(dev->map, DW_IC_TX_TL, dev->tx_fifo_depth / 2); 30 regmap_write(dev->map, DW_IC_RX_TL, 0); 31 32 /* Configure the I2C master */ 33 regmap_write(dev->map, DW_IC_CON, dev->master_cfg); 34 } 35 36 static int i2c_dw_set_timings_master(struct dw_i2c_dev *dev) 37 { 38 const char *mode_str, *fp_str = ""; 39 u32 comp_param1; 40 u32 sda_falling_time, scl_falling_time; 41 struct i2c_timings *t = &dev->timings; 42 u32 ic_clk; 43 int ret; 44 45 ret = i2c_dw_acquire_lock(dev); 46 if (ret) 47 return ret; 48 49 ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, &comp_param1); 50 i2c_dw_release_lock(dev); 51 if (ret) 52 return ret; 53 54 /* Set standard and fast speed dividers for high/low periods */ 55 sda_falling_time = t->sda_fall_ns ?: 300; /* ns */ 56 scl_falling_time = t->scl_fall_ns ?: 300; /* ns */ 57 58 /* Calculate SCL timing parameters for standard mode if not set */ 59 if (!dev->ss_hcnt || !dev->ss_lcnt) { 60 ic_clk = i2c_dw_clk_rate(dev); 61 dev->ss_hcnt = 62 i2c_dw_scl_hcnt(ic_clk, 63 4000, /* tHD;STA = tHIGH = 4.0 us */ 64 sda_falling_time, 65 0, /* 0: DW default, 1: Ideal */ 66 0); /* No offset */ 67 dev->ss_lcnt = 68 i2c_dw_scl_lcnt(ic_clk, 69 4700, /* tLOW = 4.7 us */ 70 scl_falling_time, 71 0); /* No offset */ 72 } 73 dev_dbg(dev->dev, "Standard Mode HCNT:LCNT = %d:%d\n", 74 dev->ss_hcnt, dev->ss_lcnt); 75 76 /* 77 * Set SCL timing parameters for fast mode or fast mode plus. Only 78 * difference is the timing parameter values since the registers are 79 * the same. 80 */ 81 if (t->bus_freq_hz == 1000000) { 82 /* 83 * Check are Fast Mode Plus parameters available. Calculate 84 * SCL timing parameters for Fast Mode Plus if not set. 85 */ 86 if (dev->fp_hcnt && dev->fp_lcnt) { 87 dev->fs_hcnt = dev->fp_hcnt; 88 dev->fs_lcnt = dev->fp_lcnt; 89 } else { 90 ic_clk = i2c_dw_clk_rate(dev); 91 dev->fs_hcnt = 92 i2c_dw_scl_hcnt(ic_clk, 93 260, /* tHIGH = 260 ns */ 94 sda_falling_time, 95 0, /* DW default */ 96 0); /* No offset */ 97 dev->fs_lcnt = 98 i2c_dw_scl_lcnt(ic_clk, 99 500, /* tLOW = 500 ns */ 100 scl_falling_time, 101 0); /* No offset */ 102 } 103 fp_str = " Plus"; 104 } 105 /* 106 * Calculate SCL timing parameters for fast mode if not set. They are 107 * needed also in high speed mode. 108 */ 109 if (!dev->fs_hcnt || !dev->fs_lcnt) { 110 ic_clk = i2c_dw_clk_rate(dev); 111 dev->fs_hcnt = 112 i2c_dw_scl_hcnt(ic_clk, 113 600, /* tHD;STA = tHIGH = 0.6 us */ 114 sda_falling_time, 115 0, /* 0: DW default, 1: Ideal */ 116 0); /* No offset */ 117 dev->fs_lcnt = 118 i2c_dw_scl_lcnt(ic_clk, 119 1300, /* tLOW = 1.3 us */ 120 scl_falling_time, 121 0); /* No offset */ 122 } 123 dev_dbg(dev->dev, "Fast Mode%s HCNT:LCNT = %d:%d\n", 124 fp_str, dev->fs_hcnt, dev->fs_lcnt); 125 126 /* Check is high speed possible and fall back to fast mode if not */ 127 if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) == 128 DW_IC_CON_SPEED_HIGH) { 129 if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK) 130 != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH) { 131 dev_err(dev->dev, "High Speed not supported!\n"); 132 t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ; 133 dev->master_cfg &= ~DW_IC_CON_SPEED_MASK; 134 dev->master_cfg |= DW_IC_CON_SPEED_FAST; 135 dev->hs_hcnt = 0; 136 dev->hs_lcnt = 0; 137 } else if (!dev->hs_hcnt || !dev->hs_lcnt) { 138 ic_clk = i2c_dw_clk_rate(dev); 139 dev->hs_hcnt = 140 i2c_dw_scl_hcnt(ic_clk, 141 160, /* tHIGH = 160 ns */ 142 sda_falling_time, 143 0, /* DW default */ 144 0); /* No offset */ 145 dev->hs_lcnt = 146 i2c_dw_scl_lcnt(ic_clk, 147 320, /* tLOW = 320 ns */ 148 scl_falling_time, 149 0); /* No offset */ 150 } 151 dev_dbg(dev->dev, "High Speed Mode HCNT:LCNT = %d:%d\n", 152 dev->hs_hcnt, dev->hs_lcnt); 153 } 154 155 ret = i2c_dw_set_sda_hold(dev); 156 if (ret) 157 goto out; 158 159 switch (dev->master_cfg & DW_IC_CON_SPEED_MASK) { 160 case DW_IC_CON_SPEED_STD: 161 mode_str = "Standard Mode"; 162 break; 163 case DW_IC_CON_SPEED_HIGH: 164 mode_str = "High Speed Mode"; 165 break; 166 default: 167 mode_str = "Fast Mode"; 168 } 169 dev_dbg(dev->dev, "Bus speed: %s%s\n", mode_str, fp_str); 170 171 out: 172 return ret; 173 } 174 175 /** 176 * i2c_dw_init() - Initialize the designware I2C master hardware 177 * @dev: device private data 178 * 179 * This functions configures and enables the I2C master. 180 * This function is called during I2C init function, and in case of timeout at 181 * run time. 182 */ 183 static int i2c_dw_init_master(struct dw_i2c_dev *dev) 184 { 185 int ret; 186 187 ret = i2c_dw_acquire_lock(dev); 188 if (ret) 189 return ret; 190 191 /* Disable the adapter */ 192 __i2c_dw_disable(dev); 193 194 /* Write standard speed timing parameters */ 195 regmap_write(dev->map, DW_IC_SS_SCL_HCNT, dev->ss_hcnt); 196 regmap_write(dev->map, DW_IC_SS_SCL_LCNT, dev->ss_lcnt); 197 198 /* Write fast mode/fast mode plus timing parameters */ 199 regmap_write(dev->map, DW_IC_FS_SCL_HCNT, dev->fs_hcnt); 200 regmap_write(dev->map, DW_IC_FS_SCL_LCNT, dev->fs_lcnt); 201 202 /* Write high speed timing parameters if supported */ 203 if (dev->hs_hcnt && dev->hs_lcnt) { 204 regmap_write(dev->map, DW_IC_HS_SCL_HCNT, dev->hs_hcnt); 205 regmap_write(dev->map, DW_IC_HS_SCL_LCNT, dev->hs_lcnt); 206 } 207 208 /* Write SDA hold time if supported */ 209 if (dev->sda_hold_time) 210 regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time); 211 212 i2c_dw_configure_fifo_master(dev); 213 i2c_dw_release_lock(dev); 214 215 return 0; 216 } 217 218 static void i2c_dw_xfer_init(struct dw_i2c_dev *dev) 219 { 220 struct i2c_msg *msgs = dev->msgs; 221 u32 ic_con = 0, ic_tar = 0; 222 u32 dummy; 223 224 /* Disable the adapter */ 225 __i2c_dw_disable(dev); 226 227 /* If the slave address is ten bit address, enable 10BITADDR */ 228 if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) { 229 ic_con = DW_IC_CON_10BITADDR_MASTER; 230 /* 231 * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing 232 * mode has to be enabled via bit 12 of IC_TAR register. 233 * We set it always as I2C_DYNAMIC_TAR_UPDATE can't be 234 * detected from registers. 235 */ 236 ic_tar = DW_IC_TAR_10BITADDR_MASTER; 237 } 238 239 regmap_update_bits(dev->map, DW_IC_CON, DW_IC_CON_10BITADDR_MASTER, 240 ic_con); 241 242 /* 243 * Set the slave (target) address and enable 10-bit addressing mode 244 * if applicable. 245 */ 246 regmap_write(dev->map, DW_IC_TAR, 247 msgs[dev->msg_write_idx].addr | ic_tar); 248 249 /* Enforce disabled interrupts (due to HW issues) */ 250 i2c_dw_disable_int(dev); 251 252 /* Enable the adapter */ 253 __i2c_dw_enable(dev); 254 255 /* Dummy read to avoid the register getting stuck on Bay Trail */ 256 regmap_read(dev->map, DW_IC_ENABLE_STATUS, &dummy); 257 258 /* Clear and enable interrupts */ 259 regmap_read(dev->map, DW_IC_CLR_INTR, &dummy); 260 regmap_write(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_MASTER_MASK); 261 } 262 263 /* 264 * Initiate (and continue) low level master read/write transaction. 265 * This function is only called from i2c_dw_isr, and pumping i2c_msg 266 * messages into the tx buffer. Even if the size of i2c_msg data is 267 * longer than the size of the tx buffer, it handles everything. 268 */ 269 static void 270 i2c_dw_xfer_msg(struct dw_i2c_dev *dev) 271 { 272 struct i2c_msg *msgs = dev->msgs; 273 u32 intr_mask; 274 int tx_limit, rx_limit; 275 u32 addr = msgs[dev->msg_write_idx].addr; 276 u32 buf_len = dev->tx_buf_len; 277 u8 *buf = dev->tx_buf; 278 bool need_restart = false; 279 unsigned int flr; 280 281 intr_mask = DW_IC_INTR_MASTER_MASK; 282 283 for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) { 284 u32 flags = msgs[dev->msg_write_idx].flags; 285 286 /* 287 * If target address has changed, we need to 288 * reprogram the target address in the I2C 289 * adapter when we are done with this transfer. 290 */ 291 if (msgs[dev->msg_write_idx].addr != addr) { 292 dev_err(dev->dev, 293 "%s: invalid target address\n", __func__); 294 dev->msg_err = -EINVAL; 295 break; 296 } 297 298 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) { 299 /* new i2c_msg */ 300 buf = msgs[dev->msg_write_idx].buf; 301 buf_len = msgs[dev->msg_write_idx].len; 302 303 /* If both IC_EMPTYFIFO_HOLD_MASTER_EN and 304 * IC_RESTART_EN are set, we must manually 305 * set restart bit between messages. 306 */ 307 if ((dev->master_cfg & DW_IC_CON_RESTART_EN) && 308 (dev->msg_write_idx > 0)) 309 need_restart = true; 310 } 311 312 regmap_read(dev->map, DW_IC_TXFLR, &flr); 313 tx_limit = dev->tx_fifo_depth - flr; 314 315 regmap_read(dev->map, DW_IC_RXFLR, &flr); 316 rx_limit = dev->rx_fifo_depth - flr; 317 318 while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) { 319 u32 cmd = 0; 320 321 /* 322 * If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must 323 * manually set the stop bit. However, it cannot be 324 * detected from the registers so we set it always 325 * when writing/reading the last byte. 326 */ 327 328 /* 329 * i2c-core always sets the buffer length of 330 * I2C_FUNC_SMBUS_BLOCK_DATA to 1. The length will 331 * be adjusted when receiving the first byte. 332 * Thus we can't stop the transaction here. 333 */ 334 if (dev->msg_write_idx == dev->msgs_num - 1 && 335 buf_len == 1 && !(flags & I2C_M_RECV_LEN)) 336 cmd |= BIT(9); 337 338 if (need_restart) { 339 cmd |= BIT(10); 340 need_restart = false; 341 } 342 343 if (msgs[dev->msg_write_idx].flags & I2C_M_RD) { 344 345 /* Avoid rx buffer overrun */ 346 if (dev->rx_outstanding >= dev->rx_fifo_depth) 347 break; 348 349 regmap_write(dev->map, DW_IC_DATA_CMD, 350 cmd | 0x100); 351 rx_limit--; 352 dev->rx_outstanding++; 353 } else { 354 regmap_write(dev->map, DW_IC_DATA_CMD, 355 cmd | *buf++); 356 } 357 tx_limit--; buf_len--; 358 } 359 360 dev->tx_buf = buf; 361 dev->tx_buf_len = buf_len; 362 363 /* 364 * Because we don't know the buffer length in the 365 * I2C_FUNC_SMBUS_BLOCK_DATA case, we can't stop 366 * the transaction here. 367 */ 368 if (buf_len > 0 || flags & I2C_M_RECV_LEN) { 369 /* more bytes to be written */ 370 dev->status |= STATUS_WRITE_IN_PROGRESS; 371 break; 372 } else 373 dev->status &= ~STATUS_WRITE_IN_PROGRESS; 374 } 375 376 /* 377 * If i2c_msg index search is completed, we don't need TX_EMPTY 378 * interrupt any more. 379 */ 380 if (dev->msg_write_idx == dev->msgs_num) 381 intr_mask &= ~DW_IC_INTR_TX_EMPTY; 382 383 if (dev->msg_err) 384 intr_mask = 0; 385 386 regmap_write(dev->map, DW_IC_INTR_MASK, intr_mask); 387 } 388 389 static u8 390 i2c_dw_recv_len(struct dw_i2c_dev *dev, u8 len) 391 { 392 struct i2c_msg *msgs = dev->msgs; 393 u32 flags = msgs[dev->msg_read_idx].flags; 394 395 /* 396 * Adjust the buffer length and mask the flag 397 * after receiving the first byte. 398 */ 399 len += (flags & I2C_CLIENT_PEC) ? 2 : 1; 400 dev->tx_buf_len = len - min_t(u8, len, dev->rx_outstanding); 401 msgs[dev->msg_read_idx].len = len; 402 msgs[dev->msg_read_idx].flags &= ~I2C_M_RECV_LEN; 403 404 return len; 405 } 406 407 static void 408 i2c_dw_read(struct dw_i2c_dev *dev) 409 { 410 struct i2c_msg *msgs = dev->msgs; 411 unsigned int rx_valid; 412 413 for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) { 414 u32 len, tmp; 415 u8 *buf; 416 417 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD)) 418 continue; 419 420 if (!(dev->status & STATUS_READ_IN_PROGRESS)) { 421 len = msgs[dev->msg_read_idx].len; 422 buf = msgs[dev->msg_read_idx].buf; 423 } else { 424 len = dev->rx_buf_len; 425 buf = dev->rx_buf; 426 } 427 428 regmap_read(dev->map, DW_IC_RXFLR, &rx_valid); 429 430 for (; len > 0 && rx_valid > 0; len--, rx_valid--) { 431 u32 flags = msgs[dev->msg_read_idx].flags; 432 433 regmap_read(dev->map, DW_IC_DATA_CMD, &tmp); 434 /* Ensure length byte is a valid value */ 435 if (flags & I2C_M_RECV_LEN && 436 (tmp & DW_IC_DATA_CMD_DAT) <= I2C_SMBUS_BLOCK_MAX && tmp > 0) { 437 len = i2c_dw_recv_len(dev, tmp); 438 } 439 *buf++ = tmp; 440 dev->rx_outstanding--; 441 } 442 443 if (len > 0) { 444 dev->status |= STATUS_READ_IN_PROGRESS; 445 dev->rx_buf_len = len; 446 dev->rx_buf = buf; 447 return; 448 } else 449 dev->status &= ~STATUS_READ_IN_PROGRESS; 450 } 451 } 452 453 /* 454 * Prepare controller for a transaction and call i2c_dw_xfer_msg. 455 */ 456 static int 457 i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) 458 { 459 struct dw_i2c_dev *dev = i2c_get_adapdata(adap); 460 int ret; 461 462 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); 463 464 pm_runtime_get_sync(dev->dev); 465 466 if (dev_WARN_ONCE(dev->dev, dev->suspended, "Transfer while suspended\n")) { 467 ret = -ESHUTDOWN; 468 goto done_nolock; 469 } 470 471 reinit_completion(&dev->cmd_complete); 472 dev->msgs = msgs; 473 dev->msgs_num = num; 474 dev->cmd_err = 0; 475 dev->msg_write_idx = 0; 476 dev->msg_read_idx = 0; 477 dev->msg_err = 0; 478 dev->status = STATUS_IDLE; 479 dev->abort_source = 0; 480 dev->rx_outstanding = 0; 481 482 ret = i2c_dw_acquire_lock(dev); 483 if (ret) 484 goto done_nolock; 485 486 ret = i2c_dw_wait_bus_not_busy(dev); 487 if (ret < 0) 488 goto done; 489 490 /* Start the transfers */ 491 i2c_dw_xfer_init(dev); 492 493 /* Wait for tx to complete */ 494 if (!wait_for_completion_timeout(&dev->cmd_complete, adap->timeout)) { 495 dev_err(dev->dev, "controller timed out\n"); 496 /* i2c_dw_init implicitly disables the adapter */ 497 i2c_recover_bus(&dev->adapter); 498 i2c_dw_init_master(dev); 499 ret = -ETIMEDOUT; 500 goto done; 501 } 502 503 /* 504 * We must disable the adapter before returning and signaling the end 505 * of the current transfer. Otherwise the hardware might continue 506 * generating interrupts which in turn causes a race condition with 507 * the following transfer. Needs some more investigation if the 508 * additional interrupts are a hardware bug or this driver doesn't 509 * handle them correctly yet. 510 */ 511 __i2c_dw_disable_nowait(dev); 512 513 if (dev->msg_err) { 514 ret = dev->msg_err; 515 goto done; 516 } 517 518 /* No error */ 519 if (likely(!dev->cmd_err && !dev->status)) { 520 ret = num; 521 goto done; 522 } 523 524 /* We have an error */ 525 if (dev->cmd_err == DW_IC_ERR_TX_ABRT) { 526 ret = i2c_dw_handle_tx_abort(dev); 527 goto done; 528 } 529 530 if (dev->status) 531 dev_err(dev->dev, 532 "transfer terminated early - interrupt latency too high?\n"); 533 534 ret = -EIO; 535 536 done: 537 i2c_dw_release_lock(dev); 538 539 done_nolock: 540 pm_runtime_mark_last_busy(dev->dev); 541 pm_runtime_put_autosuspend(dev->dev); 542 543 return ret; 544 } 545 546 static const struct i2c_algorithm i2c_dw_algo = { 547 .master_xfer = i2c_dw_xfer, 548 .functionality = i2c_dw_func, 549 }; 550 551 static const struct i2c_adapter_quirks i2c_dw_quirks = { 552 .flags = I2C_AQ_NO_ZERO_LEN, 553 }; 554 555 static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev) 556 { 557 u32 stat, dummy; 558 559 /* 560 * The IC_INTR_STAT register just indicates "enabled" interrupts. 561 * The unmasked raw version of interrupt status bits is available 562 * in the IC_RAW_INTR_STAT register. 563 * 564 * That is, 565 * stat = readl(IC_INTR_STAT); 566 * equals to, 567 * stat = readl(IC_RAW_INTR_STAT) & readl(IC_INTR_MASK); 568 * 569 * The raw version might be useful for debugging purposes. 570 */ 571 regmap_read(dev->map, DW_IC_INTR_STAT, &stat); 572 573 /* 574 * Do not use the IC_CLR_INTR register to clear interrupts, or 575 * you'll miss some interrupts, triggered during the period from 576 * readl(IC_INTR_STAT) to readl(IC_CLR_INTR). 577 * 578 * Instead, use the separately-prepared IC_CLR_* registers. 579 */ 580 if (stat & DW_IC_INTR_RX_UNDER) 581 regmap_read(dev->map, DW_IC_CLR_RX_UNDER, &dummy); 582 if (stat & DW_IC_INTR_RX_OVER) 583 regmap_read(dev->map, DW_IC_CLR_RX_OVER, &dummy); 584 if (stat & DW_IC_INTR_TX_OVER) 585 regmap_read(dev->map, DW_IC_CLR_TX_OVER, &dummy); 586 if (stat & DW_IC_INTR_RD_REQ) 587 regmap_read(dev->map, DW_IC_CLR_RD_REQ, &dummy); 588 if (stat & DW_IC_INTR_TX_ABRT) { 589 /* 590 * The IC_TX_ABRT_SOURCE register is cleared whenever 591 * the IC_CLR_TX_ABRT is read. Preserve it beforehand. 592 */ 593 regmap_read(dev->map, DW_IC_TX_ABRT_SOURCE, &dev->abort_source); 594 regmap_read(dev->map, DW_IC_CLR_TX_ABRT, &dummy); 595 } 596 if (stat & DW_IC_INTR_RX_DONE) 597 regmap_read(dev->map, DW_IC_CLR_RX_DONE, &dummy); 598 if (stat & DW_IC_INTR_ACTIVITY) 599 regmap_read(dev->map, DW_IC_CLR_ACTIVITY, &dummy); 600 if (stat & DW_IC_INTR_STOP_DET) 601 regmap_read(dev->map, DW_IC_CLR_STOP_DET, &dummy); 602 if (stat & DW_IC_INTR_START_DET) 603 regmap_read(dev->map, DW_IC_CLR_START_DET, &dummy); 604 if (stat & DW_IC_INTR_GEN_CALL) 605 regmap_read(dev->map, DW_IC_CLR_GEN_CALL, &dummy); 606 607 return stat; 608 } 609 610 /* 611 * Interrupt service routine. This gets called whenever an I2C master interrupt 612 * occurs. 613 */ 614 static int i2c_dw_irq_handler_master(struct dw_i2c_dev *dev) 615 { 616 u32 stat; 617 618 stat = i2c_dw_read_clear_intrbits(dev); 619 if (stat & DW_IC_INTR_TX_ABRT) { 620 dev->cmd_err |= DW_IC_ERR_TX_ABRT; 621 dev->status = STATUS_IDLE; 622 623 /* 624 * Anytime TX_ABRT is set, the contents of the tx/rx 625 * buffers are flushed. Make sure to skip them. 626 */ 627 regmap_write(dev->map, DW_IC_INTR_MASK, 0); 628 goto tx_aborted; 629 } 630 631 if (stat & DW_IC_INTR_RX_FULL) 632 i2c_dw_read(dev); 633 634 if (stat & DW_IC_INTR_TX_EMPTY) 635 i2c_dw_xfer_msg(dev); 636 637 /* 638 * No need to modify or disable the interrupt mask here. 639 * i2c_dw_xfer_msg() will take care of it according to 640 * the current transmit status. 641 */ 642 643 tx_aborted: 644 if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err) 645 complete(&dev->cmd_complete); 646 else if (unlikely(dev->flags & ACCESS_INTR_MASK)) { 647 /* Workaround to trigger pending interrupt */ 648 regmap_read(dev->map, DW_IC_INTR_MASK, &stat); 649 i2c_dw_disable_int(dev); 650 regmap_write(dev->map, DW_IC_INTR_MASK, stat); 651 } 652 653 return 0; 654 } 655 656 static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id) 657 { 658 struct dw_i2c_dev *dev = dev_id; 659 u32 stat, enabled; 660 661 regmap_read(dev->map, DW_IC_ENABLE, &enabled); 662 regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &stat); 663 dev_dbg(dev->dev, "enabled=%#x stat=%#x\n", enabled, stat); 664 if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY)) 665 return IRQ_NONE; 666 667 i2c_dw_irq_handler_master(dev); 668 669 return IRQ_HANDLED; 670 } 671 672 void i2c_dw_configure_master(struct dw_i2c_dev *dev) 673 { 674 struct i2c_timings *t = &dev->timings; 675 676 dev->functionality = I2C_FUNC_10BIT_ADDR | DW_IC_DEFAULT_FUNCTIONALITY; 677 678 dev->master_cfg = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE | 679 DW_IC_CON_RESTART_EN; 680 681 dev->mode = DW_IC_MASTER; 682 683 switch (t->bus_freq_hz) { 684 case I2C_MAX_STANDARD_MODE_FREQ: 685 dev->master_cfg |= DW_IC_CON_SPEED_STD; 686 break; 687 case I2C_MAX_HIGH_SPEED_MODE_FREQ: 688 dev->master_cfg |= DW_IC_CON_SPEED_HIGH; 689 break; 690 default: 691 dev->master_cfg |= DW_IC_CON_SPEED_FAST; 692 } 693 } 694 EXPORT_SYMBOL_GPL(i2c_dw_configure_master); 695 696 static void i2c_dw_prepare_recovery(struct i2c_adapter *adap) 697 { 698 struct dw_i2c_dev *dev = i2c_get_adapdata(adap); 699 700 i2c_dw_disable(dev); 701 reset_control_assert(dev->rst); 702 i2c_dw_prepare_clk(dev, false); 703 } 704 705 static void i2c_dw_unprepare_recovery(struct i2c_adapter *adap) 706 { 707 struct dw_i2c_dev *dev = i2c_get_adapdata(adap); 708 709 i2c_dw_prepare_clk(dev, true); 710 reset_control_deassert(dev->rst); 711 i2c_dw_init_master(dev); 712 } 713 714 static int i2c_dw_init_recovery_info(struct dw_i2c_dev *dev) 715 { 716 struct i2c_bus_recovery_info *rinfo = &dev->rinfo; 717 struct i2c_adapter *adap = &dev->adapter; 718 struct gpio_desc *gpio; 719 720 gpio = devm_gpiod_get_optional(dev->dev, "scl", GPIOD_OUT_HIGH); 721 if (IS_ERR_OR_NULL(gpio)) 722 return PTR_ERR_OR_ZERO(gpio); 723 724 rinfo->scl_gpiod = gpio; 725 726 gpio = devm_gpiod_get_optional(dev->dev, "sda", GPIOD_IN); 727 if (IS_ERR(gpio)) 728 return PTR_ERR(gpio); 729 rinfo->sda_gpiod = gpio; 730 731 rinfo->recover_bus = i2c_generic_scl_recovery; 732 rinfo->prepare_recovery = i2c_dw_prepare_recovery; 733 rinfo->unprepare_recovery = i2c_dw_unprepare_recovery; 734 adap->bus_recovery_info = rinfo; 735 736 dev_info(dev->dev, "running with gpio recovery mode! scl%s", 737 rinfo->sda_gpiod ? ",sda" : ""); 738 739 return 0; 740 } 741 742 int i2c_dw_probe_master(struct dw_i2c_dev *dev) 743 { 744 struct i2c_adapter *adap = &dev->adapter; 745 unsigned long irq_flags; 746 int ret; 747 748 init_completion(&dev->cmd_complete); 749 750 dev->init = i2c_dw_init_master; 751 dev->disable = i2c_dw_disable; 752 dev->disable_int = i2c_dw_disable_int; 753 754 ret = i2c_dw_init_regmap(dev); 755 if (ret) 756 return ret; 757 758 ret = i2c_dw_set_timings_master(dev); 759 if (ret) 760 return ret; 761 762 ret = i2c_dw_set_fifo_size(dev); 763 if (ret) 764 return ret; 765 766 ret = dev->init(dev); 767 if (ret) 768 return ret; 769 770 snprintf(adap->name, sizeof(adap->name), 771 "Synopsys DesignWare I2C adapter"); 772 adap->retries = 3; 773 adap->algo = &i2c_dw_algo; 774 adap->quirks = &i2c_dw_quirks; 775 adap->dev.parent = dev->dev; 776 i2c_set_adapdata(adap, dev); 777 778 if (dev->flags & ACCESS_NO_IRQ_SUSPEND) { 779 irq_flags = IRQF_NO_SUSPEND; 780 } else { 781 irq_flags = IRQF_SHARED | IRQF_COND_SUSPEND; 782 } 783 784 i2c_dw_disable_int(dev); 785 ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, irq_flags, 786 dev_name(dev->dev), dev); 787 if (ret) { 788 dev_err(dev->dev, "failure requesting irq %i: %d\n", 789 dev->irq, ret); 790 return ret; 791 } 792 793 ret = i2c_dw_init_recovery_info(dev); 794 if (ret) 795 return ret; 796 797 /* 798 * Increment PM usage count during adapter registration in order to 799 * avoid possible spurious runtime suspend when adapter device is 800 * registered to the device core and immediate resume in case bus has 801 * registered I2C slaves that do I2C transfers in their probe. 802 */ 803 pm_runtime_get_noresume(dev->dev); 804 ret = i2c_add_numbered_adapter(adap); 805 if (ret) 806 dev_err(dev->dev, "failure adding adapter: %d\n", ret); 807 pm_runtime_put_noidle(dev->dev); 808 809 return ret; 810 } 811 EXPORT_SYMBOL_GPL(i2c_dw_probe_master); 812 813 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus master adapter"); 814 MODULE_LICENSE("GPL"); 815