1 /* 2 * Synopsys DesignWare I2C adapter driver (master only). 3 * 4 * Based on the TI DAVINCI I2C adapter driver. 5 * 6 * Copyright (C) 2006 Texas Instruments. 7 * Copyright (C) 2007 MontaVista Software Inc. 8 * Copyright (C) 2009 Provigent Ltd. 9 * 10 * ---------------------------------------------------------------------------- 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * ---------------------------------------------------------------------------- 22 * 23 */ 24 #include <linux/delay.h> 25 #include <linux/err.h> 26 #include <linux/errno.h> 27 #include <linux/export.h> 28 #include <linux/gpio/consumer.h> 29 #include <linux/i2c.h> 30 #include <linux/interrupt.h> 31 #include <linux/io.h> 32 #include <linux/module.h> 33 #include <linux/pm_runtime.h> 34 #include <linux/reset.h> 35 36 #include "i2c-designware-core.h" 37 38 static void i2c_dw_configure_fifo_master(struct dw_i2c_dev *dev) 39 { 40 /* Configure Tx/Rx FIFO threshold levels */ 41 dw_writel(dev, dev->tx_fifo_depth / 2, DW_IC_TX_TL); 42 dw_writel(dev, 0, DW_IC_RX_TL); 43 44 /* Configure the I2C master */ 45 dw_writel(dev, dev->master_cfg, DW_IC_CON); 46 } 47 48 /** 49 * i2c_dw_init() - Initialize the designware I2C master hardware 50 * @dev: device private data 51 * 52 * This functions configures and enables the I2C master. 53 * This function is called during I2C init function, and in case of timeout at 54 * run time. 55 */ 56 static int i2c_dw_init_master(struct dw_i2c_dev *dev) 57 { 58 u32 hcnt, lcnt; 59 u32 reg, comp_param1; 60 u32 sda_falling_time, scl_falling_time; 61 int ret; 62 63 ret = i2c_dw_acquire_lock(dev); 64 if (ret) 65 return ret; 66 67 reg = dw_readl(dev, DW_IC_COMP_TYPE); 68 if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) { 69 /* Configure register endianess access */ 70 dev->flags |= ACCESS_SWAP; 71 } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) { 72 /* Configure register access mode 16bit */ 73 dev->flags |= ACCESS_16BIT; 74 } else if (reg != DW_IC_COMP_TYPE_VALUE) { 75 dev_err(dev->dev, 76 "Unknown Synopsys component type: 0x%08x\n", reg); 77 i2c_dw_release_lock(dev); 78 return -ENODEV; 79 } 80 81 comp_param1 = dw_readl(dev, DW_IC_COMP_PARAM_1); 82 83 /* Disable the adapter */ 84 __i2c_dw_enable_and_wait(dev, false); 85 86 /* Set standard and fast speed deviders for high/low periods */ 87 88 sda_falling_time = dev->sda_falling_time ?: 300; /* ns */ 89 scl_falling_time = dev->scl_falling_time ?: 300; /* ns */ 90 91 /* Set SCL timing parameters for standard-mode */ 92 if (dev->ss_hcnt && dev->ss_lcnt) { 93 hcnt = dev->ss_hcnt; 94 lcnt = dev->ss_lcnt; 95 } else { 96 hcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev), 97 4000, /* tHD;STA = tHIGH = 4.0 us */ 98 sda_falling_time, 99 0, /* 0: DW default, 1: Ideal */ 100 0); /* No offset */ 101 lcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev), 102 4700, /* tLOW = 4.7 us */ 103 scl_falling_time, 104 0); /* No offset */ 105 } 106 dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT); 107 dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT); 108 dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); 109 110 /* Set SCL timing parameters for fast-mode or fast-mode plus */ 111 if ((dev->clk_freq == 1000000) && dev->fp_hcnt && dev->fp_lcnt) { 112 hcnt = dev->fp_hcnt; 113 lcnt = dev->fp_lcnt; 114 } else if (dev->fs_hcnt && dev->fs_lcnt) { 115 hcnt = dev->fs_hcnt; 116 lcnt = dev->fs_lcnt; 117 } else { 118 hcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev), 119 600, /* tHD;STA = tHIGH = 0.6 us */ 120 sda_falling_time, 121 0, /* 0: DW default, 1: Ideal */ 122 0); /* No offset */ 123 lcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev), 124 1300, /* tLOW = 1.3 us */ 125 scl_falling_time, 126 0); /* No offset */ 127 } 128 dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT); 129 dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT); 130 dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); 131 132 if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) == 133 DW_IC_CON_SPEED_HIGH) { 134 if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK) 135 != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH) { 136 dev_err(dev->dev, "High Speed not supported!\n"); 137 dev->master_cfg &= ~DW_IC_CON_SPEED_MASK; 138 dev->master_cfg |= DW_IC_CON_SPEED_FAST; 139 } else if (dev->hs_hcnt && dev->hs_lcnt) { 140 hcnt = dev->hs_hcnt; 141 lcnt = dev->hs_lcnt; 142 dw_writel(dev, hcnt, DW_IC_HS_SCL_HCNT); 143 dw_writel(dev, lcnt, DW_IC_HS_SCL_LCNT); 144 dev_dbg(dev->dev, "HighSpeed-mode HCNT:LCNT = %d:%d\n", 145 hcnt, lcnt); 146 } 147 } 148 149 /* Configure SDA Hold Time if required */ 150 reg = dw_readl(dev, DW_IC_COMP_VERSION); 151 if (reg >= DW_IC_SDA_HOLD_MIN_VERS) { 152 if (!dev->sda_hold_time) { 153 /* Keep previous hold time setting if no one set it */ 154 dev->sda_hold_time = dw_readl(dev, DW_IC_SDA_HOLD); 155 } 156 /* 157 * Workaround for avoiding TX arbitration lost in case I2C 158 * slave pulls SDA down "too quickly" after falling egde of 159 * SCL by enabling non-zero SDA RX hold. Specification says it 160 * extends incoming SDA low to high transition while SCL is 161 * high but it apprears to help also above issue. 162 */ 163 if (!(dev->sda_hold_time & DW_IC_SDA_HOLD_RX_MASK)) 164 dev->sda_hold_time |= 1 << DW_IC_SDA_HOLD_RX_SHIFT; 165 dw_writel(dev, dev->sda_hold_time, DW_IC_SDA_HOLD); 166 } else { 167 dev_warn(dev->dev, 168 "Hardware too old to adjust SDA hold time.\n"); 169 } 170 171 i2c_dw_configure_fifo_master(dev); 172 i2c_dw_release_lock(dev); 173 174 return 0; 175 } 176 177 static void i2c_dw_xfer_init(struct dw_i2c_dev *dev) 178 { 179 struct i2c_msg *msgs = dev->msgs; 180 u32 ic_con, ic_tar = 0; 181 182 /* Disable the adapter */ 183 __i2c_dw_enable_and_wait(dev, false); 184 185 /* If the slave address is ten bit address, enable 10BITADDR */ 186 ic_con = dw_readl(dev, DW_IC_CON); 187 if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) { 188 ic_con |= DW_IC_CON_10BITADDR_MASTER; 189 /* 190 * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing 191 * mode has to be enabled via bit 12 of IC_TAR register. 192 * We set it always as I2C_DYNAMIC_TAR_UPDATE can't be 193 * detected from registers. 194 */ 195 ic_tar = DW_IC_TAR_10BITADDR_MASTER; 196 } else { 197 ic_con &= ~DW_IC_CON_10BITADDR_MASTER; 198 } 199 200 dw_writel(dev, ic_con, DW_IC_CON); 201 202 /* 203 * Set the slave (target) address and enable 10-bit addressing mode 204 * if applicable. 205 */ 206 dw_writel(dev, msgs[dev->msg_write_idx].addr | ic_tar, DW_IC_TAR); 207 208 /* Enforce disabled interrupts (due to HW issues) */ 209 i2c_dw_disable_int(dev); 210 211 /* Enable the adapter */ 212 __i2c_dw_enable(dev, true); 213 214 /* Clear and enable interrupts */ 215 dw_readl(dev, DW_IC_CLR_INTR); 216 dw_writel(dev, DW_IC_INTR_MASTER_MASK, DW_IC_INTR_MASK); 217 } 218 219 /* 220 * Initiate (and continue) low level master read/write transaction. 221 * This function is only called from i2c_dw_isr, and pumping i2c_msg 222 * messages into the tx buffer. Even if the size of i2c_msg data is 223 * longer than the size of the tx buffer, it handles everything. 224 */ 225 static void 226 i2c_dw_xfer_msg(struct dw_i2c_dev *dev) 227 { 228 struct i2c_msg *msgs = dev->msgs; 229 u32 intr_mask; 230 int tx_limit, rx_limit; 231 u32 addr = msgs[dev->msg_write_idx].addr; 232 u32 buf_len = dev->tx_buf_len; 233 u8 *buf = dev->tx_buf; 234 bool need_restart = false; 235 236 intr_mask = DW_IC_INTR_MASTER_MASK; 237 238 for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) { 239 u32 flags = msgs[dev->msg_write_idx].flags; 240 241 /* 242 * If target address has changed, we need to 243 * reprogram the target address in the I2C 244 * adapter when we are done with this transfer. 245 */ 246 if (msgs[dev->msg_write_idx].addr != addr) { 247 dev_err(dev->dev, 248 "%s: invalid target address\n", __func__); 249 dev->msg_err = -EINVAL; 250 break; 251 } 252 253 if (msgs[dev->msg_write_idx].len == 0) { 254 dev_err(dev->dev, 255 "%s: invalid message length\n", __func__); 256 dev->msg_err = -EINVAL; 257 break; 258 } 259 260 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) { 261 /* new i2c_msg */ 262 buf = msgs[dev->msg_write_idx].buf; 263 buf_len = msgs[dev->msg_write_idx].len; 264 265 /* If both IC_EMPTYFIFO_HOLD_MASTER_EN and 266 * IC_RESTART_EN are set, we must manually 267 * set restart bit between messages. 268 */ 269 if ((dev->master_cfg & DW_IC_CON_RESTART_EN) && 270 (dev->msg_write_idx > 0)) 271 need_restart = true; 272 } 273 274 tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR); 275 rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR); 276 277 while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) { 278 u32 cmd = 0; 279 280 /* 281 * If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must 282 * manually set the stop bit. However, it cannot be 283 * detected from the registers so we set it always 284 * when writing/reading the last byte. 285 */ 286 287 /* 288 * i2c-core always sets the buffer length of 289 * I2C_FUNC_SMBUS_BLOCK_DATA to 1. The length will 290 * be adjusted when receiving the first byte. 291 * Thus we can't stop the transaction here. 292 */ 293 if (dev->msg_write_idx == dev->msgs_num - 1 && 294 buf_len == 1 && !(flags & I2C_M_RECV_LEN)) 295 cmd |= BIT(9); 296 297 if (need_restart) { 298 cmd |= BIT(10); 299 need_restart = false; 300 } 301 302 if (msgs[dev->msg_write_idx].flags & I2C_M_RD) { 303 304 /* Avoid rx buffer overrun */ 305 if (dev->rx_outstanding >= dev->rx_fifo_depth) 306 break; 307 308 dw_writel(dev, cmd | 0x100, DW_IC_DATA_CMD); 309 rx_limit--; 310 dev->rx_outstanding++; 311 } else 312 dw_writel(dev, cmd | *buf++, DW_IC_DATA_CMD); 313 tx_limit--; buf_len--; 314 } 315 316 dev->tx_buf = buf; 317 dev->tx_buf_len = buf_len; 318 319 /* 320 * Because we don't know the buffer length in the 321 * I2C_FUNC_SMBUS_BLOCK_DATA case, we can't stop 322 * the transaction here. 323 */ 324 if (buf_len > 0 || flags & I2C_M_RECV_LEN) { 325 /* more bytes to be written */ 326 dev->status |= STATUS_WRITE_IN_PROGRESS; 327 break; 328 } else 329 dev->status &= ~STATUS_WRITE_IN_PROGRESS; 330 } 331 332 /* 333 * If i2c_msg index search is completed, we don't need TX_EMPTY 334 * interrupt any more. 335 */ 336 if (dev->msg_write_idx == dev->msgs_num) 337 intr_mask &= ~DW_IC_INTR_TX_EMPTY; 338 339 if (dev->msg_err) 340 intr_mask = 0; 341 342 dw_writel(dev, intr_mask, DW_IC_INTR_MASK); 343 } 344 345 static u8 346 i2c_dw_recv_len(struct dw_i2c_dev *dev, u8 len) 347 { 348 struct i2c_msg *msgs = dev->msgs; 349 u32 flags = msgs[dev->msg_read_idx].flags; 350 351 /* 352 * Adjust the buffer length and mask the flag 353 * after receiving the first byte. 354 */ 355 len += (flags & I2C_CLIENT_PEC) ? 2 : 1; 356 dev->tx_buf_len = len - min_t(u8, len, dev->rx_outstanding); 357 msgs[dev->msg_read_idx].len = len; 358 msgs[dev->msg_read_idx].flags &= ~I2C_M_RECV_LEN; 359 360 return len; 361 } 362 363 static void 364 i2c_dw_read(struct dw_i2c_dev *dev) 365 { 366 struct i2c_msg *msgs = dev->msgs; 367 int rx_valid; 368 369 for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) { 370 u32 len; 371 u8 *buf; 372 373 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD)) 374 continue; 375 376 if (!(dev->status & STATUS_READ_IN_PROGRESS)) { 377 len = msgs[dev->msg_read_idx].len; 378 buf = msgs[dev->msg_read_idx].buf; 379 } else { 380 len = dev->rx_buf_len; 381 buf = dev->rx_buf; 382 } 383 384 rx_valid = dw_readl(dev, DW_IC_RXFLR); 385 386 for (; len > 0 && rx_valid > 0; len--, rx_valid--) { 387 u32 flags = msgs[dev->msg_read_idx].flags; 388 389 *buf = dw_readl(dev, DW_IC_DATA_CMD); 390 /* Ensure length byte is a valid value */ 391 if (flags & I2C_M_RECV_LEN && 392 *buf <= I2C_SMBUS_BLOCK_MAX && *buf > 0) { 393 len = i2c_dw_recv_len(dev, *buf); 394 } 395 buf++; 396 dev->rx_outstanding--; 397 } 398 399 if (len > 0) { 400 dev->status |= STATUS_READ_IN_PROGRESS; 401 dev->rx_buf_len = len; 402 dev->rx_buf = buf; 403 return; 404 } else 405 dev->status &= ~STATUS_READ_IN_PROGRESS; 406 } 407 } 408 409 /* 410 * Prepare controller for a transaction and call i2c_dw_xfer_msg. 411 */ 412 static int 413 i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) 414 { 415 struct dw_i2c_dev *dev = i2c_get_adapdata(adap); 416 int ret; 417 418 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); 419 420 pm_runtime_get_sync(dev->dev); 421 422 reinit_completion(&dev->cmd_complete); 423 dev->msgs = msgs; 424 dev->msgs_num = num; 425 dev->cmd_err = 0; 426 dev->msg_write_idx = 0; 427 dev->msg_read_idx = 0; 428 dev->msg_err = 0; 429 dev->status = STATUS_IDLE; 430 dev->abort_source = 0; 431 dev->rx_outstanding = 0; 432 433 ret = i2c_dw_acquire_lock(dev); 434 if (ret) 435 goto done_nolock; 436 437 ret = i2c_dw_wait_bus_not_busy(dev); 438 if (ret < 0) 439 goto done; 440 441 /* Start the transfers */ 442 i2c_dw_xfer_init(dev); 443 444 /* Wait for tx to complete */ 445 if (!wait_for_completion_timeout(&dev->cmd_complete, adap->timeout)) { 446 dev_err(dev->dev, "controller timed out\n"); 447 /* i2c_dw_init implicitly disables the adapter */ 448 i2c_recover_bus(&dev->adapter); 449 i2c_dw_init_master(dev); 450 ret = -ETIMEDOUT; 451 goto done; 452 } 453 454 /* 455 * We must disable the adapter before returning and signaling the end 456 * of the current transfer. Otherwise the hardware might continue 457 * generating interrupts which in turn causes a race condition with 458 * the following transfer. Needs some more investigation if the 459 * additional interrupts are a hardware bug or this driver doesn't 460 * handle them correctly yet. 461 */ 462 __i2c_dw_enable(dev, false); 463 464 if (dev->msg_err) { 465 ret = dev->msg_err; 466 goto done; 467 } 468 469 /* No error */ 470 if (likely(!dev->cmd_err && !dev->status)) { 471 ret = num; 472 goto done; 473 } 474 475 /* We have an error */ 476 if (dev->cmd_err == DW_IC_ERR_TX_ABRT) { 477 ret = i2c_dw_handle_tx_abort(dev); 478 goto done; 479 } 480 481 if (dev->status) 482 dev_err(dev->dev, 483 "transfer terminated early - interrupt latency too high?\n"); 484 485 ret = -EIO; 486 487 done: 488 i2c_dw_release_lock(dev); 489 490 done_nolock: 491 pm_runtime_mark_last_busy(dev->dev); 492 pm_runtime_put_autosuspend(dev->dev); 493 494 return ret; 495 } 496 497 static const struct i2c_algorithm i2c_dw_algo = { 498 .master_xfer = i2c_dw_xfer, 499 .functionality = i2c_dw_func, 500 }; 501 502 static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev) 503 { 504 u32 stat; 505 506 /* 507 * The IC_INTR_STAT register just indicates "enabled" interrupts. 508 * Ths unmasked raw version of interrupt status bits are available 509 * in the IC_RAW_INTR_STAT register. 510 * 511 * That is, 512 * stat = dw_readl(IC_INTR_STAT); 513 * equals to, 514 * stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK); 515 * 516 * The raw version might be useful for debugging purposes. 517 */ 518 stat = dw_readl(dev, DW_IC_INTR_STAT); 519 520 /* 521 * Do not use the IC_CLR_INTR register to clear interrupts, or 522 * you'll miss some interrupts, triggered during the period from 523 * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR). 524 * 525 * Instead, use the separately-prepared IC_CLR_* registers. 526 */ 527 if (stat & DW_IC_INTR_RX_UNDER) 528 dw_readl(dev, DW_IC_CLR_RX_UNDER); 529 if (stat & DW_IC_INTR_RX_OVER) 530 dw_readl(dev, DW_IC_CLR_RX_OVER); 531 if (stat & DW_IC_INTR_TX_OVER) 532 dw_readl(dev, DW_IC_CLR_TX_OVER); 533 if (stat & DW_IC_INTR_RD_REQ) 534 dw_readl(dev, DW_IC_CLR_RD_REQ); 535 if (stat & DW_IC_INTR_TX_ABRT) { 536 /* 537 * The IC_TX_ABRT_SOURCE register is cleared whenever 538 * the IC_CLR_TX_ABRT is read. Preserve it beforehand. 539 */ 540 dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE); 541 dw_readl(dev, DW_IC_CLR_TX_ABRT); 542 } 543 if (stat & DW_IC_INTR_RX_DONE) 544 dw_readl(dev, DW_IC_CLR_RX_DONE); 545 if (stat & DW_IC_INTR_ACTIVITY) 546 dw_readl(dev, DW_IC_CLR_ACTIVITY); 547 if (stat & DW_IC_INTR_STOP_DET) 548 dw_readl(dev, DW_IC_CLR_STOP_DET); 549 if (stat & DW_IC_INTR_START_DET) 550 dw_readl(dev, DW_IC_CLR_START_DET); 551 if (stat & DW_IC_INTR_GEN_CALL) 552 dw_readl(dev, DW_IC_CLR_GEN_CALL); 553 554 return stat; 555 } 556 557 /* 558 * Interrupt service routine. This gets called whenever an I2C master interrupt 559 * occurs. 560 */ 561 static int i2c_dw_irq_handler_master(struct dw_i2c_dev *dev) 562 { 563 u32 stat; 564 565 stat = i2c_dw_read_clear_intrbits(dev); 566 if (stat & DW_IC_INTR_TX_ABRT) { 567 dev->cmd_err |= DW_IC_ERR_TX_ABRT; 568 dev->status = STATUS_IDLE; 569 570 /* 571 * Anytime TX_ABRT is set, the contents of the tx/rx 572 * buffers are flushed. Make sure to skip them. 573 */ 574 dw_writel(dev, 0, DW_IC_INTR_MASK); 575 goto tx_aborted; 576 } 577 578 if (stat & DW_IC_INTR_RX_FULL) 579 i2c_dw_read(dev); 580 581 if (stat & DW_IC_INTR_TX_EMPTY) 582 i2c_dw_xfer_msg(dev); 583 584 /* 585 * No need to modify or disable the interrupt mask here. 586 * i2c_dw_xfer_msg() will take care of it according to 587 * the current transmit status. 588 */ 589 590 tx_aborted: 591 if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err) 592 complete(&dev->cmd_complete); 593 else if (unlikely(dev->flags & ACCESS_INTR_MASK)) { 594 /* Workaround to trigger pending interrupt */ 595 stat = dw_readl(dev, DW_IC_INTR_MASK); 596 i2c_dw_disable_int(dev); 597 dw_writel(dev, stat, DW_IC_INTR_MASK); 598 } 599 600 return 0; 601 } 602 603 static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id) 604 { 605 struct dw_i2c_dev *dev = dev_id; 606 u32 stat, enabled; 607 608 enabled = dw_readl(dev, DW_IC_ENABLE); 609 stat = dw_readl(dev, DW_IC_RAW_INTR_STAT); 610 dev_dbg(dev->dev, "enabled=%#x stat=%#x\n", enabled, stat); 611 if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY)) 612 return IRQ_NONE; 613 614 i2c_dw_irq_handler_master(dev); 615 616 return IRQ_HANDLED; 617 } 618 619 static void i2c_dw_prepare_recovery(struct i2c_adapter *adap) 620 { 621 struct dw_i2c_dev *dev = i2c_get_adapdata(adap); 622 623 i2c_dw_disable(dev); 624 reset_control_assert(dev->rst); 625 i2c_dw_prepare_clk(dev, false); 626 } 627 628 static void i2c_dw_unprepare_recovery(struct i2c_adapter *adap) 629 { 630 struct dw_i2c_dev *dev = i2c_get_adapdata(adap); 631 632 i2c_dw_prepare_clk(dev, true); 633 reset_control_deassert(dev->rst); 634 i2c_dw_init_master(dev); 635 } 636 637 static int i2c_dw_init_recovery_info(struct dw_i2c_dev *dev) 638 { 639 struct i2c_bus_recovery_info *rinfo = &dev->rinfo; 640 struct i2c_adapter *adap = &dev->adapter; 641 struct gpio_desc *gpio; 642 int r; 643 644 gpio = devm_gpiod_get(dev->dev, "scl", GPIOD_OUT_HIGH); 645 if (IS_ERR(gpio)) { 646 r = PTR_ERR(gpio); 647 if (r == -ENOENT) 648 return 0; 649 return r; 650 } 651 rinfo->scl_gpiod = gpio; 652 653 gpio = devm_gpiod_get_optional(dev->dev, "sda", GPIOD_IN); 654 if (IS_ERR(gpio)) 655 return PTR_ERR(gpio); 656 rinfo->sda_gpiod = gpio; 657 658 rinfo->recover_bus = i2c_generic_scl_recovery; 659 rinfo->prepare_recovery = i2c_dw_prepare_recovery; 660 rinfo->unprepare_recovery = i2c_dw_unprepare_recovery; 661 adap->bus_recovery_info = rinfo; 662 663 dev_info(dev->dev, "running with gpio recovery mode! scl%s", 664 rinfo->sda_gpiod ? ",sda" : ""); 665 666 return 0; 667 } 668 669 int i2c_dw_probe(struct dw_i2c_dev *dev) 670 { 671 struct i2c_adapter *adap = &dev->adapter; 672 unsigned long irq_flags; 673 int ret; 674 675 init_completion(&dev->cmd_complete); 676 677 dev->init = i2c_dw_init_master; 678 dev->disable = i2c_dw_disable; 679 dev->disable_int = i2c_dw_disable_int; 680 681 ret = dev->init(dev); 682 if (ret) 683 return ret; 684 685 snprintf(adap->name, sizeof(adap->name), 686 "Synopsys DesignWare I2C adapter"); 687 adap->retries = 3; 688 adap->algo = &i2c_dw_algo; 689 adap->dev.parent = dev->dev; 690 i2c_set_adapdata(adap, dev); 691 692 if (dev->pm_disabled) { 693 dev_pm_syscore_device(dev->dev, true); 694 irq_flags = IRQF_NO_SUSPEND; 695 } else { 696 irq_flags = IRQF_SHARED | IRQF_COND_SUSPEND; 697 } 698 699 i2c_dw_disable_int(dev); 700 ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, irq_flags, 701 dev_name(dev->dev), dev); 702 if (ret) { 703 dev_err(dev->dev, "failure requesting irq %i: %d\n", 704 dev->irq, ret); 705 return ret; 706 } 707 708 ret = i2c_dw_init_recovery_info(dev); 709 if (ret) 710 return ret; 711 712 /* 713 * Increment PM usage count during adapter registration in order to 714 * avoid possible spurious runtime suspend when adapter device is 715 * registered to the device core and immediate resume in case bus has 716 * registered I2C slaves that do I2C transfers in their probe. 717 */ 718 pm_runtime_get_noresume(dev->dev); 719 ret = i2c_add_numbered_adapter(adap); 720 if (ret) 721 dev_err(dev->dev, "failure adding adapter: %d\n", ret); 722 pm_runtime_put_noidle(dev->dev); 723 724 return ret; 725 } 726 EXPORT_SYMBOL_GPL(i2c_dw_probe); 727 728 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus master adapter"); 729 MODULE_LICENSE("GPL"); 730