1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Synopsys DesignWare I2C adapter driver. 4 * 5 * Based on the TI DAVINCI I2C adapter driver. 6 * 7 * Copyright (C) 2006 Texas Instruments. 8 * Copyright (C) 2007 MontaVista Software Inc. 9 * Copyright (C) 2009 Provigent Ltd. 10 */ 11 12 #include <linux/i2c.h> 13 #include <linux/pm_qos.h> 14 15 #define DW_IC_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C | \ 16 I2C_FUNC_SMBUS_BYTE | \ 17 I2C_FUNC_SMBUS_BYTE_DATA | \ 18 I2C_FUNC_SMBUS_WORD_DATA | \ 19 I2C_FUNC_SMBUS_BLOCK_DATA | \ 20 I2C_FUNC_SMBUS_I2C_BLOCK) 21 22 #define DW_IC_CON_MASTER 0x1 23 #define DW_IC_CON_SPEED_STD 0x2 24 #define DW_IC_CON_SPEED_FAST 0x4 25 #define DW_IC_CON_SPEED_HIGH 0x6 26 #define DW_IC_CON_SPEED_MASK 0x6 27 #define DW_IC_CON_10BITADDR_SLAVE 0x8 28 #define DW_IC_CON_10BITADDR_MASTER 0x10 29 #define DW_IC_CON_RESTART_EN 0x20 30 #define DW_IC_CON_SLAVE_DISABLE 0x40 31 #define DW_IC_CON_STOP_DET_IFADDRESSED 0x80 32 #define DW_IC_CON_TX_EMPTY_CTRL 0x100 33 #define DW_IC_CON_RX_FIFO_FULL_HLD_CTRL 0x200 34 35 /* 36 * Registers offset 37 */ 38 #define DW_IC_CON 0x0 39 #define DW_IC_TAR 0x4 40 #define DW_IC_SAR 0x8 41 #define DW_IC_DATA_CMD 0x10 42 #define DW_IC_SS_SCL_HCNT 0x14 43 #define DW_IC_SS_SCL_LCNT 0x18 44 #define DW_IC_FS_SCL_HCNT 0x1c 45 #define DW_IC_FS_SCL_LCNT 0x20 46 #define DW_IC_HS_SCL_HCNT 0x24 47 #define DW_IC_HS_SCL_LCNT 0x28 48 #define DW_IC_INTR_STAT 0x2c 49 #define DW_IC_INTR_MASK 0x30 50 #define DW_IC_RAW_INTR_STAT 0x34 51 #define DW_IC_RX_TL 0x38 52 #define DW_IC_TX_TL 0x3c 53 #define DW_IC_CLR_INTR 0x40 54 #define DW_IC_CLR_RX_UNDER 0x44 55 #define DW_IC_CLR_RX_OVER 0x48 56 #define DW_IC_CLR_TX_OVER 0x4c 57 #define DW_IC_CLR_RD_REQ 0x50 58 #define DW_IC_CLR_TX_ABRT 0x54 59 #define DW_IC_CLR_RX_DONE 0x58 60 #define DW_IC_CLR_ACTIVITY 0x5c 61 #define DW_IC_CLR_STOP_DET 0x60 62 #define DW_IC_CLR_START_DET 0x64 63 #define DW_IC_CLR_GEN_CALL 0x68 64 #define DW_IC_ENABLE 0x6c 65 #define DW_IC_STATUS 0x70 66 #define DW_IC_TXFLR 0x74 67 #define DW_IC_RXFLR 0x78 68 #define DW_IC_SDA_HOLD 0x7c 69 #define DW_IC_TX_ABRT_SOURCE 0x80 70 #define DW_IC_ENABLE_STATUS 0x9c 71 #define DW_IC_CLR_RESTART_DET 0xa8 72 #define DW_IC_COMP_PARAM_1 0xf4 73 #define DW_IC_COMP_VERSION 0xf8 74 #define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A 75 #define DW_IC_COMP_TYPE 0xfc 76 #define DW_IC_COMP_TYPE_VALUE 0x44570140 77 78 #define DW_IC_INTR_RX_UNDER 0x001 79 #define DW_IC_INTR_RX_OVER 0x002 80 #define DW_IC_INTR_RX_FULL 0x004 81 #define DW_IC_INTR_TX_OVER 0x008 82 #define DW_IC_INTR_TX_EMPTY 0x010 83 #define DW_IC_INTR_RD_REQ 0x020 84 #define DW_IC_INTR_TX_ABRT 0x040 85 #define DW_IC_INTR_RX_DONE 0x080 86 #define DW_IC_INTR_ACTIVITY 0x100 87 #define DW_IC_INTR_STOP_DET 0x200 88 #define DW_IC_INTR_START_DET 0x400 89 #define DW_IC_INTR_GEN_CALL 0x800 90 #define DW_IC_INTR_RESTART_DET 0x1000 91 92 #define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \ 93 DW_IC_INTR_TX_ABRT | \ 94 DW_IC_INTR_STOP_DET) 95 #define DW_IC_INTR_MASTER_MASK (DW_IC_INTR_DEFAULT_MASK | \ 96 DW_IC_INTR_TX_EMPTY) 97 #define DW_IC_INTR_SLAVE_MASK (DW_IC_INTR_DEFAULT_MASK | \ 98 DW_IC_INTR_RX_DONE | \ 99 DW_IC_INTR_RX_UNDER | \ 100 DW_IC_INTR_RD_REQ) 101 102 #define DW_IC_STATUS_ACTIVITY 0x1 103 #define DW_IC_STATUS_TFE BIT(2) 104 #define DW_IC_STATUS_MASTER_ACTIVITY BIT(5) 105 #define DW_IC_STATUS_SLAVE_ACTIVITY BIT(6) 106 107 #define DW_IC_SDA_HOLD_RX_SHIFT 16 108 #define DW_IC_SDA_HOLD_RX_MASK GENMASK(23, DW_IC_SDA_HOLD_RX_SHIFT) 109 110 #define DW_IC_ERR_TX_ABRT 0x1 111 112 #define DW_IC_TAR_10BITADDR_MASTER BIT(12) 113 114 #define DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH (BIT(2) | BIT(3)) 115 #define DW_IC_COMP_PARAM_1_SPEED_MODE_MASK GENMASK(3, 2) 116 117 /* 118 * status codes 119 */ 120 #define STATUS_IDLE 0x0 121 #define STATUS_WRITE_IN_PROGRESS 0x1 122 #define STATUS_READ_IN_PROGRESS 0x2 123 124 #define TIMEOUT 20 /* ms */ 125 126 /* 127 * operation modes 128 */ 129 #define DW_IC_MASTER 0 130 #define DW_IC_SLAVE 1 131 132 /* 133 * Hardware abort codes from the DW_IC_TX_ABRT_SOURCE register 134 * 135 * Only expected abort codes are listed here 136 * refer to the datasheet for the full list 137 */ 138 #define ABRT_7B_ADDR_NOACK 0 139 #define ABRT_10ADDR1_NOACK 1 140 #define ABRT_10ADDR2_NOACK 2 141 #define ABRT_TXDATA_NOACK 3 142 #define ABRT_GCALL_NOACK 4 143 #define ABRT_GCALL_READ 5 144 #define ABRT_SBYTE_ACKDET 7 145 #define ABRT_SBYTE_NORSTRT 9 146 #define ABRT_10B_RD_NORSTRT 10 147 #define ABRT_MASTER_DIS 11 148 #define ARB_LOST 12 149 #define ABRT_SLAVE_FLUSH_TXFIFO 13 150 #define ABRT_SLAVE_ARBLOST 14 151 #define ABRT_SLAVE_RD_INTX 15 152 153 #define DW_IC_TX_ABRT_7B_ADDR_NOACK (1UL << ABRT_7B_ADDR_NOACK) 154 #define DW_IC_TX_ABRT_10ADDR1_NOACK (1UL << ABRT_10ADDR1_NOACK) 155 #define DW_IC_TX_ABRT_10ADDR2_NOACK (1UL << ABRT_10ADDR2_NOACK) 156 #define DW_IC_TX_ABRT_TXDATA_NOACK (1UL << ABRT_TXDATA_NOACK) 157 #define DW_IC_TX_ABRT_GCALL_NOACK (1UL << ABRT_GCALL_NOACK) 158 #define DW_IC_TX_ABRT_GCALL_READ (1UL << ABRT_GCALL_READ) 159 #define DW_IC_TX_ABRT_SBYTE_ACKDET (1UL << ABRT_SBYTE_ACKDET) 160 #define DW_IC_TX_ABRT_SBYTE_NORSTRT (1UL << ABRT_SBYTE_NORSTRT) 161 #define DW_IC_TX_ABRT_10B_RD_NORSTRT (1UL << ABRT_10B_RD_NORSTRT) 162 #define DW_IC_TX_ABRT_MASTER_DIS (1UL << ABRT_MASTER_DIS) 163 #define DW_IC_TX_ARB_LOST (1UL << ARB_LOST) 164 #define DW_IC_RX_ABRT_SLAVE_RD_INTX (1UL << ABRT_SLAVE_RD_INTX) 165 #define DW_IC_RX_ABRT_SLAVE_ARBLOST (1UL << ABRT_SLAVE_ARBLOST) 166 #define DW_IC_RX_ABRT_SLAVE_FLUSH_TXFIFO (1UL << ABRT_SLAVE_FLUSH_TXFIFO) 167 168 #define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \ 169 DW_IC_TX_ABRT_10ADDR1_NOACK | \ 170 DW_IC_TX_ABRT_10ADDR2_NOACK | \ 171 DW_IC_TX_ABRT_TXDATA_NOACK | \ 172 DW_IC_TX_ABRT_GCALL_NOACK) 173 174 175 /** 176 * struct dw_i2c_dev - private i2c-designware data 177 * @dev: driver model device node 178 * @base: IO registers pointer 179 * @cmd_complete: tx completion indicator 180 * @clk: input reference clock 181 * @slave: represent an I2C slave device 182 * @cmd_err: run time hadware error code 183 * @msgs: points to an array of messages currently being transferred 184 * @msgs_num: the number of elements in msgs 185 * @msg_write_idx: the element index of the current tx message in the msgs 186 * array 187 * @tx_buf_len: the length of the current tx buffer 188 * @tx_buf: the current tx buffer 189 * @msg_read_idx: the element index of the current rx message in the msgs 190 * array 191 * @rx_buf_len: the length of the current rx buffer 192 * @rx_buf: the current rx buffer 193 * @msg_err: error status of the current transfer 194 * @status: i2c master status, one of STATUS_* 195 * @abort_source: copy of the TX_ABRT_SOURCE register 196 * @irq: interrupt number for the i2c master 197 * @adapter: i2c subsystem adapter node 198 * @slave_cfg: configuration for the slave device 199 * @tx_fifo_depth: depth of the hardware tx fifo 200 * @rx_fifo_depth: depth of the hardware rx fifo 201 * @rx_outstanding: current master-rx elements in tx fifo 202 * @timings: bus clock frequency, SDA hold and other timings 203 * @sda_hold_time: SDA hold value 204 * @ss_hcnt: standard speed HCNT value 205 * @ss_lcnt: standard speed LCNT value 206 * @fs_hcnt: fast speed HCNT value 207 * @fs_lcnt: fast speed LCNT value 208 * @fp_hcnt: fast plus HCNT value 209 * @fp_lcnt: fast plus LCNT value 210 * @hs_hcnt: high speed HCNT value 211 * @hs_lcnt: high speed LCNT value 212 * @pm_qos: pm_qos_request used while holding a hardware lock on the bus 213 * @acquire_lock: function to acquire a hardware lock on the bus 214 * @release_lock: function to release a hardware lock on the bus 215 * @pm_disabled: true if power-management should be disabled for this i2c-bus 216 * @disable: function to disable the controller 217 * @disable_int: function to disable all interrupts 218 * @init: function to initialize the I2C hardware 219 * @mode: operation mode - DW_IC_MASTER or DW_IC_SLAVE 220 * 221 * HCNT and LCNT parameters can be used if the platform knows more accurate 222 * values than the one computed based only on the input clock frequency. 223 * Leave them to be %0 if not used. 224 */ 225 struct dw_i2c_dev { 226 struct device *dev; 227 void __iomem *base; 228 struct completion cmd_complete; 229 struct clk *clk; 230 struct reset_control *rst; 231 struct i2c_client *slave; 232 u32 (*get_clk_rate_khz) (struct dw_i2c_dev *dev); 233 struct dw_pci_controller *controller; 234 int cmd_err; 235 struct i2c_msg *msgs; 236 int msgs_num; 237 int msg_write_idx; 238 u32 tx_buf_len; 239 u8 *tx_buf; 240 int msg_read_idx; 241 u32 rx_buf_len; 242 u8 *rx_buf; 243 int msg_err; 244 unsigned int status; 245 u32 abort_source; 246 int irq; 247 u32 flags; 248 struct i2c_adapter adapter; 249 u32 functionality; 250 u32 master_cfg; 251 u32 slave_cfg; 252 unsigned int tx_fifo_depth; 253 unsigned int rx_fifo_depth; 254 int rx_outstanding; 255 struct i2c_timings timings; 256 u32 sda_hold_time; 257 u16 ss_hcnt; 258 u16 ss_lcnt; 259 u16 fs_hcnt; 260 u16 fs_lcnt; 261 u16 fp_hcnt; 262 u16 fp_lcnt; 263 u16 hs_hcnt; 264 u16 hs_lcnt; 265 struct pm_qos_request pm_qos; 266 int (*acquire_lock)(struct dw_i2c_dev *dev); 267 void (*release_lock)(struct dw_i2c_dev *dev); 268 bool pm_disabled; 269 void (*disable)(struct dw_i2c_dev *dev); 270 void (*disable_int)(struct dw_i2c_dev *dev); 271 int (*init)(struct dw_i2c_dev *dev); 272 int mode; 273 struct i2c_bus_recovery_info rinfo; 274 }; 275 276 #define ACCESS_SWAP 0x00000001 277 #define ACCESS_16BIT 0x00000002 278 #define ACCESS_INTR_MASK 0x00000004 279 280 #define MODEL_CHERRYTRAIL 0x00000100 281 282 u32 dw_readl(struct dw_i2c_dev *dev, int offset); 283 void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset); 284 int i2c_dw_set_reg_access(struct dw_i2c_dev *dev); 285 u32 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset); 286 u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset); 287 int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev); 288 unsigned long i2c_dw_clk_rate(struct dw_i2c_dev *dev); 289 int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare); 290 int i2c_dw_acquire_lock(struct dw_i2c_dev *dev); 291 void i2c_dw_release_lock(struct dw_i2c_dev *dev); 292 int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev); 293 int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev); 294 u32 i2c_dw_func(struct i2c_adapter *adap); 295 void i2c_dw_disable(struct dw_i2c_dev *dev); 296 void i2c_dw_disable_int(struct dw_i2c_dev *dev); 297 298 static inline void __i2c_dw_enable(struct dw_i2c_dev *dev) 299 { 300 dw_writel(dev, 1, DW_IC_ENABLE); 301 } 302 303 static inline void __i2c_dw_disable_nowait(struct dw_i2c_dev *dev) 304 { 305 dw_writel(dev, 0, DW_IC_ENABLE); 306 } 307 308 void __i2c_dw_disable(struct dw_i2c_dev *dev); 309 310 extern u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev); 311 extern int i2c_dw_probe(struct dw_i2c_dev *dev); 312 #if IS_ENABLED(CONFIG_I2C_DESIGNWARE_SLAVE) 313 extern int i2c_dw_probe_slave(struct dw_i2c_dev *dev); 314 #else 315 static inline int i2c_dw_probe_slave(struct dw_i2c_dev *dev) { return -EINVAL; } 316 #endif 317 318 #if IS_ENABLED(CONFIG_I2C_DESIGNWARE_BAYTRAIL) 319 extern int i2c_dw_probe_lock_support(struct dw_i2c_dev *dev); 320 extern void i2c_dw_remove_lock_support(struct dw_i2c_dev *dev); 321 #else 322 static inline int i2c_dw_probe_lock_support(struct dw_i2c_dev *dev) { return 0; } 323 static inline void i2c_dw_remove_lock_support(struct dw_i2c_dev *dev) {} 324 #endif 325