1 /* 2 * Synopsys DesignWare I2C adapter driver (master only). 3 * 4 * Based on the TI DAVINCI I2C adapter driver. 5 * 6 * Copyright (C) 2006 Texas Instruments. 7 * Copyright (C) 2007 MontaVista Software Inc. 8 * Copyright (C) 2009 Provigent Ltd. 9 * 10 * ---------------------------------------------------------------------------- 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * ---------------------------------------------------------------------------- 22 * 23 */ 24 25 #include <linux/i2c.h> 26 #include <linux/pm_qos.h> 27 28 #define DW_IC_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C | \ 29 I2C_FUNC_SMBUS_BYTE | \ 30 I2C_FUNC_SMBUS_BYTE_DATA | \ 31 I2C_FUNC_SMBUS_WORD_DATA | \ 32 I2C_FUNC_SMBUS_BLOCK_DATA | \ 33 I2C_FUNC_SMBUS_I2C_BLOCK) 34 35 #define DW_IC_CON_MASTER 0x1 36 #define DW_IC_CON_SPEED_STD 0x2 37 #define DW_IC_CON_SPEED_FAST 0x4 38 #define DW_IC_CON_SPEED_HIGH 0x6 39 #define DW_IC_CON_SPEED_MASK 0x6 40 #define DW_IC_CON_10BITADDR_MASTER 0x10 41 #define DW_IC_CON_RESTART_EN 0x20 42 #define DW_IC_CON_SLAVE_DISABLE 0x40 43 44 45 /** 46 * struct dw_i2c_dev - private i2c-designware data 47 * @dev: driver model device node 48 * @base: IO registers pointer 49 * @cmd_complete: tx completion indicator 50 * @clk: input reference clock 51 * @cmd_err: run time hadware error code 52 * @msgs: points to an array of messages currently being transfered 53 * @msgs_num: the number of elements in msgs 54 * @msg_write_idx: the element index of the current tx message in the msgs 55 * array 56 * @tx_buf_len: the length of the current tx buffer 57 * @tx_buf: the current tx buffer 58 * @msg_read_idx: the element index of the current rx message in the msgs 59 * array 60 * @rx_buf_len: the length of the current rx buffer 61 * @rx_buf: the current rx buffer 62 * @msg_err: error status of the current transfer 63 * @status: i2c master status, one of STATUS_* 64 * @abort_source: copy of the TX_ABRT_SOURCE register 65 * @irq: interrupt number for the i2c master 66 * @adapter: i2c subsystem adapter node 67 * @tx_fifo_depth: depth of the hardware tx fifo 68 * @rx_fifo_depth: depth of the hardware rx fifo 69 * @rx_outstanding: current master-rx elements in tx fifo 70 * @clk_freq: bus clock frequency 71 * @ss_hcnt: standard speed HCNT value 72 * @ss_lcnt: standard speed LCNT value 73 * @fs_hcnt: fast speed HCNT value 74 * @fs_lcnt: fast speed LCNT value 75 * @fp_hcnt: fast plus HCNT value 76 * @fp_lcnt: fast plus LCNT value 77 * @hs_hcnt: high speed HCNT value 78 * @hs_lcnt: high speed LCNT value 79 * @pm_qos: pm_qos_request used while holding a hardware lock on the bus 80 * @acquire_lock: function to acquire a hardware lock on the bus 81 * @release_lock: function to release a hardware lock on the bus 82 * @pm_disabled: true if power-management should be disabled for this i2c-bus 83 * 84 * HCNT and LCNT parameters can be used if the platform knows more accurate 85 * values than the one computed based only on the input clock frequency. 86 * Leave them to be %0 if not used. 87 */ 88 struct dw_i2c_dev { 89 struct device *dev; 90 void __iomem *base; 91 struct completion cmd_complete; 92 struct clk *clk; 93 struct reset_control *rst; 94 u32 (*get_clk_rate_khz) (struct dw_i2c_dev *dev); 95 struct dw_pci_controller *controller; 96 int cmd_err; 97 struct i2c_msg *msgs; 98 int msgs_num; 99 int msg_write_idx; 100 u32 tx_buf_len; 101 u8 *tx_buf; 102 int msg_read_idx; 103 u32 rx_buf_len; 104 u8 *rx_buf; 105 int msg_err; 106 unsigned int status; 107 u32 abort_source; 108 int irq; 109 u32 flags; 110 struct i2c_adapter adapter; 111 u32 functionality; 112 u32 master_cfg; 113 unsigned int tx_fifo_depth; 114 unsigned int rx_fifo_depth; 115 int rx_outstanding; 116 u32 clk_freq; 117 u32 sda_hold_time; 118 u32 sda_falling_time; 119 u32 scl_falling_time; 120 u16 ss_hcnt; 121 u16 ss_lcnt; 122 u16 fs_hcnt; 123 u16 fs_lcnt; 124 u16 fp_hcnt; 125 u16 fp_lcnt; 126 u16 hs_hcnt; 127 u16 hs_lcnt; 128 struct pm_qos_request pm_qos; 129 int (*acquire_lock)(struct dw_i2c_dev *dev); 130 void (*release_lock)(struct dw_i2c_dev *dev); 131 bool pm_disabled; 132 }; 133 134 #define ACCESS_SWAP 0x00000001 135 #define ACCESS_16BIT 0x00000002 136 #define ACCESS_INTR_MASK 0x00000004 137 138 #define MODEL_CHERRYTRAIL 0x00000100 139 140 extern int i2c_dw_init(struct dw_i2c_dev *dev); 141 extern void i2c_dw_disable(struct dw_i2c_dev *dev); 142 extern void i2c_dw_disable_int(struct dw_i2c_dev *dev); 143 extern u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev); 144 extern int i2c_dw_probe(struct dw_i2c_dev *dev); 145 146 #if IS_ENABLED(CONFIG_I2C_DESIGNWARE_BAYTRAIL) 147 extern int i2c_dw_probe_lock_support(struct dw_i2c_dev *dev); 148 extern void i2c_dw_remove_lock_support(struct dw_i2c_dev *dev); 149 #else 150 static inline int i2c_dw_probe_lock_support(struct dw_i2c_dev *dev) { return 0; } 151 static inline void i2c_dw_remove_lock_support(struct dw_i2c_dev *dev) {} 152 #endif 153