1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Synopsys DesignWare I2C adapter driver. 4 * 5 * Based on the TI DAVINCI I2C adapter driver. 6 * 7 * Copyright (C) 2006 Texas Instruments. 8 * Copyright (C) 2007 MontaVista Software Inc. 9 * Copyright (C) 2009 Provigent Ltd. 10 */ 11 12 #include <linux/bits.h> 13 #include <linux/compiler_types.h> 14 #include <linux/completion.h> 15 #include <linux/dev_printk.h> 16 #include <linux/errno.h> 17 #include <linux/i2c.h> 18 #include <linux/regmap.h> 19 #include <linux/types.h> 20 21 #define DW_IC_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C | \ 22 I2C_FUNC_SMBUS_BYTE | \ 23 I2C_FUNC_SMBUS_BYTE_DATA | \ 24 I2C_FUNC_SMBUS_WORD_DATA | \ 25 I2C_FUNC_SMBUS_BLOCK_DATA | \ 26 I2C_FUNC_SMBUS_I2C_BLOCK) 27 28 #define DW_IC_CON_MASTER BIT(0) 29 #define DW_IC_CON_SPEED_STD (1 << 1) 30 #define DW_IC_CON_SPEED_FAST (2 << 1) 31 #define DW_IC_CON_SPEED_HIGH (3 << 1) 32 #define DW_IC_CON_SPEED_MASK GENMASK(2, 1) 33 #define DW_IC_CON_10BITADDR_SLAVE BIT(3) 34 #define DW_IC_CON_10BITADDR_MASTER BIT(4) 35 #define DW_IC_CON_RESTART_EN BIT(5) 36 #define DW_IC_CON_SLAVE_DISABLE BIT(6) 37 #define DW_IC_CON_STOP_DET_IFADDRESSED BIT(7) 38 #define DW_IC_CON_TX_EMPTY_CTRL BIT(8) 39 #define DW_IC_CON_RX_FIFO_FULL_HLD_CTRL BIT(9) 40 41 #define DW_IC_DATA_CMD_DAT GENMASK(7, 0) 42 43 /* 44 * Registers offset 45 */ 46 #define DW_IC_CON 0x00 47 #define DW_IC_TAR 0x04 48 #define DW_IC_SAR 0x08 49 #define DW_IC_DATA_CMD 0x10 50 #define DW_IC_SS_SCL_HCNT 0x14 51 #define DW_IC_SS_SCL_LCNT 0x18 52 #define DW_IC_FS_SCL_HCNT 0x1c 53 #define DW_IC_FS_SCL_LCNT 0x20 54 #define DW_IC_HS_SCL_HCNT 0x24 55 #define DW_IC_HS_SCL_LCNT 0x28 56 #define DW_IC_INTR_STAT 0x2c 57 #define DW_IC_INTR_MASK 0x30 58 #define DW_IC_RAW_INTR_STAT 0x34 59 #define DW_IC_RX_TL 0x38 60 #define DW_IC_TX_TL 0x3c 61 #define DW_IC_CLR_INTR 0x40 62 #define DW_IC_CLR_RX_UNDER 0x44 63 #define DW_IC_CLR_RX_OVER 0x48 64 #define DW_IC_CLR_TX_OVER 0x4c 65 #define DW_IC_CLR_RD_REQ 0x50 66 #define DW_IC_CLR_TX_ABRT 0x54 67 #define DW_IC_CLR_RX_DONE 0x58 68 #define DW_IC_CLR_ACTIVITY 0x5c 69 #define DW_IC_CLR_STOP_DET 0x60 70 #define DW_IC_CLR_START_DET 0x64 71 #define DW_IC_CLR_GEN_CALL 0x68 72 #define DW_IC_ENABLE 0x6c 73 #define DW_IC_STATUS 0x70 74 #define DW_IC_TXFLR 0x74 75 #define DW_IC_RXFLR 0x78 76 #define DW_IC_SDA_HOLD 0x7c 77 #define DW_IC_TX_ABRT_SOURCE 0x80 78 #define DW_IC_ENABLE_STATUS 0x9c 79 #define DW_IC_CLR_RESTART_DET 0xa8 80 #define DW_IC_COMP_PARAM_1 0xf4 81 #define DW_IC_COMP_VERSION 0xf8 82 #define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A 83 #define DW_IC_COMP_TYPE 0xfc 84 #define DW_IC_COMP_TYPE_VALUE 0x44570140 85 86 #define DW_IC_INTR_RX_UNDER BIT(0) 87 #define DW_IC_INTR_RX_OVER BIT(1) 88 #define DW_IC_INTR_RX_FULL BIT(2) 89 #define DW_IC_INTR_TX_OVER BIT(3) 90 #define DW_IC_INTR_TX_EMPTY BIT(4) 91 #define DW_IC_INTR_RD_REQ BIT(5) 92 #define DW_IC_INTR_TX_ABRT BIT(6) 93 #define DW_IC_INTR_RX_DONE BIT(7) 94 #define DW_IC_INTR_ACTIVITY BIT(8) 95 #define DW_IC_INTR_STOP_DET BIT(9) 96 #define DW_IC_INTR_START_DET BIT(10) 97 #define DW_IC_INTR_GEN_CALL BIT(11) 98 #define DW_IC_INTR_RESTART_DET BIT(12) 99 100 #define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \ 101 DW_IC_INTR_TX_ABRT | \ 102 DW_IC_INTR_STOP_DET) 103 #define DW_IC_INTR_MASTER_MASK (DW_IC_INTR_DEFAULT_MASK | \ 104 DW_IC_INTR_TX_EMPTY) 105 #define DW_IC_INTR_SLAVE_MASK (DW_IC_INTR_DEFAULT_MASK | \ 106 DW_IC_INTR_RX_DONE | \ 107 DW_IC_INTR_RX_UNDER | \ 108 DW_IC_INTR_RD_REQ) 109 110 #define DW_IC_STATUS_ACTIVITY BIT(0) 111 #define DW_IC_STATUS_TFE BIT(2) 112 #define DW_IC_STATUS_MASTER_ACTIVITY BIT(5) 113 #define DW_IC_STATUS_SLAVE_ACTIVITY BIT(6) 114 115 #define DW_IC_SDA_HOLD_RX_SHIFT 16 116 #define DW_IC_SDA_HOLD_RX_MASK GENMASK(23, 16) 117 118 #define DW_IC_ERR_TX_ABRT 0x1 119 120 #define DW_IC_TAR_10BITADDR_MASTER BIT(12) 121 122 #define DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH (BIT(2) | BIT(3)) 123 #define DW_IC_COMP_PARAM_1_SPEED_MODE_MASK GENMASK(3, 2) 124 125 /* 126 * status codes 127 */ 128 #define STATUS_IDLE 0x0 129 #define STATUS_ACTIVE 0x1 130 #define STATUS_WRITE_IN_PROGRESS 0x2 131 #define STATUS_READ_IN_PROGRESS 0x4 132 133 /* 134 * operation modes 135 */ 136 #define DW_IC_MASTER 0 137 #define DW_IC_SLAVE 1 138 139 /* 140 * Hardware abort codes from the DW_IC_TX_ABRT_SOURCE register 141 * 142 * Only expected abort codes are listed here 143 * refer to the datasheet for the full list 144 */ 145 #define ABRT_7B_ADDR_NOACK 0 146 #define ABRT_10ADDR1_NOACK 1 147 #define ABRT_10ADDR2_NOACK 2 148 #define ABRT_TXDATA_NOACK 3 149 #define ABRT_GCALL_NOACK 4 150 #define ABRT_GCALL_READ 5 151 #define ABRT_SBYTE_ACKDET 7 152 #define ABRT_SBYTE_NORSTRT 9 153 #define ABRT_10B_RD_NORSTRT 10 154 #define ABRT_MASTER_DIS 11 155 #define ARB_LOST 12 156 #define ABRT_SLAVE_FLUSH_TXFIFO 13 157 #define ABRT_SLAVE_ARBLOST 14 158 #define ABRT_SLAVE_RD_INTX 15 159 160 #define DW_IC_TX_ABRT_7B_ADDR_NOACK BIT(ABRT_7B_ADDR_NOACK) 161 #define DW_IC_TX_ABRT_10ADDR1_NOACK BIT(ABRT_10ADDR1_NOACK) 162 #define DW_IC_TX_ABRT_10ADDR2_NOACK BIT(ABRT_10ADDR2_NOACK) 163 #define DW_IC_TX_ABRT_TXDATA_NOACK BIT(ABRT_TXDATA_NOACK) 164 #define DW_IC_TX_ABRT_GCALL_NOACK BIT(ABRT_GCALL_NOACK) 165 #define DW_IC_TX_ABRT_GCALL_READ BIT(ABRT_GCALL_READ) 166 #define DW_IC_TX_ABRT_SBYTE_ACKDET BIT(ABRT_SBYTE_ACKDET) 167 #define DW_IC_TX_ABRT_SBYTE_NORSTRT BIT(ABRT_SBYTE_NORSTRT) 168 #define DW_IC_TX_ABRT_10B_RD_NORSTRT BIT(ABRT_10B_RD_NORSTRT) 169 #define DW_IC_TX_ABRT_MASTER_DIS BIT(ABRT_MASTER_DIS) 170 #define DW_IC_TX_ARB_LOST BIT(ARB_LOST) 171 #define DW_IC_RX_ABRT_SLAVE_RD_INTX BIT(ABRT_SLAVE_RD_INTX) 172 #define DW_IC_RX_ABRT_SLAVE_ARBLOST BIT(ABRT_SLAVE_ARBLOST) 173 #define DW_IC_RX_ABRT_SLAVE_FLUSH_TXFIFO BIT(ABRT_SLAVE_FLUSH_TXFIFO) 174 175 #define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \ 176 DW_IC_TX_ABRT_10ADDR1_NOACK | \ 177 DW_IC_TX_ABRT_10ADDR2_NOACK | \ 178 DW_IC_TX_ABRT_TXDATA_NOACK | \ 179 DW_IC_TX_ABRT_GCALL_NOACK) 180 181 struct clk; 182 struct device; 183 struct reset_control; 184 185 /** 186 * struct dw_i2c_dev - private i2c-designware data 187 * @dev: driver model device node 188 * @map: IO registers map 189 * @sysmap: System controller registers map 190 * @base: IO registers pointer 191 * @ext: Extended IO registers pointer 192 * @cmd_complete: tx completion indicator 193 * @clk: input reference clock 194 * @pclk: clock required to access the registers 195 * @rst: optional reset for the controller 196 * @slave: represent an I2C slave device 197 * @get_clk_rate_khz: callback to retrieve IP specific bus speed 198 * @cmd_err: run time hadware error code 199 * @msgs: points to an array of messages currently being transferred 200 * @msgs_num: the number of elements in msgs 201 * @msg_write_idx: the element index of the current tx message in the msgs array 202 * @tx_buf_len: the length of the current tx buffer 203 * @tx_buf: the current tx buffer 204 * @msg_read_idx: the element index of the current rx message in the msgs array 205 * @rx_buf_len: the length of the current rx buffer 206 * @rx_buf: the current rx buffer 207 * @msg_err: error status of the current transfer 208 * @status: i2c master status, one of STATUS_* 209 * @abort_source: copy of the TX_ABRT_SOURCE register 210 * @irq: interrupt number for the i2c master 211 * @flags: platform specific flags like type of IO accessors or model 212 * @adapter: i2c subsystem adapter node 213 * @functionality: I2C_FUNC_* ORed bits to reflect what controller does support 214 * @master_cfg: configuration for the master device 215 * @slave_cfg: configuration for the slave device 216 * @tx_fifo_depth: depth of the hardware tx fifo 217 * @rx_fifo_depth: depth of the hardware rx fifo 218 * @rx_outstanding: current master-rx elements in tx fifo 219 * @timings: bus clock frequency, SDA hold and other timings 220 * @sda_hold_time: SDA hold value 221 * @ss_hcnt: standard speed HCNT value 222 * @ss_lcnt: standard speed LCNT value 223 * @fs_hcnt: fast speed HCNT value 224 * @fs_lcnt: fast speed LCNT value 225 * @fp_hcnt: fast plus HCNT value 226 * @fp_lcnt: fast plus LCNT value 227 * @hs_hcnt: high speed HCNT value 228 * @hs_lcnt: high speed LCNT value 229 * @acquire_lock: function to acquire a hardware lock on the bus 230 * @release_lock: function to release a hardware lock on the bus 231 * @semaphore_idx: Index of table with semaphore type attached to the bus. It's 232 * -1 if there is no semaphore. 233 * @shared_with_punit: true if this bus is shared with the SoCs PUNIT 234 * @disable: function to disable the controller 235 * @disable_int: function to disable all interrupts 236 * @init: function to initialize the I2C hardware 237 * @set_sda_hold_time: callback to retrieve IP specific SDA hold timing 238 * @mode: operation mode - DW_IC_MASTER or DW_IC_SLAVE 239 * @rinfo: I²C GPIO recovery information 240 * 241 * HCNT and LCNT parameters can be used if the platform knows more accurate 242 * values than the one computed based only on the input clock frequency. 243 * Leave them to be %0 if not used. 244 */ 245 struct dw_i2c_dev { 246 struct device *dev; 247 struct regmap *map; 248 struct regmap *sysmap; 249 void __iomem *base; 250 void __iomem *ext; 251 struct completion cmd_complete; 252 struct clk *clk; 253 struct clk *pclk; 254 struct reset_control *rst; 255 struct i2c_client *slave; 256 u32 (*get_clk_rate_khz) (struct dw_i2c_dev *dev); 257 int cmd_err; 258 struct i2c_msg *msgs; 259 int msgs_num; 260 int msg_write_idx; 261 u32 tx_buf_len; 262 u8 *tx_buf; 263 int msg_read_idx; 264 u32 rx_buf_len; 265 u8 *rx_buf; 266 int msg_err; 267 unsigned int status; 268 u32 abort_source; 269 int irq; 270 u32 flags; 271 struct i2c_adapter adapter; 272 u32 functionality; 273 u32 master_cfg; 274 u32 slave_cfg; 275 unsigned int tx_fifo_depth; 276 unsigned int rx_fifo_depth; 277 int rx_outstanding; 278 struct i2c_timings timings; 279 u32 sda_hold_time; 280 u16 ss_hcnt; 281 u16 ss_lcnt; 282 u16 fs_hcnt; 283 u16 fs_lcnt; 284 u16 fp_hcnt; 285 u16 fp_lcnt; 286 u16 hs_hcnt; 287 u16 hs_lcnt; 288 int (*acquire_lock)(void); 289 void (*release_lock)(void); 290 int semaphore_idx; 291 bool shared_with_punit; 292 void (*disable)(struct dw_i2c_dev *dev); 293 void (*disable_int)(struct dw_i2c_dev *dev); 294 int (*init)(struct dw_i2c_dev *dev); 295 int (*set_sda_hold_time)(struct dw_i2c_dev *dev); 296 int mode; 297 struct i2c_bus_recovery_info rinfo; 298 }; 299 300 #define ACCESS_INTR_MASK BIT(0) 301 #define ACCESS_NO_IRQ_SUSPEND BIT(1) 302 #define ARBITRATION_SEMAPHORE BIT(2) 303 304 #define MODEL_MSCC_OCELOT BIT(8) 305 #define MODEL_BAIKAL_BT1 BIT(9) 306 #define MODEL_AMD_NAVI_GPU BIT(10) 307 #define MODEL_MASK GENMASK(11, 8) 308 309 /* 310 * Enable UCSI interrupt by writing 0xd at register 311 * offset 0x474 specified in hardware specification. 312 */ 313 #define AMD_UCSI_INTR_REG 0x474 314 #define AMD_UCSI_INTR_EN 0xd 315 316 struct i2c_dw_semaphore_callbacks { 317 int (*probe)(struct dw_i2c_dev *dev); 318 void (*remove)(struct dw_i2c_dev *dev); 319 }; 320 321 int i2c_dw_init_regmap(struct dw_i2c_dev *dev); 322 u32 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset); 323 u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset); 324 int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev); 325 unsigned long i2c_dw_clk_rate(struct dw_i2c_dev *dev); 326 int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare); 327 int i2c_dw_acquire_lock(struct dw_i2c_dev *dev); 328 void i2c_dw_release_lock(struct dw_i2c_dev *dev); 329 int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev); 330 int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev); 331 int i2c_dw_set_fifo_size(struct dw_i2c_dev *dev); 332 u32 i2c_dw_func(struct i2c_adapter *adap); 333 void i2c_dw_disable(struct dw_i2c_dev *dev); 334 void i2c_dw_disable_int(struct dw_i2c_dev *dev); 335 336 static inline void __i2c_dw_enable(struct dw_i2c_dev *dev) 337 { 338 dev->status |= STATUS_ACTIVE; 339 regmap_write(dev->map, DW_IC_ENABLE, 1); 340 } 341 342 static inline void __i2c_dw_disable_nowait(struct dw_i2c_dev *dev) 343 { 344 regmap_write(dev->map, DW_IC_ENABLE, 0); 345 dev->status &= ~STATUS_ACTIVE; 346 } 347 348 void __i2c_dw_disable(struct dw_i2c_dev *dev); 349 350 extern void i2c_dw_configure_master(struct dw_i2c_dev *dev); 351 extern int i2c_dw_probe_master(struct dw_i2c_dev *dev); 352 353 #if IS_ENABLED(CONFIG_I2C_DESIGNWARE_SLAVE) 354 extern void i2c_dw_configure_slave(struct dw_i2c_dev *dev); 355 extern int i2c_dw_probe_slave(struct dw_i2c_dev *dev); 356 #else 357 static inline void i2c_dw_configure_slave(struct dw_i2c_dev *dev) { } 358 static inline int i2c_dw_probe_slave(struct dw_i2c_dev *dev) { return -EINVAL; } 359 #endif 360 361 static inline int i2c_dw_probe(struct dw_i2c_dev *dev) 362 { 363 switch (dev->mode) { 364 case DW_IC_SLAVE: 365 return i2c_dw_probe_slave(dev); 366 case DW_IC_MASTER: 367 return i2c_dw_probe_master(dev); 368 default: 369 dev_err(dev->dev, "Wrong operation mode: %d\n", dev->mode); 370 return -EINVAL; 371 } 372 } 373 374 static inline void i2c_dw_configure(struct dw_i2c_dev *dev) 375 { 376 if (i2c_detect_slave_mode(dev->dev)) 377 i2c_dw_configure_slave(dev); 378 else 379 i2c_dw_configure_master(dev); 380 } 381 382 #if IS_ENABLED(CONFIG_I2C_DESIGNWARE_BAYTRAIL) 383 int i2c_dw_baytrail_probe_lock_support(struct dw_i2c_dev *dev); 384 #endif 385 386 #if IS_ENABLED(CONFIG_I2C_DESIGNWARE_AMDPSP) 387 int i2c_dw_amdpsp_probe_lock_support(struct dw_i2c_dev *dev); 388 void i2c_dw_amdpsp_remove_lock_support(struct dw_i2c_dev *dev); 389 #endif 390 391 int i2c_dw_validate_speed(struct dw_i2c_dev *dev); 392 void i2c_dw_adjust_bus_speed(struct dw_i2c_dev *dev); 393 394 #if IS_ENABLED(CONFIG_ACPI) 395 int i2c_dw_acpi_configure(struct device *device); 396 #else 397 static inline int i2c_dw_acpi_configure(struct device *device) { return -ENODEV; } 398 #endif 399