1 /*
2  * Synopsys DesignWare I2C adapter driver (master only).
3  *
4  * Based on the TI DAVINCI I2C adapter driver.
5  *
6  * Copyright (C) 2006 Texas Instruments.
7  * Copyright (C) 2007 MontaVista Software Inc.
8  * Copyright (C) 2009 Provigent Ltd.
9  *
10  * ----------------------------------------------------------------------------
11  *
12  * This program is free software; you can redistribute it and/or modify
13  * it under the terms of the GNU General Public License as published by
14  * the Free Software Foundation; either version 2 of the License, or
15  * (at your option) any later version.
16  *
17  * This program is distributed in the hope that it will be useful,
18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
20  * GNU General Public License for more details.
21  * ----------------------------------------------------------------------------
22  *
23  */
24 
25 
26 #define DW_IC_CON_MASTER		0x1
27 #define DW_IC_CON_SPEED_STD		0x2
28 #define DW_IC_CON_SPEED_FAST		0x4
29 #define DW_IC_CON_10BITADDR_MASTER	0x10
30 #define DW_IC_CON_RESTART_EN		0x20
31 #define DW_IC_CON_SLAVE_DISABLE		0x40
32 
33 
34 /**
35  * struct dw_i2c_dev - private i2c-designware data
36  * @dev: driver model device node
37  * @base: IO registers pointer
38  * @cmd_complete: tx completion indicator
39  * @lock: protect this struct and IO registers
40  * @clk: input reference clock
41  * @cmd_err: run time hadware error code
42  * @msgs: points to an array of messages currently being transfered
43  * @msgs_num: the number of elements in msgs
44  * @msg_write_idx: the element index of the current tx message in the msgs
45  *	array
46  * @tx_buf_len: the length of the current tx buffer
47  * @tx_buf: the current tx buffer
48  * @msg_read_idx: the element index of the current rx message in the msgs
49  *	array
50  * @rx_buf_len: the length of the current rx buffer
51  * @rx_buf: the current rx buffer
52  * @msg_err: error status of the current transfer
53  * @status: i2c master status, one of STATUS_*
54  * @abort_source: copy of the TX_ABRT_SOURCE register
55  * @irq: interrupt number for the i2c master
56  * @adapter: i2c subsystem adapter node
57  * @tx_fifo_depth: depth of the hardware tx fifo
58  * @rx_fifo_depth: depth of the hardware rx fifo
59  * @rx_outstanding: current master-rx elements in tx fifo
60  * @ss_hcnt: standard speed HCNT value
61  * @ss_lcnt: standard speed LCNT value
62  * @fs_hcnt: fast speed HCNT value
63  * @fs_lcnt: fast speed LCNT value
64  * @acquire_lock: function to acquire a hardware lock on the bus
65  * @release_lock: function to release a hardware lock on the bus
66  * @pm_runtime_disabled: true if pm runtime is disabled
67  *
68  * HCNT and LCNT parameters can be used if the platform knows more accurate
69  * values than the one computed based only on the input clock frequency.
70  * Leave them to be %0 if not used.
71  */
72 struct dw_i2c_dev {
73 	struct device		*dev;
74 	void __iomem		*base;
75 	struct completion	cmd_complete;
76 	struct mutex		lock;
77 	struct clk		*clk;
78 	u32			(*get_clk_rate_khz) (struct dw_i2c_dev *dev);
79 	struct dw_pci_controller *controller;
80 	int			cmd_err;
81 	struct i2c_msg		*msgs;
82 	int			msgs_num;
83 	int			msg_write_idx;
84 	u32			tx_buf_len;
85 	u8			*tx_buf;
86 	int			msg_read_idx;
87 	u32			rx_buf_len;
88 	u8			*rx_buf;
89 	int			msg_err;
90 	unsigned int		status;
91 	u32			abort_source;
92 	int			irq;
93 	u32			accessor_flags;
94 	struct i2c_adapter	adapter;
95 	u32			functionality;
96 	u32			master_cfg;
97 	unsigned int		tx_fifo_depth;
98 	unsigned int		rx_fifo_depth;
99 	int			rx_outstanding;
100 	u32			sda_hold_time;
101 	u32			sda_falling_time;
102 	u32			scl_falling_time;
103 	u16			ss_hcnt;
104 	u16			ss_lcnt;
105 	u16			fs_hcnt;
106 	u16			fs_lcnt;
107 	int			(*acquire_lock)(struct dw_i2c_dev *dev);
108 	void			(*release_lock)(struct dw_i2c_dev *dev);
109 	bool			pm_runtime_disabled;
110 };
111 
112 #define ACCESS_SWAP		0x00000001
113 #define ACCESS_16BIT		0x00000002
114 
115 extern u32 dw_readl(struct dw_i2c_dev *dev, int offset);
116 extern void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset);
117 extern int i2c_dw_init(struct dw_i2c_dev *dev);
118 extern int i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
119 		int num);
120 extern u32 i2c_dw_func(struct i2c_adapter *adap);
121 extern irqreturn_t i2c_dw_isr(int this_irq, void *dev_id);
122 extern void i2c_dw_enable(struct dw_i2c_dev *dev);
123 extern u32 i2c_dw_is_enabled(struct dw_i2c_dev *dev);
124 extern void i2c_dw_disable(struct dw_i2c_dev *dev);
125 extern void i2c_dw_clear_int(struct dw_i2c_dev *dev);
126 extern void i2c_dw_disable_int(struct dw_i2c_dev *dev);
127 extern u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev);
128 
129 #if IS_ENABLED(CONFIG_I2C_DESIGNWARE_BAYTRAIL)
130 extern int i2c_dw_eval_lock_support(struct dw_i2c_dev *dev);
131 #else
132 static inline int i2c_dw_eval_lock_support(struct dw_i2c_dev *dev) { return 0; }
133 #endif
134