1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Synopsys DesignWare I2C adapter driver. 4 * 5 * Based on the TI DAVINCI I2C adapter driver. 6 * 7 * Copyright (C) 2006 Texas Instruments. 8 * Copyright (C) 2007 MontaVista Software Inc. 9 * Copyright (C) 2009 Provigent Ltd. 10 */ 11 12 #include <linux/i2c.h> 13 14 #define DW_IC_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C | \ 15 I2C_FUNC_SMBUS_BYTE | \ 16 I2C_FUNC_SMBUS_BYTE_DATA | \ 17 I2C_FUNC_SMBUS_WORD_DATA | \ 18 I2C_FUNC_SMBUS_BLOCK_DATA | \ 19 I2C_FUNC_SMBUS_I2C_BLOCK) 20 21 #define DW_IC_CON_MASTER 0x1 22 #define DW_IC_CON_SPEED_STD 0x2 23 #define DW_IC_CON_SPEED_FAST 0x4 24 #define DW_IC_CON_SPEED_HIGH 0x6 25 #define DW_IC_CON_SPEED_MASK 0x6 26 #define DW_IC_CON_10BITADDR_SLAVE 0x8 27 #define DW_IC_CON_10BITADDR_MASTER 0x10 28 #define DW_IC_CON_RESTART_EN 0x20 29 #define DW_IC_CON_SLAVE_DISABLE 0x40 30 #define DW_IC_CON_STOP_DET_IFADDRESSED 0x80 31 #define DW_IC_CON_TX_EMPTY_CTRL 0x100 32 #define DW_IC_CON_RX_FIFO_FULL_HLD_CTRL 0x200 33 34 /* 35 * Registers offset 36 */ 37 #define DW_IC_CON 0x0 38 #define DW_IC_TAR 0x4 39 #define DW_IC_SAR 0x8 40 #define DW_IC_DATA_CMD 0x10 41 #define DW_IC_SS_SCL_HCNT 0x14 42 #define DW_IC_SS_SCL_LCNT 0x18 43 #define DW_IC_FS_SCL_HCNT 0x1c 44 #define DW_IC_FS_SCL_LCNT 0x20 45 #define DW_IC_HS_SCL_HCNT 0x24 46 #define DW_IC_HS_SCL_LCNT 0x28 47 #define DW_IC_INTR_STAT 0x2c 48 #define DW_IC_INTR_MASK 0x30 49 #define DW_IC_RAW_INTR_STAT 0x34 50 #define DW_IC_RX_TL 0x38 51 #define DW_IC_TX_TL 0x3c 52 #define DW_IC_CLR_INTR 0x40 53 #define DW_IC_CLR_RX_UNDER 0x44 54 #define DW_IC_CLR_RX_OVER 0x48 55 #define DW_IC_CLR_TX_OVER 0x4c 56 #define DW_IC_CLR_RD_REQ 0x50 57 #define DW_IC_CLR_TX_ABRT 0x54 58 #define DW_IC_CLR_RX_DONE 0x58 59 #define DW_IC_CLR_ACTIVITY 0x5c 60 #define DW_IC_CLR_STOP_DET 0x60 61 #define DW_IC_CLR_START_DET 0x64 62 #define DW_IC_CLR_GEN_CALL 0x68 63 #define DW_IC_ENABLE 0x6c 64 #define DW_IC_STATUS 0x70 65 #define DW_IC_TXFLR 0x74 66 #define DW_IC_RXFLR 0x78 67 #define DW_IC_SDA_HOLD 0x7c 68 #define DW_IC_TX_ABRT_SOURCE 0x80 69 #define DW_IC_ENABLE_STATUS 0x9c 70 #define DW_IC_CLR_RESTART_DET 0xa8 71 #define DW_IC_COMP_PARAM_1 0xf4 72 #define DW_IC_COMP_VERSION 0xf8 73 #define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A 74 #define DW_IC_COMP_TYPE 0xfc 75 #define DW_IC_COMP_TYPE_VALUE 0x44570140 76 77 #define DW_IC_INTR_RX_UNDER 0x001 78 #define DW_IC_INTR_RX_OVER 0x002 79 #define DW_IC_INTR_RX_FULL 0x004 80 #define DW_IC_INTR_TX_OVER 0x008 81 #define DW_IC_INTR_TX_EMPTY 0x010 82 #define DW_IC_INTR_RD_REQ 0x020 83 #define DW_IC_INTR_TX_ABRT 0x040 84 #define DW_IC_INTR_RX_DONE 0x080 85 #define DW_IC_INTR_ACTIVITY 0x100 86 #define DW_IC_INTR_STOP_DET 0x200 87 #define DW_IC_INTR_START_DET 0x400 88 #define DW_IC_INTR_GEN_CALL 0x800 89 #define DW_IC_INTR_RESTART_DET 0x1000 90 91 #define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \ 92 DW_IC_INTR_TX_ABRT | \ 93 DW_IC_INTR_STOP_DET) 94 #define DW_IC_INTR_MASTER_MASK (DW_IC_INTR_DEFAULT_MASK | \ 95 DW_IC_INTR_TX_EMPTY) 96 #define DW_IC_INTR_SLAVE_MASK (DW_IC_INTR_DEFAULT_MASK | \ 97 DW_IC_INTR_RX_DONE | \ 98 DW_IC_INTR_RX_UNDER | \ 99 DW_IC_INTR_RD_REQ) 100 101 #define DW_IC_STATUS_ACTIVITY 0x1 102 #define DW_IC_STATUS_TFE BIT(2) 103 #define DW_IC_STATUS_MASTER_ACTIVITY BIT(5) 104 #define DW_IC_STATUS_SLAVE_ACTIVITY BIT(6) 105 106 #define DW_IC_SDA_HOLD_RX_SHIFT 16 107 #define DW_IC_SDA_HOLD_RX_MASK GENMASK(23, DW_IC_SDA_HOLD_RX_SHIFT) 108 109 #define DW_IC_ERR_TX_ABRT 0x1 110 111 #define DW_IC_TAR_10BITADDR_MASTER BIT(12) 112 113 #define DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH (BIT(2) | BIT(3)) 114 #define DW_IC_COMP_PARAM_1_SPEED_MODE_MASK GENMASK(3, 2) 115 116 /* 117 * status codes 118 */ 119 #define STATUS_IDLE 0x0 120 #define STATUS_WRITE_IN_PROGRESS 0x1 121 #define STATUS_READ_IN_PROGRESS 0x2 122 123 #define TIMEOUT 20 /* ms */ 124 125 /* 126 * operation modes 127 */ 128 #define DW_IC_MASTER 0 129 #define DW_IC_SLAVE 1 130 131 /* 132 * Hardware abort codes from the DW_IC_TX_ABRT_SOURCE register 133 * 134 * Only expected abort codes are listed here 135 * refer to the datasheet for the full list 136 */ 137 #define ABRT_7B_ADDR_NOACK 0 138 #define ABRT_10ADDR1_NOACK 1 139 #define ABRT_10ADDR2_NOACK 2 140 #define ABRT_TXDATA_NOACK 3 141 #define ABRT_GCALL_NOACK 4 142 #define ABRT_GCALL_READ 5 143 #define ABRT_SBYTE_ACKDET 7 144 #define ABRT_SBYTE_NORSTRT 9 145 #define ABRT_10B_RD_NORSTRT 10 146 #define ABRT_MASTER_DIS 11 147 #define ARB_LOST 12 148 #define ABRT_SLAVE_FLUSH_TXFIFO 13 149 #define ABRT_SLAVE_ARBLOST 14 150 #define ABRT_SLAVE_RD_INTX 15 151 152 #define DW_IC_TX_ABRT_7B_ADDR_NOACK (1UL << ABRT_7B_ADDR_NOACK) 153 #define DW_IC_TX_ABRT_10ADDR1_NOACK (1UL << ABRT_10ADDR1_NOACK) 154 #define DW_IC_TX_ABRT_10ADDR2_NOACK (1UL << ABRT_10ADDR2_NOACK) 155 #define DW_IC_TX_ABRT_TXDATA_NOACK (1UL << ABRT_TXDATA_NOACK) 156 #define DW_IC_TX_ABRT_GCALL_NOACK (1UL << ABRT_GCALL_NOACK) 157 #define DW_IC_TX_ABRT_GCALL_READ (1UL << ABRT_GCALL_READ) 158 #define DW_IC_TX_ABRT_SBYTE_ACKDET (1UL << ABRT_SBYTE_ACKDET) 159 #define DW_IC_TX_ABRT_SBYTE_NORSTRT (1UL << ABRT_SBYTE_NORSTRT) 160 #define DW_IC_TX_ABRT_10B_RD_NORSTRT (1UL << ABRT_10B_RD_NORSTRT) 161 #define DW_IC_TX_ABRT_MASTER_DIS (1UL << ABRT_MASTER_DIS) 162 #define DW_IC_TX_ARB_LOST (1UL << ARB_LOST) 163 #define DW_IC_RX_ABRT_SLAVE_RD_INTX (1UL << ABRT_SLAVE_RD_INTX) 164 #define DW_IC_RX_ABRT_SLAVE_ARBLOST (1UL << ABRT_SLAVE_ARBLOST) 165 #define DW_IC_RX_ABRT_SLAVE_FLUSH_TXFIFO (1UL << ABRT_SLAVE_FLUSH_TXFIFO) 166 167 #define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \ 168 DW_IC_TX_ABRT_10ADDR1_NOACK | \ 169 DW_IC_TX_ABRT_10ADDR2_NOACK | \ 170 DW_IC_TX_ABRT_TXDATA_NOACK | \ 171 DW_IC_TX_ABRT_GCALL_NOACK) 172 173 174 /** 175 * struct dw_i2c_dev - private i2c-designware data 176 * @dev: driver model device node 177 * @base: IO registers pointer 178 * @cmd_complete: tx completion indicator 179 * @clk: input reference clock 180 * @slave: represent an I2C slave device 181 * @cmd_err: run time hadware error code 182 * @msgs: points to an array of messages currently being transferred 183 * @msgs_num: the number of elements in msgs 184 * @msg_write_idx: the element index of the current tx message in the msgs 185 * array 186 * @tx_buf_len: the length of the current tx buffer 187 * @tx_buf: the current tx buffer 188 * @msg_read_idx: the element index of the current rx message in the msgs 189 * array 190 * @rx_buf_len: the length of the current rx buffer 191 * @rx_buf: the current rx buffer 192 * @msg_err: error status of the current transfer 193 * @status: i2c master status, one of STATUS_* 194 * @abort_source: copy of the TX_ABRT_SOURCE register 195 * @irq: interrupt number for the i2c master 196 * @adapter: i2c subsystem adapter node 197 * @slave_cfg: configuration for the slave device 198 * @tx_fifo_depth: depth of the hardware tx fifo 199 * @rx_fifo_depth: depth of the hardware rx fifo 200 * @rx_outstanding: current master-rx elements in tx fifo 201 * @timings: bus clock frequency, SDA hold and other timings 202 * @sda_hold_time: SDA hold value 203 * @ss_hcnt: standard speed HCNT value 204 * @ss_lcnt: standard speed LCNT value 205 * @fs_hcnt: fast speed HCNT value 206 * @fs_lcnt: fast speed LCNT value 207 * @fp_hcnt: fast plus HCNT value 208 * @fp_lcnt: fast plus LCNT value 209 * @hs_hcnt: high speed HCNT value 210 * @hs_lcnt: high speed LCNT value 211 * @acquire_lock: function to acquire a hardware lock on the bus 212 * @release_lock: function to release a hardware lock on the bus 213 * @shared_with_punit: true if this bus is shared with the SoCs PUNIT 214 * @disable: function to disable the controller 215 * @disable_int: function to disable all interrupts 216 * @init: function to initialize the I2C hardware 217 * @mode: operation mode - DW_IC_MASTER or DW_IC_SLAVE 218 * 219 * HCNT and LCNT parameters can be used if the platform knows more accurate 220 * values than the one computed based only on the input clock frequency. 221 * Leave them to be %0 if not used. 222 */ 223 struct dw_i2c_dev { 224 struct device *dev; 225 void __iomem *base; 226 void __iomem *ext; 227 struct completion cmd_complete; 228 struct clk *clk; 229 struct reset_control *rst; 230 struct i2c_client *slave; 231 u32 (*get_clk_rate_khz) (struct dw_i2c_dev *dev); 232 struct dw_pci_controller *controller; 233 int cmd_err; 234 struct i2c_msg *msgs; 235 int msgs_num; 236 int msg_write_idx; 237 u32 tx_buf_len; 238 u8 *tx_buf; 239 int msg_read_idx; 240 u32 rx_buf_len; 241 u8 *rx_buf; 242 int msg_err; 243 unsigned int status; 244 u32 abort_source; 245 int irq; 246 u32 flags; 247 struct i2c_adapter adapter; 248 u32 functionality; 249 u32 master_cfg; 250 u32 slave_cfg; 251 unsigned int tx_fifo_depth; 252 unsigned int rx_fifo_depth; 253 int rx_outstanding; 254 struct i2c_timings timings; 255 u32 sda_hold_time; 256 u16 ss_hcnt; 257 u16 ss_lcnt; 258 u16 fs_hcnt; 259 u16 fs_lcnt; 260 u16 fp_hcnt; 261 u16 fp_lcnt; 262 u16 hs_hcnt; 263 u16 hs_lcnt; 264 int (*acquire_lock)(void); 265 void (*release_lock)(void); 266 bool shared_with_punit; 267 void (*disable)(struct dw_i2c_dev *dev); 268 void (*disable_int)(struct dw_i2c_dev *dev); 269 int (*init)(struct dw_i2c_dev *dev); 270 int (*set_sda_hold_time)(struct dw_i2c_dev *dev); 271 int mode; 272 struct i2c_bus_recovery_info rinfo; 273 }; 274 275 #define ACCESS_SWAP 0x00000001 276 #define ACCESS_16BIT 0x00000002 277 #define ACCESS_INTR_MASK 0x00000004 278 #define ACCESS_NO_IRQ_SUSPEND 0x00000008 279 280 #define MODEL_CHERRYTRAIL 0x00000100 281 #define MODEL_MSCC_OCELOT 0x00000200 282 #define MODEL_MASK 0x00000f00 283 284 u32 dw_readl(struct dw_i2c_dev *dev, int offset); 285 void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset); 286 int i2c_dw_set_reg_access(struct dw_i2c_dev *dev); 287 u32 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset); 288 u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset); 289 int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev); 290 unsigned long i2c_dw_clk_rate(struct dw_i2c_dev *dev); 291 int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare); 292 int i2c_dw_acquire_lock(struct dw_i2c_dev *dev); 293 void i2c_dw_release_lock(struct dw_i2c_dev *dev); 294 int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev); 295 int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev); 296 u32 i2c_dw_func(struct i2c_adapter *adap); 297 void i2c_dw_disable(struct dw_i2c_dev *dev); 298 void i2c_dw_disable_int(struct dw_i2c_dev *dev); 299 300 static inline void __i2c_dw_enable(struct dw_i2c_dev *dev) 301 { 302 dw_writel(dev, 1, DW_IC_ENABLE); 303 } 304 305 static inline void __i2c_dw_disable_nowait(struct dw_i2c_dev *dev) 306 { 307 dw_writel(dev, 0, DW_IC_ENABLE); 308 } 309 310 void __i2c_dw_disable(struct dw_i2c_dev *dev); 311 312 extern u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev); 313 extern int i2c_dw_probe(struct dw_i2c_dev *dev); 314 #if IS_ENABLED(CONFIG_I2C_DESIGNWARE_SLAVE) 315 extern int i2c_dw_probe_slave(struct dw_i2c_dev *dev); 316 #else 317 static inline int i2c_dw_probe_slave(struct dw_i2c_dev *dev) { return -EINVAL; } 318 #endif 319 320 #if IS_ENABLED(CONFIG_I2C_DESIGNWARE_BAYTRAIL) 321 extern int i2c_dw_probe_lock_support(struct dw_i2c_dev *dev); 322 #else 323 static inline int i2c_dw_probe_lock_support(struct dw_i2c_dev *dev) { return 0; } 324 #endif 325