1 /* 2 * Synopsys DesignWare I2C adapter driver. 3 * 4 * Based on the TI DAVINCI I2C adapter driver. 5 * 6 * Copyright (C) 2006 Texas Instruments. 7 * Copyright (C) 2007 MontaVista Software Inc. 8 * Copyright (C) 2009 Provigent Ltd. 9 * 10 * ---------------------------------------------------------------------------- 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * ---------------------------------------------------------------------------- 22 * 23 */ 24 #include <linux/clk.h> 25 #include <linux/delay.h> 26 #include <linux/export.h> 27 #include <linux/errno.h> 28 #include <linux/err.h> 29 #include <linux/i2c.h> 30 #include <linux/interrupt.h> 31 #include <linux/io.h> 32 #include <linux/module.h> 33 #include <linux/pm_runtime.h> 34 35 #include "i2c-designware-core.h" 36 37 static char *abort_sources[] = { 38 [ABRT_7B_ADDR_NOACK] = 39 "slave address not acknowledged (7bit mode)", 40 [ABRT_10ADDR1_NOACK] = 41 "first address byte not acknowledged (10bit mode)", 42 [ABRT_10ADDR2_NOACK] = 43 "second address byte not acknowledged (10bit mode)", 44 [ABRT_TXDATA_NOACK] = 45 "data not acknowledged", 46 [ABRT_GCALL_NOACK] = 47 "no acknowledgement for a general call", 48 [ABRT_GCALL_READ] = 49 "read after general call", 50 [ABRT_SBYTE_ACKDET] = 51 "start byte acknowledged", 52 [ABRT_SBYTE_NORSTRT] = 53 "trying to send start byte when restart is disabled", 54 [ABRT_10B_RD_NORSTRT] = 55 "trying to read when restart is disabled (10bit mode)", 56 [ABRT_MASTER_DIS] = 57 "trying to use disabled adapter", 58 [ARB_LOST] = 59 "lost arbitration", 60 [ABRT_SLAVE_FLUSH_TXFIFO] = 61 "read command so flush old data in the TX FIFO", 62 [ABRT_SLAVE_ARBLOST] = 63 "slave lost the bus while transmitting data to a remote master", 64 [ABRT_SLAVE_RD_INTX] = 65 "incorrect slave-transmitter mode configuration", 66 }; 67 68 u32 dw_readl(struct dw_i2c_dev *dev, int offset) 69 { 70 u32 value; 71 72 if (dev->flags & ACCESS_16BIT) 73 value = readw_relaxed(dev->base + offset) | 74 (readw_relaxed(dev->base + offset + 2) << 16); 75 else 76 value = readl_relaxed(dev->base + offset); 77 78 if (dev->flags & ACCESS_SWAP) 79 return swab32(value); 80 else 81 return value; 82 } 83 84 void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset) 85 { 86 if (dev->flags & ACCESS_SWAP) 87 b = swab32(b); 88 89 if (dev->flags & ACCESS_16BIT) { 90 writew_relaxed((u16)b, dev->base + offset); 91 writew_relaxed((u16)(b >> 16), dev->base + offset + 2); 92 } else { 93 writel_relaxed(b, dev->base + offset); 94 } 95 } 96 97 u32 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset) 98 { 99 /* 100 * DesignWare I2C core doesn't seem to have solid strategy to meet 101 * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec 102 * will result in violation of the tHD;STA spec. 103 */ 104 if (cond) 105 /* 106 * Conditional expression: 107 * 108 * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH 109 * 110 * This is based on the DW manuals, and represents an ideal 111 * configuration. The resulting I2C bus speed will be 112 * faster than any of the others. 113 * 114 * If your hardware is free from tHD;STA issue, try this one. 115 */ 116 return (ic_clk * tSYMBOL + 500000) / 1000000 - 8 + offset; 117 else 118 /* 119 * Conditional expression: 120 * 121 * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf) 122 * 123 * This is just experimental rule; the tHD;STA period turned 124 * out to be proportinal to (_HCNT + 3). With this setting, 125 * we could meet both tHIGH and tHD;STA timing specs. 126 * 127 * If unsure, you'd better to take this alternative. 128 * 129 * The reason why we need to take into account "tf" here, 130 * is the same as described in i2c_dw_scl_lcnt(). 131 */ 132 return (ic_clk * (tSYMBOL + tf) + 500000) / 1000000 133 - 3 + offset; 134 } 135 136 u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset) 137 { 138 /* 139 * Conditional expression: 140 * 141 * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf) 142 * 143 * DW I2C core starts counting the SCL CNTs for the LOW period 144 * of the SCL clock (tLOW) as soon as it pulls the SCL line. 145 * In order to meet the tLOW timing spec, we need to take into 146 * account the fall time of SCL signal (tf). Default tf value 147 * should be 0.3 us, for safety. 148 */ 149 return ((ic_clk * (tLOW + tf) + 500000) / 1000000) - 1 + offset; 150 } 151 152 void __i2c_dw_enable(struct dw_i2c_dev *dev, bool enable) 153 { 154 dw_writel(dev, enable, DW_IC_ENABLE); 155 } 156 157 void __i2c_dw_enable_and_wait(struct dw_i2c_dev *dev, bool enable) 158 { 159 int timeout = 100; 160 161 do { 162 __i2c_dw_enable(dev, enable); 163 if ((dw_readl(dev, DW_IC_ENABLE_STATUS) & 1) == enable) 164 return; 165 166 /* 167 * Wait 10 times the signaling period of the highest I2C 168 * transfer supported by the driver (for 400KHz this is 169 * 25us) as described in the DesignWare I2C databook. 170 */ 171 usleep_range(25, 250); 172 } while (timeout--); 173 174 dev_warn(dev->dev, "timeout in %sabling adapter\n", 175 enable ? "en" : "dis"); 176 } 177 178 unsigned long i2c_dw_clk_rate(struct dw_i2c_dev *dev) 179 { 180 /* 181 * Clock is not necessary if we got LCNT/HCNT values directly from 182 * the platform code. 183 */ 184 if (WARN_ON_ONCE(!dev->get_clk_rate_khz)) 185 return 0; 186 return dev->get_clk_rate_khz(dev); 187 } 188 189 int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare) 190 { 191 if (IS_ERR(dev->clk)) 192 return PTR_ERR(dev->clk); 193 194 if (prepare) 195 return clk_prepare_enable(dev->clk); 196 197 clk_disable_unprepare(dev->clk); 198 return 0; 199 } 200 EXPORT_SYMBOL_GPL(i2c_dw_prepare_clk); 201 202 int i2c_dw_acquire_lock(struct dw_i2c_dev *dev) 203 { 204 int ret; 205 206 if (!dev->acquire_lock) 207 return 0; 208 209 ret = dev->acquire_lock(dev); 210 if (!ret) 211 return 0; 212 213 dev_err(dev->dev, "couldn't acquire bus ownership\n"); 214 215 return ret; 216 } 217 218 void i2c_dw_release_lock(struct dw_i2c_dev *dev) 219 { 220 if (dev->release_lock) 221 dev->release_lock(dev); 222 } 223 224 /* 225 * Waiting for bus not busy 226 */ 227 int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev) 228 { 229 int timeout = TIMEOUT; 230 231 while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) { 232 if (timeout <= 0) { 233 dev_warn(dev->dev, "timeout waiting for bus ready\n"); 234 i2c_recover_bus(&dev->adapter); 235 236 if (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) 237 return -ETIMEDOUT; 238 return 0; 239 } 240 timeout--; 241 usleep_range(1000, 1100); 242 } 243 244 return 0; 245 } 246 247 int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev) 248 { 249 unsigned long abort_source = dev->abort_source; 250 int i; 251 252 if (abort_source & DW_IC_TX_ABRT_NOACK) { 253 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) 254 dev_dbg(dev->dev, 255 "%s: %s\n", __func__, abort_sources[i]); 256 return -EREMOTEIO; 257 } 258 259 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) 260 dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]); 261 262 if (abort_source & DW_IC_TX_ARB_LOST) 263 return -EAGAIN; 264 else if (abort_source & DW_IC_TX_ABRT_GCALL_READ) 265 return -EINVAL; /* wrong msgs[] data */ 266 else 267 return -EIO; 268 } 269 270 u32 i2c_dw_func(struct i2c_adapter *adap) 271 { 272 struct dw_i2c_dev *dev = i2c_get_adapdata(adap); 273 274 return dev->functionality; 275 } 276 277 void i2c_dw_disable(struct dw_i2c_dev *dev) 278 { 279 /* Disable controller */ 280 __i2c_dw_enable_and_wait(dev, false); 281 282 /* Disable all interupts */ 283 dw_writel(dev, 0, DW_IC_INTR_MASK); 284 dw_readl(dev, DW_IC_CLR_INTR); 285 } 286 287 void i2c_dw_disable_int(struct dw_i2c_dev *dev) 288 { 289 dw_writel(dev, 0, DW_IC_INTR_MASK); 290 } 291 292 u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev) 293 { 294 return dw_readl(dev, DW_IC_COMP_PARAM_1); 295 } 296 EXPORT_SYMBOL_GPL(i2c_dw_read_comp_param); 297 298 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core"); 299 MODULE_LICENSE("GPL"); 300