1 /* 2 * Synopsys DesignWare I2C adapter driver. 3 * 4 * Based on the TI DAVINCI I2C adapter driver. 5 * 6 * Copyright (C) 2006 Texas Instruments. 7 * Copyright (C) 2007 MontaVista Software Inc. 8 * Copyright (C) 2009 Provigent Ltd. 9 * 10 * ---------------------------------------------------------------------------- 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * ---------------------------------------------------------------------------- 22 * 23 */ 24 #include <linux/delay.h> 25 #include <linux/export.h> 26 #include <linux/errno.h> 27 #include <linux/err.h> 28 #include <linux/i2c.h> 29 #include <linux/interrupt.h> 30 #include <linux/io.h> 31 #include <linux/module.h> 32 #include <linux/pm_runtime.h> 33 34 #include "i2c-designware-core.h" 35 36 static char *abort_sources[] = { 37 [ABRT_7B_ADDR_NOACK] = 38 "slave address not acknowledged (7bit mode)", 39 [ABRT_10ADDR1_NOACK] = 40 "first address byte not acknowledged (10bit mode)", 41 [ABRT_10ADDR2_NOACK] = 42 "second address byte not acknowledged (10bit mode)", 43 [ABRT_TXDATA_NOACK] = 44 "data not acknowledged", 45 [ABRT_GCALL_NOACK] = 46 "no acknowledgement for a general call", 47 [ABRT_GCALL_READ] = 48 "read after general call", 49 [ABRT_SBYTE_ACKDET] = 50 "start byte acknowledged", 51 [ABRT_SBYTE_NORSTRT] = 52 "trying to send start byte when restart is disabled", 53 [ABRT_10B_RD_NORSTRT] = 54 "trying to read when restart is disabled (10bit mode)", 55 [ABRT_MASTER_DIS] = 56 "trying to use disabled adapter", 57 [ARB_LOST] = 58 "lost arbitration", 59 [ABRT_SLAVE_FLUSH_TXFIFO] = 60 "read command so flush old data in the TX FIFO", 61 [ABRT_SLAVE_ARBLOST] = 62 "slave lost the bus while transmitting data to a remote master", 63 [ABRT_SLAVE_RD_INTX] = 64 "incorrect slave-transmitter mode configuration", 65 }; 66 67 u32 dw_readl(struct dw_i2c_dev *dev, int offset) 68 { 69 u32 value; 70 71 if (dev->flags & ACCESS_16BIT) 72 value = readw_relaxed(dev->base + offset) | 73 (readw_relaxed(dev->base + offset + 2) << 16); 74 else 75 value = readl_relaxed(dev->base + offset); 76 77 if (dev->flags & ACCESS_SWAP) 78 return swab32(value); 79 else 80 return value; 81 } 82 83 void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset) 84 { 85 if (dev->flags & ACCESS_SWAP) 86 b = swab32(b); 87 88 if (dev->flags & ACCESS_16BIT) { 89 writew_relaxed((u16)b, dev->base + offset); 90 writew_relaxed((u16)(b >> 16), dev->base + offset + 2); 91 } else { 92 writel_relaxed(b, dev->base + offset); 93 } 94 } 95 96 u32 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset) 97 { 98 /* 99 * DesignWare I2C core doesn't seem to have solid strategy to meet 100 * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec 101 * will result in violation of the tHD;STA spec. 102 */ 103 if (cond) 104 /* 105 * Conditional expression: 106 * 107 * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH 108 * 109 * This is based on the DW manuals, and represents an ideal 110 * configuration. The resulting I2C bus speed will be 111 * faster than any of the others. 112 * 113 * If your hardware is free from tHD;STA issue, try this one. 114 */ 115 return (ic_clk * tSYMBOL + 500000) / 1000000 - 8 + offset; 116 else 117 /* 118 * Conditional expression: 119 * 120 * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf) 121 * 122 * This is just experimental rule; the tHD;STA period turned 123 * out to be proportinal to (_HCNT + 3). With this setting, 124 * we could meet both tHIGH and tHD;STA timing specs. 125 * 126 * If unsure, you'd better to take this alternative. 127 * 128 * The reason why we need to take into account "tf" here, 129 * is the same as described in i2c_dw_scl_lcnt(). 130 */ 131 return (ic_clk * (tSYMBOL + tf) + 500000) / 1000000 132 - 3 + offset; 133 } 134 135 u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset) 136 { 137 /* 138 * Conditional expression: 139 * 140 * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf) 141 * 142 * DW I2C core starts counting the SCL CNTs for the LOW period 143 * of the SCL clock (tLOW) as soon as it pulls the SCL line. 144 * In order to meet the tLOW timing spec, we need to take into 145 * account the fall time of SCL signal (tf). Default tf value 146 * should be 0.3 us, for safety. 147 */ 148 return ((ic_clk * (tLOW + tf) + 500000) / 1000000) - 1 + offset; 149 } 150 151 void __i2c_dw_enable(struct dw_i2c_dev *dev, bool enable) 152 { 153 dw_writel(dev, enable, DW_IC_ENABLE); 154 } 155 156 void __i2c_dw_enable_and_wait(struct dw_i2c_dev *dev, bool enable) 157 { 158 int timeout = 100; 159 160 do { 161 __i2c_dw_enable(dev, enable); 162 if ((dw_readl(dev, DW_IC_ENABLE_STATUS) & 1) == enable) 163 return; 164 165 /* 166 * Wait 10 times the signaling period of the highest I2C 167 * transfer supported by the driver (for 400KHz this is 168 * 25us) as described in the DesignWare I2C databook. 169 */ 170 usleep_range(25, 250); 171 } while (timeout--); 172 173 dev_warn(dev->dev, "timeout in %sabling adapter\n", 174 enable ? "en" : "dis"); 175 } 176 177 unsigned long i2c_dw_clk_rate(struct dw_i2c_dev *dev) 178 { 179 /* 180 * Clock is not necessary if we got LCNT/HCNT values directly from 181 * the platform code. 182 */ 183 if (WARN_ON_ONCE(!dev->get_clk_rate_khz)) 184 return 0; 185 return dev->get_clk_rate_khz(dev); 186 } 187 188 int i2c_dw_acquire_lock(struct dw_i2c_dev *dev) 189 { 190 int ret; 191 192 if (!dev->acquire_lock) 193 return 0; 194 195 ret = dev->acquire_lock(dev); 196 if (!ret) 197 return 0; 198 199 dev_err(dev->dev, "couldn't acquire bus ownership\n"); 200 201 return ret; 202 } 203 204 void i2c_dw_release_lock(struct dw_i2c_dev *dev) 205 { 206 if (dev->release_lock) 207 dev->release_lock(dev); 208 } 209 210 /* 211 * Waiting for bus not busy 212 */ 213 int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev) 214 { 215 int timeout = TIMEOUT; 216 217 while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) { 218 if (timeout <= 0) { 219 dev_warn(dev->dev, "timeout waiting for bus ready\n"); 220 return -ETIMEDOUT; 221 } 222 timeout--; 223 usleep_range(1000, 1100); 224 } 225 226 return 0; 227 } 228 229 int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev) 230 { 231 unsigned long abort_source = dev->abort_source; 232 int i; 233 234 if (abort_source & DW_IC_TX_ABRT_NOACK) { 235 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) 236 dev_dbg(dev->dev, 237 "%s: %s\n", __func__, abort_sources[i]); 238 return -EREMOTEIO; 239 } 240 241 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) 242 dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]); 243 244 if (abort_source & DW_IC_TX_ARB_LOST) 245 return -EAGAIN; 246 else if (abort_source & DW_IC_TX_ABRT_GCALL_READ) 247 return -EINVAL; /* wrong msgs[] data */ 248 else 249 return -EIO; 250 } 251 252 u32 i2c_dw_func(struct i2c_adapter *adap) 253 { 254 struct dw_i2c_dev *dev = i2c_get_adapdata(adap); 255 256 return dev->functionality; 257 } 258 259 void i2c_dw_disable(struct dw_i2c_dev *dev) 260 { 261 /* Disable controller */ 262 __i2c_dw_enable_and_wait(dev, false); 263 264 /* Disable all interupts */ 265 dw_writel(dev, 0, DW_IC_INTR_MASK); 266 dw_readl(dev, DW_IC_CLR_INTR); 267 } 268 269 void i2c_dw_disable_int(struct dw_i2c_dev *dev) 270 { 271 dw_writel(dev, 0, DW_IC_INTR_MASK); 272 } 273 274 u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev) 275 { 276 return dw_readl(dev, DW_IC_COMP_PARAM_1); 277 } 278 EXPORT_SYMBOL_GPL(i2c_dw_read_comp_param); 279 280 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core"); 281 MODULE_LICENSE("GPL"); 282