1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Synopsys DesignWare I2C adapter driver. 4 * 5 * Based on the TI DAVINCI I2C adapter driver. 6 * 7 * Copyright (C) 2006 Texas Instruments. 8 * Copyright (C) 2007 MontaVista Software Inc. 9 * Copyright (C) 2009 Provigent Ltd. 10 */ 11 #include <linux/acpi.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/device.h> 15 #include <linux/err.h> 16 #include <linux/errno.h> 17 #include <linux/export.h> 18 #include <linux/i2c.h> 19 #include <linux/interrupt.h> 20 #include <linux/io.h> 21 #include <linux/kernel.h> 22 #include <linux/module.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/regmap.h> 25 #include <linux/swab.h> 26 #include <linux/types.h> 27 28 #include "i2c-designware-core.h" 29 30 static char *abort_sources[] = { 31 [ABRT_7B_ADDR_NOACK] = 32 "slave address not acknowledged (7bit mode)", 33 [ABRT_10ADDR1_NOACK] = 34 "first address byte not acknowledged (10bit mode)", 35 [ABRT_10ADDR2_NOACK] = 36 "second address byte not acknowledged (10bit mode)", 37 [ABRT_TXDATA_NOACK] = 38 "data not acknowledged", 39 [ABRT_GCALL_NOACK] = 40 "no acknowledgement for a general call", 41 [ABRT_GCALL_READ] = 42 "read after general call", 43 [ABRT_SBYTE_ACKDET] = 44 "start byte acknowledged", 45 [ABRT_SBYTE_NORSTRT] = 46 "trying to send start byte when restart is disabled", 47 [ABRT_10B_RD_NORSTRT] = 48 "trying to read when restart is disabled (10bit mode)", 49 [ABRT_MASTER_DIS] = 50 "trying to use disabled adapter", 51 [ARB_LOST] = 52 "lost arbitration", 53 [ABRT_SLAVE_FLUSH_TXFIFO] = 54 "read command so flush old data in the TX FIFO", 55 [ABRT_SLAVE_ARBLOST] = 56 "slave lost the bus while transmitting data to a remote master", 57 [ABRT_SLAVE_RD_INTX] = 58 "incorrect slave-transmitter mode configuration", 59 }; 60 61 static int dw_reg_read(void *context, unsigned int reg, unsigned int *val) 62 { 63 struct dw_i2c_dev *dev = context; 64 65 *val = readl_relaxed(dev->base + reg); 66 67 return 0; 68 } 69 70 static int dw_reg_write(void *context, unsigned int reg, unsigned int val) 71 { 72 struct dw_i2c_dev *dev = context; 73 74 writel_relaxed(val, dev->base + reg); 75 76 return 0; 77 } 78 79 static int dw_reg_read_swab(void *context, unsigned int reg, unsigned int *val) 80 { 81 struct dw_i2c_dev *dev = context; 82 83 *val = swab32(readl_relaxed(dev->base + reg)); 84 85 return 0; 86 } 87 88 static int dw_reg_write_swab(void *context, unsigned int reg, unsigned int val) 89 { 90 struct dw_i2c_dev *dev = context; 91 92 writel_relaxed(swab32(val), dev->base + reg); 93 94 return 0; 95 } 96 97 static int dw_reg_read_word(void *context, unsigned int reg, unsigned int *val) 98 { 99 struct dw_i2c_dev *dev = context; 100 101 *val = readw_relaxed(dev->base + reg) | 102 (readw_relaxed(dev->base + reg + 2) << 16); 103 104 return 0; 105 } 106 107 static int dw_reg_write_word(void *context, unsigned int reg, unsigned int val) 108 { 109 struct dw_i2c_dev *dev = context; 110 111 writew_relaxed(val, dev->base + reg); 112 writew_relaxed(val >> 16, dev->base + reg + 2); 113 114 return 0; 115 } 116 117 /** 118 * i2c_dw_init_regmap() - Initialize registers map 119 * @dev: device private data 120 * 121 * Autodetects needed register access mode and creates the regmap with 122 * corresponding read/write callbacks. This must be called before doing any 123 * other register access. 124 */ 125 int i2c_dw_init_regmap(struct dw_i2c_dev *dev) 126 { 127 struct regmap_config map_cfg = { 128 .reg_bits = 32, 129 .val_bits = 32, 130 .reg_stride = 4, 131 .disable_locking = true, 132 .reg_read = dw_reg_read, 133 .reg_write = dw_reg_write, 134 .max_register = DW_IC_COMP_TYPE, 135 }; 136 u32 reg; 137 int ret; 138 139 /* 140 * Skip detecting the registers map configuration if the regmap has 141 * already been provided by a higher code. 142 */ 143 if (dev->map) 144 return 0; 145 146 ret = i2c_dw_acquire_lock(dev); 147 if (ret) 148 return ret; 149 150 reg = readl(dev->base + DW_IC_COMP_TYPE); 151 i2c_dw_release_lock(dev); 152 153 if ((dev->flags & MODEL_MASK) == MODEL_AMD_NAVI_GPU) 154 map_cfg.max_register = AMD_UCSI_INTR_REG; 155 156 if (reg == swab32(DW_IC_COMP_TYPE_VALUE)) { 157 map_cfg.reg_read = dw_reg_read_swab; 158 map_cfg.reg_write = dw_reg_write_swab; 159 } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) { 160 map_cfg.reg_read = dw_reg_read_word; 161 map_cfg.reg_write = dw_reg_write_word; 162 } else if (reg != DW_IC_COMP_TYPE_VALUE) { 163 dev_err(dev->dev, 164 "Unknown Synopsys component type: 0x%08x\n", reg); 165 return -ENODEV; 166 } 167 168 /* 169 * Note we'll check the return value of the regmap IO accessors only 170 * at the probe stage. The rest of the code won't do this because 171 * basically we have MMIO-based regmap so non of the read/write methods 172 * can fail. 173 */ 174 dev->map = devm_regmap_init(dev->dev, NULL, dev, &map_cfg); 175 if (IS_ERR(dev->map)) { 176 dev_err(dev->dev, "Failed to init the registers map\n"); 177 return PTR_ERR(dev->map); 178 } 179 180 return 0; 181 } 182 183 static const u32 supported_speeds[] = { 184 I2C_MAX_HIGH_SPEED_MODE_FREQ, 185 I2C_MAX_FAST_MODE_PLUS_FREQ, 186 I2C_MAX_FAST_MODE_FREQ, 187 I2C_MAX_STANDARD_MODE_FREQ, 188 }; 189 190 int i2c_dw_validate_speed(struct dw_i2c_dev *dev) 191 { 192 struct i2c_timings *t = &dev->timings; 193 unsigned int i; 194 195 /* 196 * Only standard mode at 100kHz, fast mode at 400kHz, 197 * fast mode plus at 1MHz and high speed mode at 3.4MHz are supported. 198 */ 199 for (i = 0; i < ARRAY_SIZE(supported_speeds); i++) { 200 if (t->bus_freq_hz == supported_speeds[i]) 201 return 0; 202 } 203 204 dev_err(dev->dev, 205 "%d Hz is unsupported, only 100kHz, 400kHz, 1MHz and 3.4MHz are supported\n", 206 t->bus_freq_hz); 207 208 return -EINVAL; 209 } 210 EXPORT_SYMBOL_GPL(i2c_dw_validate_speed); 211 212 #ifdef CONFIG_ACPI 213 214 #include <linux/dmi.h> 215 216 /* 217 * The HCNT/LCNT information coming from ACPI should be the most accurate 218 * for given platform. However, some systems get it wrong. On such systems 219 * we get better results by calculating those based on the input clock. 220 */ 221 static const struct dmi_system_id i2c_dw_no_acpi_params[] = { 222 { 223 .ident = "Dell Inspiron 7348", 224 .matches = { 225 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 226 DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 7348"), 227 }, 228 }, 229 {} 230 }; 231 232 static void i2c_dw_acpi_params(struct device *device, char method[], 233 u16 *hcnt, u16 *lcnt, u32 *sda_hold) 234 { 235 struct acpi_buffer buf = { ACPI_ALLOCATE_BUFFER }; 236 acpi_handle handle = ACPI_HANDLE(device); 237 union acpi_object *obj; 238 239 if (dmi_check_system(i2c_dw_no_acpi_params)) 240 return; 241 242 if (ACPI_FAILURE(acpi_evaluate_object(handle, method, NULL, &buf))) 243 return; 244 245 obj = (union acpi_object *)buf.pointer; 246 if (obj->type == ACPI_TYPE_PACKAGE && obj->package.count == 3) { 247 const union acpi_object *objs = obj->package.elements; 248 249 *hcnt = (u16)objs[0].integer.value; 250 *lcnt = (u16)objs[1].integer.value; 251 *sda_hold = (u32)objs[2].integer.value; 252 } 253 254 kfree(buf.pointer); 255 } 256 257 int i2c_dw_acpi_configure(struct device *device) 258 { 259 struct dw_i2c_dev *dev = dev_get_drvdata(device); 260 struct i2c_timings *t = &dev->timings; 261 u32 ss_ht = 0, fp_ht = 0, hs_ht = 0, fs_ht = 0; 262 263 /* 264 * Try to get SDA hold time and *CNT values from an ACPI method for 265 * selected speed modes. 266 */ 267 i2c_dw_acpi_params(device, "SSCN", &dev->ss_hcnt, &dev->ss_lcnt, &ss_ht); 268 i2c_dw_acpi_params(device, "FPCN", &dev->fp_hcnt, &dev->fp_lcnt, &fp_ht); 269 i2c_dw_acpi_params(device, "HSCN", &dev->hs_hcnt, &dev->hs_lcnt, &hs_ht); 270 i2c_dw_acpi_params(device, "FMCN", &dev->fs_hcnt, &dev->fs_lcnt, &fs_ht); 271 272 switch (t->bus_freq_hz) { 273 case I2C_MAX_STANDARD_MODE_FREQ: 274 dev->sda_hold_time = ss_ht; 275 break; 276 case I2C_MAX_FAST_MODE_PLUS_FREQ: 277 dev->sda_hold_time = fp_ht; 278 break; 279 case I2C_MAX_HIGH_SPEED_MODE_FREQ: 280 dev->sda_hold_time = hs_ht; 281 break; 282 case I2C_MAX_FAST_MODE_FREQ: 283 default: 284 dev->sda_hold_time = fs_ht; 285 break; 286 } 287 288 return 0; 289 } 290 EXPORT_SYMBOL_GPL(i2c_dw_acpi_configure); 291 292 static u32 i2c_dw_acpi_round_bus_speed(struct device *device) 293 { 294 u32 acpi_speed; 295 int i; 296 297 acpi_speed = i2c_acpi_find_bus_speed(device); 298 /* 299 * Some DSTDs use a non standard speed, round down to the lowest 300 * standard speed. 301 */ 302 for (i = 0; i < ARRAY_SIZE(supported_speeds); i++) { 303 if (acpi_speed >= supported_speeds[i]) 304 return supported_speeds[i]; 305 } 306 307 return 0; 308 } 309 310 #else /* CONFIG_ACPI */ 311 312 static inline u32 i2c_dw_acpi_round_bus_speed(struct device *device) { return 0; } 313 314 #endif /* CONFIG_ACPI */ 315 316 void i2c_dw_adjust_bus_speed(struct dw_i2c_dev *dev) 317 { 318 u32 acpi_speed = i2c_dw_acpi_round_bus_speed(dev->dev); 319 struct i2c_timings *t = &dev->timings; 320 321 /* 322 * Find bus speed from the "clock-frequency" device property, ACPI 323 * or by using fast mode if neither is set. 324 */ 325 if (acpi_speed && t->bus_freq_hz) 326 t->bus_freq_hz = min(t->bus_freq_hz, acpi_speed); 327 else if (acpi_speed || t->bus_freq_hz) 328 t->bus_freq_hz = max(t->bus_freq_hz, acpi_speed); 329 else 330 t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ; 331 } 332 EXPORT_SYMBOL_GPL(i2c_dw_adjust_bus_speed); 333 334 u32 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset) 335 { 336 /* 337 * DesignWare I2C core doesn't seem to have solid strategy to meet 338 * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec 339 * will result in violation of the tHD;STA spec. 340 */ 341 if (cond) 342 /* 343 * Conditional expression: 344 * 345 * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH 346 * 347 * This is based on the DW manuals, and represents an ideal 348 * configuration. The resulting I2C bus speed will be 349 * faster than any of the others. 350 * 351 * If your hardware is free from tHD;STA issue, try this one. 352 */ 353 return (ic_clk * tSYMBOL + 500000) / 1000000 - 8 + offset; 354 else 355 /* 356 * Conditional expression: 357 * 358 * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf) 359 * 360 * This is just experimental rule; the tHD;STA period turned 361 * out to be proportinal to (_HCNT + 3). With this setting, 362 * we could meet both tHIGH and tHD;STA timing specs. 363 * 364 * If unsure, you'd better to take this alternative. 365 * 366 * The reason why we need to take into account "tf" here, 367 * is the same as described in i2c_dw_scl_lcnt(). 368 */ 369 return (ic_clk * (tSYMBOL + tf) + 500000) / 1000000 370 - 3 + offset; 371 } 372 373 u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset) 374 { 375 /* 376 * Conditional expression: 377 * 378 * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf) 379 * 380 * DW I2C core starts counting the SCL CNTs for the LOW period 381 * of the SCL clock (tLOW) as soon as it pulls the SCL line. 382 * In order to meet the tLOW timing spec, we need to take into 383 * account the fall time of SCL signal (tf). Default tf value 384 * should be 0.3 us, for safety. 385 */ 386 return ((ic_clk * (tLOW + tf) + 500000) / 1000000) - 1 + offset; 387 } 388 389 int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev) 390 { 391 u32 reg; 392 int ret; 393 394 ret = i2c_dw_acquire_lock(dev); 395 if (ret) 396 return ret; 397 398 /* Configure SDA Hold Time if required */ 399 ret = regmap_read(dev->map, DW_IC_COMP_VERSION, ®); 400 if (ret) 401 goto err_release_lock; 402 403 if (reg >= DW_IC_SDA_HOLD_MIN_VERS) { 404 if (!dev->sda_hold_time) { 405 /* Keep previous hold time setting if no one set it */ 406 ret = regmap_read(dev->map, DW_IC_SDA_HOLD, 407 &dev->sda_hold_time); 408 if (ret) 409 goto err_release_lock; 410 } 411 412 /* 413 * Workaround for avoiding TX arbitration lost in case I2C 414 * slave pulls SDA down "too quickly" after falling edge of 415 * SCL by enabling non-zero SDA RX hold. Specification says it 416 * extends incoming SDA low to high transition while SCL is 417 * high but it appears to help also above issue. 418 */ 419 if (!(dev->sda_hold_time & DW_IC_SDA_HOLD_RX_MASK)) 420 dev->sda_hold_time |= 1 << DW_IC_SDA_HOLD_RX_SHIFT; 421 422 dev_dbg(dev->dev, "SDA Hold Time TX:RX = %d:%d\n", 423 dev->sda_hold_time & ~(u32)DW_IC_SDA_HOLD_RX_MASK, 424 dev->sda_hold_time >> DW_IC_SDA_HOLD_RX_SHIFT); 425 } else if (dev->set_sda_hold_time) { 426 dev->set_sda_hold_time(dev); 427 } else if (dev->sda_hold_time) { 428 dev_warn(dev->dev, 429 "Hardware too old to adjust SDA hold time.\n"); 430 dev->sda_hold_time = 0; 431 } 432 433 err_release_lock: 434 i2c_dw_release_lock(dev); 435 436 return ret; 437 } 438 439 void __i2c_dw_disable(struct dw_i2c_dev *dev) 440 { 441 int timeout = 100; 442 u32 status; 443 444 do { 445 __i2c_dw_disable_nowait(dev); 446 /* 447 * The enable status register may be unimplemented, but 448 * in that case this test reads zero and exits the loop. 449 */ 450 regmap_read(dev->map, DW_IC_ENABLE_STATUS, &status); 451 if ((status & 1) == 0) 452 return; 453 454 /* 455 * Wait 10 times the signaling period of the highest I2C 456 * transfer supported by the driver (for 400KHz this is 457 * 25us) as described in the DesignWare I2C databook. 458 */ 459 usleep_range(25, 250); 460 } while (timeout--); 461 462 dev_warn(dev->dev, "timeout in disabling adapter\n"); 463 } 464 465 unsigned long i2c_dw_clk_rate(struct dw_i2c_dev *dev) 466 { 467 /* 468 * Clock is not necessary if we got LCNT/HCNT values directly from 469 * the platform code. 470 */ 471 if (WARN_ON_ONCE(!dev->get_clk_rate_khz)) 472 return 0; 473 return dev->get_clk_rate_khz(dev); 474 } 475 476 int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare) 477 { 478 int ret; 479 480 if (IS_ERR(dev->clk)) 481 return PTR_ERR(dev->clk); 482 483 if (prepare) { 484 /* Optional interface clock */ 485 ret = clk_prepare_enable(dev->pclk); 486 if (ret) 487 return ret; 488 489 ret = clk_prepare_enable(dev->clk); 490 if (ret) 491 clk_disable_unprepare(dev->pclk); 492 493 return ret; 494 } 495 496 clk_disable_unprepare(dev->clk); 497 clk_disable_unprepare(dev->pclk); 498 499 return 0; 500 } 501 EXPORT_SYMBOL_GPL(i2c_dw_prepare_clk); 502 503 int i2c_dw_acquire_lock(struct dw_i2c_dev *dev) 504 { 505 int ret; 506 507 if (!dev->acquire_lock) 508 return 0; 509 510 ret = dev->acquire_lock(); 511 if (!ret) 512 return 0; 513 514 dev_err(dev->dev, "couldn't acquire bus ownership\n"); 515 516 return ret; 517 } 518 519 void i2c_dw_release_lock(struct dw_i2c_dev *dev) 520 { 521 if (dev->release_lock) 522 dev->release_lock(); 523 } 524 525 /* 526 * Waiting for bus not busy 527 */ 528 int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev) 529 { 530 u32 status; 531 int ret; 532 533 ret = regmap_read_poll_timeout(dev->map, DW_IC_STATUS, status, 534 !(status & DW_IC_STATUS_ACTIVITY), 535 1100, 20000); 536 if (ret) { 537 dev_warn(dev->dev, "timeout waiting for bus ready\n"); 538 539 i2c_recover_bus(&dev->adapter); 540 541 regmap_read(dev->map, DW_IC_STATUS, &status); 542 if (!(status & DW_IC_STATUS_ACTIVITY)) 543 ret = 0; 544 } 545 546 return ret; 547 } 548 549 int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev) 550 { 551 unsigned long abort_source = dev->abort_source; 552 int i; 553 554 if (abort_source & DW_IC_TX_ABRT_NOACK) { 555 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) 556 dev_dbg(dev->dev, 557 "%s: %s\n", __func__, abort_sources[i]); 558 return -EREMOTEIO; 559 } 560 561 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) 562 dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]); 563 564 if (abort_source & DW_IC_TX_ARB_LOST) 565 return -EAGAIN; 566 else if (abort_source & DW_IC_TX_ABRT_GCALL_READ) 567 return -EINVAL; /* wrong msgs[] data */ 568 else 569 return -EIO; 570 } 571 572 int i2c_dw_set_fifo_size(struct dw_i2c_dev *dev) 573 { 574 u32 param, tx_fifo_depth, rx_fifo_depth; 575 int ret; 576 577 /* 578 * Try to detect the FIFO depth if not set by interface driver, 579 * the depth could be from 2 to 256 from HW spec. 580 */ 581 ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, ¶m); 582 if (ret) 583 return ret; 584 585 tx_fifo_depth = ((param >> 16) & 0xff) + 1; 586 rx_fifo_depth = ((param >> 8) & 0xff) + 1; 587 if (!dev->tx_fifo_depth) { 588 dev->tx_fifo_depth = tx_fifo_depth; 589 dev->rx_fifo_depth = rx_fifo_depth; 590 } else if (tx_fifo_depth >= 2) { 591 dev->tx_fifo_depth = min_t(u32, dev->tx_fifo_depth, 592 tx_fifo_depth); 593 dev->rx_fifo_depth = min_t(u32, dev->rx_fifo_depth, 594 rx_fifo_depth); 595 } 596 597 return 0; 598 } 599 600 u32 i2c_dw_func(struct i2c_adapter *adap) 601 { 602 struct dw_i2c_dev *dev = i2c_get_adapdata(adap); 603 604 return dev->functionality; 605 } 606 607 void i2c_dw_disable(struct dw_i2c_dev *dev) 608 { 609 u32 dummy; 610 611 /* Disable controller */ 612 __i2c_dw_disable(dev); 613 614 /* Disable all interrupts */ 615 regmap_write(dev->map, DW_IC_INTR_MASK, 0); 616 regmap_read(dev->map, DW_IC_CLR_INTR, &dummy); 617 } 618 619 void i2c_dw_disable_int(struct dw_i2c_dev *dev) 620 { 621 regmap_write(dev->map, DW_IC_INTR_MASK, 0); 622 } 623 624 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core"); 625 MODULE_LICENSE("GPL"); 626