1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Synopsys DesignWare I2C adapter driver.
4  *
5  * Based on the TI DAVINCI I2C adapter driver.
6  *
7  * Copyright (C) 2006 Texas Instruments.
8  * Copyright (C) 2007 MontaVista Software Inc.
9  * Copyright (C) 2009 Provigent Ltd.
10  */
11 #include <linux/acpi.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/err.h>
16 #include <linux/errno.h>
17 #include <linux/export.h>
18 #include <linux/i2c.h>
19 #include <linux/interrupt.h>
20 #include <linux/io.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/regmap.h>
25 #include <linux/swab.h>
26 #include <linux/types.h>
27 #include <linux/units.h>
28 
29 #include "i2c-designware-core.h"
30 
31 static char *abort_sources[] = {
32 	[ABRT_7B_ADDR_NOACK] =
33 		"slave address not acknowledged (7bit mode)",
34 	[ABRT_10ADDR1_NOACK] =
35 		"first address byte not acknowledged (10bit mode)",
36 	[ABRT_10ADDR2_NOACK] =
37 		"second address byte not acknowledged (10bit mode)",
38 	[ABRT_TXDATA_NOACK] =
39 		"data not acknowledged",
40 	[ABRT_GCALL_NOACK] =
41 		"no acknowledgement for a general call",
42 	[ABRT_GCALL_READ] =
43 		"read after general call",
44 	[ABRT_SBYTE_ACKDET] =
45 		"start byte acknowledged",
46 	[ABRT_SBYTE_NORSTRT] =
47 		"trying to send start byte when restart is disabled",
48 	[ABRT_10B_RD_NORSTRT] =
49 		"trying to read when restart is disabled (10bit mode)",
50 	[ABRT_MASTER_DIS] =
51 		"trying to use disabled adapter",
52 	[ARB_LOST] =
53 		"lost arbitration",
54 	[ABRT_SLAVE_FLUSH_TXFIFO] =
55 		"read command so flush old data in the TX FIFO",
56 	[ABRT_SLAVE_ARBLOST] =
57 		"slave lost the bus while transmitting data to a remote master",
58 	[ABRT_SLAVE_RD_INTX] =
59 		"incorrect slave-transmitter mode configuration",
60 };
61 
62 static int dw_reg_read(void *context, unsigned int reg, unsigned int *val)
63 {
64 	struct dw_i2c_dev *dev = context;
65 
66 	*val = readl_relaxed(dev->base + reg);
67 
68 	return 0;
69 }
70 
71 static int dw_reg_write(void *context, unsigned int reg, unsigned int val)
72 {
73 	struct dw_i2c_dev *dev = context;
74 
75 	writel_relaxed(val, dev->base + reg);
76 
77 	return 0;
78 }
79 
80 static int dw_reg_read_swab(void *context, unsigned int reg, unsigned int *val)
81 {
82 	struct dw_i2c_dev *dev = context;
83 
84 	*val = swab32(readl_relaxed(dev->base + reg));
85 
86 	return 0;
87 }
88 
89 static int dw_reg_write_swab(void *context, unsigned int reg, unsigned int val)
90 {
91 	struct dw_i2c_dev *dev = context;
92 
93 	writel_relaxed(swab32(val), dev->base + reg);
94 
95 	return 0;
96 }
97 
98 static int dw_reg_read_word(void *context, unsigned int reg, unsigned int *val)
99 {
100 	struct dw_i2c_dev *dev = context;
101 
102 	*val = readw_relaxed(dev->base + reg) |
103 		(readw_relaxed(dev->base + reg + 2) << 16);
104 
105 	return 0;
106 }
107 
108 static int dw_reg_write_word(void *context, unsigned int reg, unsigned int val)
109 {
110 	struct dw_i2c_dev *dev = context;
111 
112 	writew_relaxed(val, dev->base + reg);
113 	writew_relaxed(val >> 16, dev->base + reg + 2);
114 
115 	return 0;
116 }
117 
118 /**
119  * i2c_dw_init_regmap() - Initialize registers map
120  * @dev: device private data
121  *
122  * Autodetects needed register access mode and creates the regmap with
123  * corresponding read/write callbacks. This must be called before doing any
124  * other register access.
125  */
126 int i2c_dw_init_regmap(struct dw_i2c_dev *dev)
127 {
128 	struct regmap_config map_cfg = {
129 		.reg_bits = 32,
130 		.val_bits = 32,
131 		.reg_stride = 4,
132 		.disable_locking = true,
133 		.reg_read = dw_reg_read,
134 		.reg_write = dw_reg_write,
135 		.max_register = DW_IC_COMP_TYPE,
136 	};
137 	u32 reg;
138 	int ret;
139 
140 	/*
141 	 * Skip detecting the registers map configuration if the regmap has
142 	 * already been provided by a higher code.
143 	 */
144 	if (dev->map)
145 		return 0;
146 
147 	ret = i2c_dw_acquire_lock(dev);
148 	if (ret)
149 		return ret;
150 
151 	reg = readl(dev->base + DW_IC_COMP_TYPE);
152 	i2c_dw_release_lock(dev);
153 
154 	if ((dev->flags & MODEL_MASK) == MODEL_AMD_NAVI_GPU)
155 		map_cfg.max_register = AMD_UCSI_INTR_REG;
156 
157 	if (reg == swab32(DW_IC_COMP_TYPE_VALUE)) {
158 		map_cfg.reg_read = dw_reg_read_swab;
159 		map_cfg.reg_write = dw_reg_write_swab;
160 	} else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
161 		map_cfg.reg_read = dw_reg_read_word;
162 		map_cfg.reg_write = dw_reg_write_word;
163 	} else if (reg != DW_IC_COMP_TYPE_VALUE) {
164 		dev_err(dev->dev,
165 			"Unknown Synopsys component type: 0x%08x\n", reg);
166 		return -ENODEV;
167 	}
168 
169 	/*
170 	 * Note we'll check the return value of the regmap IO accessors only
171 	 * at the probe stage. The rest of the code won't do this because
172 	 * basically we have MMIO-based regmap so non of the read/write methods
173 	 * can fail.
174 	 */
175 	dev->map = devm_regmap_init(dev->dev, NULL, dev, &map_cfg);
176 	if (IS_ERR(dev->map)) {
177 		dev_err(dev->dev, "Failed to init the registers map\n");
178 		return PTR_ERR(dev->map);
179 	}
180 
181 	return 0;
182 }
183 
184 static const u32 supported_speeds[] = {
185 	I2C_MAX_HIGH_SPEED_MODE_FREQ,
186 	I2C_MAX_FAST_MODE_PLUS_FREQ,
187 	I2C_MAX_FAST_MODE_FREQ,
188 	I2C_MAX_STANDARD_MODE_FREQ,
189 };
190 
191 int i2c_dw_validate_speed(struct dw_i2c_dev *dev)
192 {
193 	struct i2c_timings *t = &dev->timings;
194 	unsigned int i;
195 
196 	/*
197 	 * Only standard mode at 100kHz, fast mode at 400kHz,
198 	 * fast mode plus at 1MHz and high speed mode at 3.4MHz are supported.
199 	 */
200 	for (i = 0; i < ARRAY_SIZE(supported_speeds); i++) {
201 		if (t->bus_freq_hz == supported_speeds[i])
202 			return 0;
203 	}
204 
205 	dev_err(dev->dev,
206 		"%d Hz is unsupported, only 100kHz, 400kHz, 1MHz and 3.4MHz are supported\n",
207 		t->bus_freq_hz);
208 
209 	return -EINVAL;
210 }
211 EXPORT_SYMBOL_GPL(i2c_dw_validate_speed);
212 
213 #ifdef CONFIG_ACPI
214 
215 #include <linux/dmi.h>
216 
217 /*
218  * The HCNT/LCNT information coming from ACPI should be the most accurate
219  * for given platform. However, some systems get it wrong. On such systems
220  * we get better results by calculating those based on the input clock.
221  */
222 static const struct dmi_system_id i2c_dw_no_acpi_params[] = {
223 	{
224 		.ident = "Dell Inspiron 7348",
225 		.matches = {
226 			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
227 			DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 7348"),
228 		},
229 	},
230 	{}
231 };
232 
233 static void i2c_dw_acpi_params(struct device *device, char method[],
234 			       u16 *hcnt, u16 *lcnt, u32 *sda_hold)
235 {
236 	struct acpi_buffer buf = { ACPI_ALLOCATE_BUFFER };
237 	acpi_handle handle = ACPI_HANDLE(device);
238 	union acpi_object *obj;
239 
240 	if (dmi_check_system(i2c_dw_no_acpi_params))
241 		return;
242 
243 	if (ACPI_FAILURE(acpi_evaluate_object(handle, method, NULL, &buf)))
244 		return;
245 
246 	obj = (union acpi_object *)buf.pointer;
247 	if (obj->type == ACPI_TYPE_PACKAGE && obj->package.count == 3) {
248 		const union acpi_object *objs = obj->package.elements;
249 
250 		*hcnt = (u16)objs[0].integer.value;
251 		*lcnt = (u16)objs[1].integer.value;
252 		*sda_hold = (u32)objs[2].integer.value;
253 	}
254 
255 	kfree(buf.pointer);
256 }
257 
258 int i2c_dw_acpi_configure(struct device *device)
259 {
260 	struct dw_i2c_dev *dev = dev_get_drvdata(device);
261 	struct i2c_timings *t = &dev->timings;
262 	u32 ss_ht = 0, fp_ht = 0, hs_ht = 0, fs_ht = 0;
263 
264 	/*
265 	 * Try to get SDA hold time and *CNT values from an ACPI method for
266 	 * selected speed modes.
267 	 */
268 	i2c_dw_acpi_params(device, "SSCN", &dev->ss_hcnt, &dev->ss_lcnt, &ss_ht);
269 	i2c_dw_acpi_params(device, "FMCN", &dev->fs_hcnt, &dev->fs_lcnt, &fs_ht);
270 	i2c_dw_acpi_params(device, "FPCN", &dev->fp_hcnt, &dev->fp_lcnt, &fp_ht);
271 	i2c_dw_acpi_params(device, "HSCN", &dev->hs_hcnt, &dev->hs_lcnt, &hs_ht);
272 
273 	switch (t->bus_freq_hz) {
274 	case I2C_MAX_STANDARD_MODE_FREQ:
275 		dev->sda_hold_time = ss_ht;
276 		break;
277 	case I2C_MAX_FAST_MODE_PLUS_FREQ:
278 		dev->sda_hold_time = fp_ht;
279 		break;
280 	case I2C_MAX_HIGH_SPEED_MODE_FREQ:
281 		dev->sda_hold_time = hs_ht;
282 		break;
283 	case I2C_MAX_FAST_MODE_FREQ:
284 	default:
285 		dev->sda_hold_time = fs_ht;
286 		break;
287 	}
288 
289 	return 0;
290 }
291 EXPORT_SYMBOL_GPL(i2c_dw_acpi_configure);
292 
293 static u32 i2c_dw_acpi_round_bus_speed(struct device *device)
294 {
295 	u32 acpi_speed;
296 	int i;
297 
298 	acpi_speed = i2c_acpi_find_bus_speed(device);
299 	/*
300 	 * Some DSTDs use a non standard speed, round down to the lowest
301 	 * standard speed.
302 	 */
303 	for (i = 0; i < ARRAY_SIZE(supported_speeds); i++) {
304 		if (acpi_speed >= supported_speeds[i])
305 			return supported_speeds[i];
306 	}
307 
308 	return 0;
309 }
310 
311 #else	/* CONFIG_ACPI */
312 
313 static inline u32 i2c_dw_acpi_round_bus_speed(struct device *device) { return 0; }
314 
315 #endif	/* CONFIG_ACPI */
316 
317 void i2c_dw_adjust_bus_speed(struct dw_i2c_dev *dev)
318 {
319 	u32 acpi_speed = i2c_dw_acpi_round_bus_speed(dev->dev);
320 	struct i2c_timings *t = &dev->timings;
321 
322 	/*
323 	 * Find bus speed from the "clock-frequency" device property, ACPI
324 	 * or by using fast mode if neither is set.
325 	 */
326 	if (acpi_speed && t->bus_freq_hz)
327 		t->bus_freq_hz = min(t->bus_freq_hz, acpi_speed);
328 	else if (acpi_speed || t->bus_freq_hz)
329 		t->bus_freq_hz = max(t->bus_freq_hz, acpi_speed);
330 	else
331 		t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ;
332 }
333 EXPORT_SYMBOL_GPL(i2c_dw_adjust_bus_speed);
334 
335 u32 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset)
336 {
337 	/*
338 	 * DesignWare I2C core doesn't seem to have solid strategy to meet
339 	 * the tHD;STA timing spec.  Configuring _HCNT based on tHIGH spec
340 	 * will result in violation of the tHD;STA spec.
341 	 */
342 	if (cond)
343 		/*
344 		 * Conditional expression:
345 		 *
346 		 *   IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH
347 		 *
348 		 * This is based on the DW manuals, and represents an ideal
349 		 * configuration.  The resulting I2C bus speed will be
350 		 * faster than any of the others.
351 		 *
352 		 * If your hardware is free from tHD;STA issue, try this one.
353 		 */
354 		return DIV_ROUND_CLOSEST_ULL((u64)ic_clk * tSYMBOL, MICRO) -
355 		       8 + offset;
356 	else
357 		/*
358 		 * Conditional expression:
359 		 *
360 		 *   IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf)
361 		 *
362 		 * This is just experimental rule; the tHD;STA period turned
363 		 * out to be proportinal to (_HCNT + 3).  With this setting,
364 		 * we could meet both tHIGH and tHD;STA timing specs.
365 		 *
366 		 * If unsure, you'd better to take this alternative.
367 		 *
368 		 * The reason why we need to take into account "tf" here,
369 		 * is the same as described in i2c_dw_scl_lcnt().
370 		 */
371 		return DIV_ROUND_CLOSEST_ULL((u64)ic_clk * (tSYMBOL + tf), MICRO) -
372 		       3 + offset;
373 }
374 
375 u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset)
376 {
377 	/*
378 	 * Conditional expression:
379 	 *
380 	 *   IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf)
381 	 *
382 	 * DW I2C core starts counting the SCL CNTs for the LOW period
383 	 * of the SCL clock (tLOW) as soon as it pulls the SCL line.
384 	 * In order to meet the tLOW timing spec, we need to take into
385 	 * account the fall time of SCL signal (tf).  Default tf value
386 	 * should be 0.3 us, for safety.
387 	 */
388 	return DIV_ROUND_CLOSEST_ULL((u64)ic_clk * (tLOW + tf), MICRO) -
389 	       1 + offset;
390 }
391 
392 int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev)
393 {
394 	unsigned int reg;
395 	int ret;
396 
397 	ret = i2c_dw_acquire_lock(dev);
398 	if (ret)
399 		return ret;
400 
401 	/* Configure SDA Hold Time if required */
402 	ret = regmap_read(dev->map, DW_IC_COMP_VERSION, &reg);
403 	if (ret)
404 		goto err_release_lock;
405 
406 	if (reg >= DW_IC_SDA_HOLD_MIN_VERS) {
407 		if (!dev->sda_hold_time) {
408 			/* Keep previous hold time setting if no one set it */
409 			ret = regmap_read(dev->map, DW_IC_SDA_HOLD,
410 					  &dev->sda_hold_time);
411 			if (ret)
412 				goto err_release_lock;
413 		}
414 
415 		/*
416 		 * Workaround for avoiding TX arbitration lost in case I2C
417 		 * slave pulls SDA down "too quickly" after falling edge of
418 		 * SCL by enabling non-zero SDA RX hold. Specification says it
419 		 * extends incoming SDA low to high transition while SCL is
420 		 * high but it appears to help also above issue.
421 		 */
422 		if (!(dev->sda_hold_time & DW_IC_SDA_HOLD_RX_MASK))
423 			dev->sda_hold_time |= 1 << DW_IC_SDA_HOLD_RX_SHIFT;
424 
425 		dev_dbg(dev->dev, "SDA Hold Time TX:RX = %d:%d\n",
426 			dev->sda_hold_time & ~(u32)DW_IC_SDA_HOLD_RX_MASK,
427 			dev->sda_hold_time >> DW_IC_SDA_HOLD_RX_SHIFT);
428 	} else if (dev->set_sda_hold_time) {
429 		dev->set_sda_hold_time(dev);
430 	} else if (dev->sda_hold_time) {
431 		dev_warn(dev->dev,
432 			"Hardware too old to adjust SDA hold time.\n");
433 		dev->sda_hold_time = 0;
434 	}
435 
436 err_release_lock:
437 	i2c_dw_release_lock(dev);
438 
439 	return ret;
440 }
441 
442 void __i2c_dw_disable(struct dw_i2c_dev *dev)
443 {
444 	int timeout = 100;
445 	unsigned int status;
446 
447 	do {
448 		__i2c_dw_disable_nowait(dev);
449 		/*
450 		 * The enable status register may be unimplemented, but
451 		 * in that case this test reads zero and exits the loop.
452 		 */
453 		regmap_read(dev->map, DW_IC_ENABLE_STATUS, &status);
454 		if ((status & 1) == 0)
455 			return;
456 
457 		/*
458 		 * Wait 10 times the signaling period of the highest I2C
459 		 * transfer supported by the driver (for 400KHz this is
460 		 * 25us) as described in the DesignWare I2C databook.
461 		 */
462 		usleep_range(25, 250);
463 	} while (timeout--);
464 
465 	dev_warn(dev->dev, "timeout in disabling adapter\n");
466 }
467 
468 u32 i2c_dw_clk_rate(struct dw_i2c_dev *dev)
469 {
470 	/*
471 	 * Clock is not necessary if we got LCNT/HCNT values directly from
472 	 * the platform code.
473 	 */
474 	if (WARN_ON_ONCE(!dev->get_clk_rate_khz))
475 		return 0;
476 	return dev->get_clk_rate_khz(dev);
477 }
478 
479 int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare)
480 {
481 	int ret;
482 
483 	if (prepare) {
484 		/* Optional interface clock */
485 		ret = clk_prepare_enable(dev->pclk);
486 		if (ret)
487 			return ret;
488 
489 		ret = clk_prepare_enable(dev->clk);
490 		if (ret)
491 			clk_disable_unprepare(dev->pclk);
492 
493 		return ret;
494 	}
495 
496 	clk_disable_unprepare(dev->clk);
497 	clk_disable_unprepare(dev->pclk);
498 
499 	return 0;
500 }
501 EXPORT_SYMBOL_GPL(i2c_dw_prepare_clk);
502 
503 int i2c_dw_acquire_lock(struct dw_i2c_dev *dev)
504 {
505 	int ret;
506 
507 	if (!dev->acquire_lock)
508 		return 0;
509 
510 	ret = dev->acquire_lock();
511 	if (!ret)
512 		return 0;
513 
514 	dev_err(dev->dev, "couldn't acquire bus ownership\n");
515 
516 	return ret;
517 }
518 
519 void i2c_dw_release_lock(struct dw_i2c_dev *dev)
520 {
521 	if (dev->release_lock)
522 		dev->release_lock();
523 }
524 
525 /*
526  * Waiting for bus not busy
527  */
528 int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
529 {
530 	unsigned int status;
531 	int ret;
532 
533 	ret = regmap_read_poll_timeout(dev->map, DW_IC_STATUS, status,
534 				       !(status & DW_IC_STATUS_ACTIVITY),
535 				       1100, 20000);
536 	if (ret) {
537 		dev_warn(dev->dev, "timeout waiting for bus ready\n");
538 
539 		i2c_recover_bus(&dev->adapter);
540 
541 		regmap_read(dev->map, DW_IC_STATUS, &status);
542 		if (!(status & DW_IC_STATUS_ACTIVITY))
543 			ret = 0;
544 	}
545 
546 	return ret;
547 }
548 
549 int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev)
550 {
551 	unsigned long abort_source = dev->abort_source;
552 	int i;
553 
554 	if (abort_source & DW_IC_TX_ABRT_NOACK) {
555 		for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
556 			dev_dbg(dev->dev,
557 				"%s: %s\n", __func__, abort_sources[i]);
558 		return -EREMOTEIO;
559 	}
560 
561 	for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
562 		dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]);
563 
564 	if (abort_source & DW_IC_TX_ARB_LOST)
565 		return -EAGAIN;
566 	else if (abort_source & DW_IC_TX_ABRT_GCALL_READ)
567 		return -EINVAL; /* wrong msgs[] data */
568 	else
569 		return -EIO;
570 }
571 
572 int i2c_dw_set_fifo_size(struct dw_i2c_dev *dev)
573 {
574 	u32 tx_fifo_depth, rx_fifo_depth;
575 	unsigned int param;
576 	int ret;
577 
578 	/*
579 	 * Try to detect the FIFO depth if not set by interface driver,
580 	 * the depth could be from 2 to 256 from HW spec.
581 	 */
582 	ret = i2c_dw_acquire_lock(dev);
583 	if (ret)
584 		return ret;
585 
586 	ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, &param);
587 	i2c_dw_release_lock(dev);
588 	if (ret)
589 		return ret;
590 
591 	tx_fifo_depth = ((param >> 16) & 0xff) + 1;
592 	rx_fifo_depth = ((param >> 8)  & 0xff) + 1;
593 	if (!dev->tx_fifo_depth) {
594 		dev->tx_fifo_depth = tx_fifo_depth;
595 		dev->rx_fifo_depth = rx_fifo_depth;
596 	} else if (tx_fifo_depth >= 2) {
597 		dev->tx_fifo_depth = min_t(u32, dev->tx_fifo_depth,
598 				tx_fifo_depth);
599 		dev->rx_fifo_depth = min_t(u32, dev->rx_fifo_depth,
600 				rx_fifo_depth);
601 	}
602 
603 	return 0;
604 }
605 
606 u32 i2c_dw_func(struct i2c_adapter *adap)
607 {
608 	struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
609 
610 	return dev->functionality;
611 }
612 
613 void i2c_dw_disable(struct dw_i2c_dev *dev)
614 {
615 	unsigned int dummy;
616 	int ret;
617 
618 	ret = i2c_dw_acquire_lock(dev);
619 	if (ret)
620 		return;
621 
622 	/* Disable controller */
623 	__i2c_dw_disable(dev);
624 
625 	/* Disable all interrupts */
626 	regmap_write(dev->map, DW_IC_INTR_MASK, 0);
627 	regmap_read(dev->map, DW_IC_CLR_INTR, &dummy);
628 
629 	i2c_dw_release_lock(dev);
630 }
631 
632 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core");
633 MODULE_LICENSE("GPL");
634