1 /* 2 * TI DAVINCI I2C adapter driver. 3 * 4 * Copyright (C) 2006 Texas Instruments. 5 * Copyright (C) 2007 MontaVista Software Inc. 6 * 7 * Updated by Vinod & Sudhakar Feb 2005 8 * 9 * ---------------------------------------------------------------------------- 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 24 * ---------------------------------------------------------------------------- 25 * 26 */ 27 #include <linux/kernel.h> 28 #include <linux/module.h> 29 #include <linux/delay.h> 30 #include <linux/i2c.h> 31 #include <linux/clk.h> 32 #include <linux/errno.h> 33 #include <linux/sched.h> 34 #include <linux/err.h> 35 #include <linux/interrupt.h> 36 #include <linux/platform_device.h> 37 #include <linux/io.h> 38 #include <linux/slab.h> 39 #include <linux/cpufreq.h> 40 #include <linux/gpio.h> 41 #include <linux/of_device.h> 42 #include <linux/platform_data/i2c-davinci.h> 43 44 /* ----- global defines ----------------------------------------------- */ 45 46 #define DAVINCI_I2C_TIMEOUT (1*HZ) 47 #define DAVINCI_I2C_MAX_TRIES 2 48 #define I2C_DAVINCI_INTR_ALL (DAVINCI_I2C_IMR_AAS | \ 49 DAVINCI_I2C_IMR_SCD | \ 50 DAVINCI_I2C_IMR_ARDY | \ 51 DAVINCI_I2C_IMR_NACK | \ 52 DAVINCI_I2C_IMR_AL) 53 54 #define DAVINCI_I2C_OAR_REG 0x00 55 #define DAVINCI_I2C_IMR_REG 0x04 56 #define DAVINCI_I2C_STR_REG 0x08 57 #define DAVINCI_I2C_CLKL_REG 0x0c 58 #define DAVINCI_I2C_CLKH_REG 0x10 59 #define DAVINCI_I2C_CNT_REG 0x14 60 #define DAVINCI_I2C_DRR_REG 0x18 61 #define DAVINCI_I2C_SAR_REG 0x1c 62 #define DAVINCI_I2C_DXR_REG 0x20 63 #define DAVINCI_I2C_MDR_REG 0x24 64 #define DAVINCI_I2C_IVR_REG 0x28 65 #define DAVINCI_I2C_EMDR_REG 0x2c 66 #define DAVINCI_I2C_PSC_REG 0x30 67 68 #define DAVINCI_I2C_IVR_AAS 0x07 69 #define DAVINCI_I2C_IVR_SCD 0x06 70 #define DAVINCI_I2C_IVR_XRDY 0x05 71 #define DAVINCI_I2C_IVR_RDR 0x04 72 #define DAVINCI_I2C_IVR_ARDY 0x03 73 #define DAVINCI_I2C_IVR_NACK 0x02 74 #define DAVINCI_I2C_IVR_AL 0x01 75 76 #define DAVINCI_I2C_STR_BB BIT(12) 77 #define DAVINCI_I2C_STR_RSFULL BIT(11) 78 #define DAVINCI_I2C_STR_SCD BIT(5) 79 #define DAVINCI_I2C_STR_ARDY BIT(2) 80 #define DAVINCI_I2C_STR_NACK BIT(1) 81 #define DAVINCI_I2C_STR_AL BIT(0) 82 83 #define DAVINCI_I2C_MDR_NACK BIT(15) 84 #define DAVINCI_I2C_MDR_STT BIT(13) 85 #define DAVINCI_I2C_MDR_STP BIT(11) 86 #define DAVINCI_I2C_MDR_MST BIT(10) 87 #define DAVINCI_I2C_MDR_TRX BIT(9) 88 #define DAVINCI_I2C_MDR_XA BIT(8) 89 #define DAVINCI_I2C_MDR_RM BIT(7) 90 #define DAVINCI_I2C_MDR_IRS BIT(5) 91 92 #define DAVINCI_I2C_IMR_AAS BIT(6) 93 #define DAVINCI_I2C_IMR_SCD BIT(5) 94 #define DAVINCI_I2C_IMR_XRDY BIT(4) 95 #define DAVINCI_I2C_IMR_RRDY BIT(3) 96 #define DAVINCI_I2C_IMR_ARDY BIT(2) 97 #define DAVINCI_I2C_IMR_NACK BIT(1) 98 #define DAVINCI_I2C_IMR_AL BIT(0) 99 100 struct davinci_i2c_dev { 101 struct device *dev; 102 void __iomem *base; 103 struct completion cmd_complete; 104 struct clk *clk; 105 int cmd_err; 106 u8 *buf; 107 size_t buf_len; 108 int irq; 109 int stop; 110 u8 terminate; 111 struct i2c_adapter adapter; 112 #ifdef CONFIG_CPU_FREQ 113 struct completion xfr_complete; 114 struct notifier_block freq_transition; 115 #endif 116 struct davinci_i2c_platform_data *pdata; 117 }; 118 119 /* default platform data to use if not supplied in the platform_device */ 120 static struct davinci_i2c_platform_data davinci_i2c_platform_data_default = { 121 .bus_freq = 100, 122 .bus_delay = 0, 123 }; 124 125 static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev, 126 int reg, u16 val) 127 { 128 writew_relaxed(val, i2c_dev->base + reg); 129 } 130 131 static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg) 132 { 133 return readw_relaxed(i2c_dev->base + reg); 134 } 135 136 /* Generate a pulse on the i2c clock pin. */ 137 static void davinci_i2c_clock_pulse(unsigned int scl_pin) 138 { 139 u16 i; 140 141 if (scl_pin) { 142 /* Send high and low on the SCL line */ 143 for (i = 0; i < 9; i++) { 144 gpio_set_value(scl_pin, 0); 145 udelay(20); 146 gpio_set_value(scl_pin, 1); 147 udelay(20); 148 } 149 } 150 } 151 152 /* This routine does i2c bus recovery as specified in the 153 * i2c protocol Rev. 03 section 3.16 titled "Bus clear" 154 */ 155 static void davinci_i2c_recover_bus(struct davinci_i2c_dev *dev) 156 { 157 u32 flag = 0; 158 struct davinci_i2c_platform_data *pdata = dev->pdata; 159 160 dev_err(dev->dev, "initiating i2c bus recovery\n"); 161 /* Send NACK to the slave */ 162 flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); 163 flag |= DAVINCI_I2C_MDR_NACK; 164 /* write the data into mode register */ 165 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); 166 davinci_i2c_clock_pulse(pdata->scl_pin); 167 /* Send STOP */ 168 flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); 169 flag |= DAVINCI_I2C_MDR_STP; 170 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); 171 } 172 173 static inline void davinci_i2c_reset_ctrl(struct davinci_i2c_dev *i2c_dev, 174 int val) 175 { 176 u16 w; 177 178 w = davinci_i2c_read_reg(i2c_dev, DAVINCI_I2C_MDR_REG); 179 if (!val) /* put I2C into reset */ 180 w &= ~DAVINCI_I2C_MDR_IRS; 181 else /* take I2C out of reset */ 182 w |= DAVINCI_I2C_MDR_IRS; 183 184 davinci_i2c_write_reg(i2c_dev, DAVINCI_I2C_MDR_REG, w); 185 } 186 187 static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev) 188 { 189 struct davinci_i2c_platform_data *pdata = dev->pdata; 190 u16 psc; 191 u32 clk; 192 u32 d; 193 u32 clkh; 194 u32 clkl; 195 u32 input_clock = clk_get_rate(dev->clk); 196 197 /* NOTE: I2C Clock divider programming info 198 * As per I2C specs the following formulas provide prescaler 199 * and low/high divider values 200 * input clk --> PSC Div -----------> ICCL/H Div --> output clock 201 * module clk 202 * 203 * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ] 204 * 205 * Thus, 206 * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d; 207 * 208 * where if PSC == 0, d = 7, 209 * if PSC == 1, d = 6 210 * if PSC > 1 , d = 5 211 */ 212 213 /* get minimum of 7 MHz clock, but max of 12 MHz */ 214 psc = (input_clock / 7000000) - 1; 215 if ((input_clock / (psc + 1)) > 12000000) 216 psc++; /* better to run under spec than over */ 217 d = (psc >= 2) ? 5 : 7 - psc; 218 219 clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000)) - (d << 1); 220 clkh = clk >> 1; 221 clkl = clk - clkh; 222 223 davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc); 224 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh); 225 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl); 226 227 dev_dbg(dev->dev, "input_clock = %d, CLK = %d\n", input_clock, clk); 228 } 229 230 /* 231 * This function configures I2C and brings I2C out of reset. 232 * This function is called during I2C init function. This function 233 * also gets called if I2C encounters any errors. 234 */ 235 static int i2c_davinci_init(struct davinci_i2c_dev *dev) 236 { 237 struct davinci_i2c_platform_data *pdata = dev->pdata; 238 239 /* put I2C into reset */ 240 davinci_i2c_reset_ctrl(dev, 0); 241 242 /* compute clock dividers */ 243 i2c_davinci_calc_clk_dividers(dev); 244 245 /* Respond at reserved "SMBus Host" slave address" (and zero); 246 * we seem to have no option to not respond... 247 */ 248 davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, 0x08); 249 250 dev_dbg(dev->dev, "PSC = %d\n", 251 davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG)); 252 dev_dbg(dev->dev, "CLKL = %d\n", 253 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG)); 254 dev_dbg(dev->dev, "CLKH = %d\n", 255 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG)); 256 dev_dbg(dev->dev, "bus_freq = %dkHz, bus_delay = %d\n", 257 pdata->bus_freq, pdata->bus_delay); 258 259 260 /* Take the I2C module out of reset: */ 261 davinci_i2c_reset_ctrl(dev, 1); 262 263 /* Enable interrupts */ 264 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL); 265 266 return 0; 267 } 268 269 /* 270 * Waiting for bus not busy 271 */ 272 static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev, 273 char allow_sleep) 274 { 275 unsigned long timeout; 276 static u16 to_cnt; 277 278 timeout = jiffies + dev->adapter.timeout; 279 while (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) 280 & DAVINCI_I2C_STR_BB) { 281 if (to_cnt <= DAVINCI_I2C_MAX_TRIES) { 282 if (time_after(jiffies, timeout)) { 283 dev_warn(dev->dev, 284 "timeout waiting for bus ready\n"); 285 to_cnt++; 286 return -ETIMEDOUT; 287 } else { 288 to_cnt = 0; 289 davinci_i2c_recover_bus(dev); 290 i2c_davinci_init(dev); 291 } 292 } 293 if (allow_sleep) 294 schedule_timeout(1); 295 } 296 297 return 0; 298 } 299 300 /* 301 * Low level master read/write transaction. This function is called 302 * from i2c_davinci_xfer. 303 */ 304 static int 305 i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop) 306 { 307 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap); 308 struct davinci_i2c_platform_data *pdata = dev->pdata; 309 u32 flag; 310 u16 w; 311 int r; 312 313 /* Introduce a delay, required for some boards (e.g Davinci EVM) */ 314 if (pdata->bus_delay) 315 udelay(pdata->bus_delay); 316 317 /* set the slave address */ 318 davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr); 319 320 dev->buf = msg->buf; 321 dev->buf_len = msg->len; 322 dev->stop = stop; 323 324 davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len); 325 326 reinit_completion(&dev->cmd_complete); 327 dev->cmd_err = 0; 328 329 /* Take I2C out of reset and configure it as master */ 330 flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST; 331 332 /* if the slave address is ten bit address, enable XA bit */ 333 if (msg->flags & I2C_M_TEN) 334 flag |= DAVINCI_I2C_MDR_XA; 335 if (!(msg->flags & I2C_M_RD)) 336 flag |= DAVINCI_I2C_MDR_TRX; 337 if (msg->len == 0) 338 flag |= DAVINCI_I2C_MDR_RM; 339 340 /* Enable receive or transmit interrupts */ 341 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG); 342 if (msg->flags & I2C_M_RD) 343 w |= DAVINCI_I2C_IMR_RRDY; 344 else 345 w |= DAVINCI_I2C_IMR_XRDY; 346 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w); 347 348 dev->terminate = 0; 349 350 /* 351 * Write mode register first as needed for correct behaviour 352 * on OMAP-L138, but don't set STT yet to avoid a race with XRDY 353 * occurring before we have loaded DXR 354 */ 355 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); 356 357 /* 358 * First byte should be set here, not after interrupt, 359 * because transmit-data-ready interrupt can come before 360 * NACK-interrupt during sending of previous message and 361 * ICDXR may have wrong data 362 * It also saves us one interrupt, slightly faster 363 */ 364 if ((!(msg->flags & I2C_M_RD)) && dev->buf_len) { 365 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++); 366 dev->buf_len--; 367 } 368 369 /* Set STT to begin transmit now DXR is loaded */ 370 flag |= DAVINCI_I2C_MDR_STT; 371 if (stop && msg->len != 0) 372 flag |= DAVINCI_I2C_MDR_STP; 373 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); 374 375 r = wait_for_completion_interruptible_timeout(&dev->cmd_complete, 376 dev->adapter.timeout); 377 if (r == 0) { 378 dev_err(dev->dev, "controller timed out\n"); 379 davinci_i2c_recover_bus(dev); 380 i2c_davinci_init(dev); 381 dev->buf_len = 0; 382 return -ETIMEDOUT; 383 } 384 if (dev->buf_len) { 385 /* This should be 0 if all bytes were transferred 386 * or dev->cmd_err denotes an error. 387 * A signal may have aborted the transfer. 388 */ 389 if (r >= 0) { 390 dev_err(dev->dev, "abnormal termination buf_len=%i\n", 391 dev->buf_len); 392 r = -EREMOTEIO; 393 } 394 dev->terminate = 1; 395 wmb(); 396 dev->buf_len = 0; 397 } 398 if (r < 0) 399 return r; 400 401 /* no error */ 402 if (likely(!dev->cmd_err)) 403 return msg->len; 404 405 /* We have an error */ 406 if (dev->cmd_err & DAVINCI_I2C_STR_AL) { 407 i2c_davinci_init(dev); 408 return -EIO; 409 } 410 411 if (dev->cmd_err & DAVINCI_I2C_STR_NACK) { 412 if (msg->flags & I2C_M_IGNORE_NAK) 413 return msg->len; 414 if (stop) { 415 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); 416 w |= DAVINCI_I2C_MDR_STP; 417 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); 418 } 419 return -EREMOTEIO; 420 } 421 return -EIO; 422 } 423 424 /* 425 * Prepare controller for a transaction and call i2c_davinci_xfer_msg 426 */ 427 static int 428 i2c_davinci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) 429 { 430 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap); 431 int i; 432 int ret; 433 434 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); 435 436 ret = i2c_davinci_wait_bus_not_busy(dev, 1); 437 if (ret < 0) { 438 dev_warn(dev->dev, "timeout waiting for bus ready\n"); 439 return ret; 440 } 441 442 for (i = 0; i < num; i++) { 443 ret = i2c_davinci_xfer_msg(adap, &msgs[i], (i == (num - 1))); 444 dev_dbg(dev->dev, "%s [%d/%d] ret: %d\n", __func__, i + 1, num, 445 ret); 446 if (ret < 0) 447 return ret; 448 } 449 450 #ifdef CONFIG_CPU_FREQ 451 complete(&dev->xfr_complete); 452 #endif 453 454 return num; 455 } 456 457 static u32 i2c_davinci_func(struct i2c_adapter *adap) 458 { 459 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 460 } 461 462 static void terminate_read(struct davinci_i2c_dev *dev) 463 { 464 u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); 465 w |= DAVINCI_I2C_MDR_NACK; 466 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); 467 468 /* Throw away data */ 469 davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG); 470 if (!dev->terminate) 471 dev_err(dev->dev, "RDR IRQ while no data requested\n"); 472 } 473 static void terminate_write(struct davinci_i2c_dev *dev) 474 { 475 u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); 476 w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP; 477 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); 478 479 if (!dev->terminate) 480 dev_dbg(dev->dev, "TDR IRQ while no data to send\n"); 481 } 482 483 /* 484 * Interrupt service routine. This gets called whenever an I2C interrupt 485 * occurs. 486 */ 487 static irqreturn_t i2c_davinci_isr(int this_irq, void *dev_id) 488 { 489 struct davinci_i2c_dev *dev = dev_id; 490 u32 stat; 491 int count = 0; 492 u16 w; 493 494 while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) { 495 dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat); 496 if (count++ == 100) { 497 dev_warn(dev->dev, "Too much work in one IRQ\n"); 498 break; 499 } 500 501 switch (stat) { 502 case DAVINCI_I2C_IVR_AL: 503 /* Arbitration lost, must retry */ 504 dev->cmd_err |= DAVINCI_I2C_STR_AL; 505 dev->buf_len = 0; 506 complete(&dev->cmd_complete); 507 break; 508 509 case DAVINCI_I2C_IVR_NACK: 510 dev->cmd_err |= DAVINCI_I2C_STR_NACK; 511 dev->buf_len = 0; 512 complete(&dev->cmd_complete); 513 break; 514 515 case DAVINCI_I2C_IVR_ARDY: 516 davinci_i2c_write_reg(dev, 517 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY); 518 if (((dev->buf_len == 0) && (dev->stop != 0)) || 519 (dev->cmd_err & DAVINCI_I2C_STR_NACK)) { 520 w = davinci_i2c_read_reg(dev, 521 DAVINCI_I2C_MDR_REG); 522 w |= DAVINCI_I2C_MDR_STP; 523 davinci_i2c_write_reg(dev, 524 DAVINCI_I2C_MDR_REG, w); 525 } 526 complete(&dev->cmd_complete); 527 break; 528 529 case DAVINCI_I2C_IVR_RDR: 530 if (dev->buf_len) { 531 *dev->buf++ = 532 davinci_i2c_read_reg(dev, 533 DAVINCI_I2C_DRR_REG); 534 dev->buf_len--; 535 if (dev->buf_len) 536 continue; 537 538 davinci_i2c_write_reg(dev, 539 DAVINCI_I2C_STR_REG, 540 DAVINCI_I2C_IMR_RRDY); 541 } else { 542 /* signal can terminate transfer */ 543 terminate_read(dev); 544 } 545 break; 546 547 case DAVINCI_I2C_IVR_XRDY: 548 if (dev->buf_len) { 549 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, 550 *dev->buf++); 551 dev->buf_len--; 552 if (dev->buf_len) 553 continue; 554 555 w = davinci_i2c_read_reg(dev, 556 DAVINCI_I2C_IMR_REG); 557 w &= ~DAVINCI_I2C_IMR_XRDY; 558 davinci_i2c_write_reg(dev, 559 DAVINCI_I2C_IMR_REG, 560 w); 561 } else { 562 /* signal can terminate transfer */ 563 terminate_write(dev); 564 } 565 break; 566 567 case DAVINCI_I2C_IVR_SCD: 568 davinci_i2c_write_reg(dev, 569 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD); 570 complete(&dev->cmd_complete); 571 break; 572 573 case DAVINCI_I2C_IVR_AAS: 574 dev_dbg(dev->dev, "Address as slave interrupt\n"); 575 break; 576 577 default: 578 dev_warn(dev->dev, "Unrecognized irq stat %d\n", stat); 579 break; 580 } 581 } 582 583 return count ? IRQ_HANDLED : IRQ_NONE; 584 } 585 586 #ifdef CONFIG_CPU_FREQ 587 static int i2c_davinci_cpufreq_transition(struct notifier_block *nb, 588 unsigned long val, void *data) 589 { 590 struct davinci_i2c_dev *dev; 591 592 dev = container_of(nb, struct davinci_i2c_dev, freq_transition); 593 if (val == CPUFREQ_PRECHANGE) { 594 wait_for_completion(&dev->xfr_complete); 595 davinci_i2c_reset_ctrl(dev, 0); 596 } else if (val == CPUFREQ_POSTCHANGE) { 597 i2c_davinci_calc_clk_dividers(dev); 598 davinci_i2c_reset_ctrl(dev, 1); 599 } 600 601 return 0; 602 } 603 604 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev) 605 { 606 dev->freq_transition.notifier_call = i2c_davinci_cpufreq_transition; 607 608 return cpufreq_register_notifier(&dev->freq_transition, 609 CPUFREQ_TRANSITION_NOTIFIER); 610 } 611 612 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev) 613 { 614 cpufreq_unregister_notifier(&dev->freq_transition, 615 CPUFREQ_TRANSITION_NOTIFIER); 616 } 617 #else 618 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev) 619 { 620 return 0; 621 } 622 623 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev) 624 { 625 } 626 #endif 627 628 static struct i2c_algorithm i2c_davinci_algo = { 629 .master_xfer = i2c_davinci_xfer, 630 .functionality = i2c_davinci_func, 631 }; 632 633 static const struct of_device_id davinci_i2c_of_match[] = { 634 {.compatible = "ti,davinci-i2c", }, 635 {}, 636 }; 637 MODULE_DEVICE_TABLE(of, davinci_i2c_of_match); 638 639 static int davinci_i2c_probe(struct platform_device *pdev) 640 { 641 struct davinci_i2c_dev *dev; 642 struct i2c_adapter *adap; 643 struct resource *mem, *irq; 644 int r; 645 646 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 647 if (!irq) { 648 dev_err(&pdev->dev, "no irq resource?\n"); 649 return -ENODEV; 650 } 651 652 dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_i2c_dev), 653 GFP_KERNEL); 654 if (!dev) { 655 dev_err(&pdev->dev, "Memory allocation failed\n"); 656 return -ENOMEM; 657 } 658 659 init_completion(&dev->cmd_complete); 660 #ifdef CONFIG_CPU_FREQ 661 init_completion(&dev->xfr_complete); 662 #endif 663 dev->dev = &pdev->dev; 664 dev->irq = irq->start; 665 dev->pdata = dev_get_platdata(&pdev->dev); 666 platform_set_drvdata(pdev, dev); 667 668 if (!dev->pdata && pdev->dev.of_node) { 669 u32 prop; 670 671 dev->pdata = devm_kzalloc(&pdev->dev, 672 sizeof(struct davinci_i2c_platform_data), GFP_KERNEL); 673 if (!dev->pdata) 674 return -ENOMEM; 675 676 memcpy(dev->pdata, &davinci_i2c_platform_data_default, 677 sizeof(struct davinci_i2c_platform_data)); 678 if (!of_property_read_u32(pdev->dev.of_node, "clock-frequency", 679 &prop)) 680 dev->pdata->bus_freq = prop / 1000; 681 } else if (!dev->pdata) { 682 dev->pdata = &davinci_i2c_platform_data_default; 683 } 684 685 dev->clk = devm_clk_get(&pdev->dev, NULL); 686 if (IS_ERR(dev->clk)) 687 return -ENODEV; 688 clk_prepare_enable(dev->clk); 689 690 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 691 dev->base = devm_ioremap_resource(&pdev->dev, mem); 692 if (IS_ERR(dev->base)) { 693 r = PTR_ERR(dev->base); 694 goto err_unuse_clocks; 695 } 696 697 i2c_davinci_init(dev); 698 699 r = devm_request_irq(&pdev->dev, dev->irq, i2c_davinci_isr, 0, 700 pdev->name, dev); 701 if (r) { 702 dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq); 703 goto err_unuse_clocks; 704 } 705 706 r = i2c_davinci_cpufreq_register(dev); 707 if (r) { 708 dev_err(&pdev->dev, "failed to register cpufreq\n"); 709 goto err_unuse_clocks; 710 } 711 712 adap = &dev->adapter; 713 i2c_set_adapdata(adap, dev); 714 adap->owner = THIS_MODULE; 715 adap->class = I2C_CLASS_DEPRECATED; 716 strlcpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name)); 717 adap->algo = &i2c_davinci_algo; 718 adap->dev.parent = &pdev->dev; 719 adap->timeout = DAVINCI_I2C_TIMEOUT; 720 adap->dev.of_node = pdev->dev.of_node; 721 722 adap->nr = pdev->id; 723 r = i2c_add_numbered_adapter(adap); 724 if (r) { 725 dev_err(&pdev->dev, "failure adding adapter\n"); 726 goto err_unuse_clocks; 727 } 728 729 return 0; 730 731 err_unuse_clocks: 732 clk_disable_unprepare(dev->clk); 733 dev->clk = NULL; 734 return r; 735 } 736 737 static int davinci_i2c_remove(struct platform_device *pdev) 738 { 739 struct davinci_i2c_dev *dev = platform_get_drvdata(pdev); 740 741 i2c_davinci_cpufreq_deregister(dev); 742 743 i2c_del_adapter(&dev->adapter); 744 745 clk_disable_unprepare(dev->clk); 746 dev->clk = NULL; 747 748 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, 0); 749 750 return 0; 751 } 752 753 #ifdef CONFIG_PM 754 static int davinci_i2c_suspend(struct device *dev) 755 { 756 struct platform_device *pdev = to_platform_device(dev); 757 struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 758 759 /* put I2C into reset */ 760 davinci_i2c_reset_ctrl(i2c_dev, 0); 761 clk_disable_unprepare(i2c_dev->clk); 762 763 return 0; 764 } 765 766 static int davinci_i2c_resume(struct device *dev) 767 { 768 struct platform_device *pdev = to_platform_device(dev); 769 struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 770 771 clk_prepare_enable(i2c_dev->clk); 772 /* take I2C out of reset */ 773 davinci_i2c_reset_ctrl(i2c_dev, 1); 774 775 return 0; 776 } 777 778 static const struct dev_pm_ops davinci_i2c_pm = { 779 .suspend = davinci_i2c_suspend, 780 .resume = davinci_i2c_resume, 781 }; 782 783 #define davinci_i2c_pm_ops (&davinci_i2c_pm) 784 #else 785 #define davinci_i2c_pm_ops NULL 786 #endif 787 788 /* work with hotplug and coldplug */ 789 MODULE_ALIAS("platform:i2c_davinci"); 790 791 static struct platform_driver davinci_i2c_driver = { 792 .probe = davinci_i2c_probe, 793 .remove = davinci_i2c_remove, 794 .driver = { 795 .name = "i2c_davinci", 796 .owner = THIS_MODULE, 797 .pm = davinci_i2c_pm_ops, 798 .of_match_table = davinci_i2c_of_match, 799 }, 800 }; 801 802 /* I2C may be needed to bring up other drivers */ 803 static int __init davinci_i2c_init_driver(void) 804 { 805 return platform_driver_register(&davinci_i2c_driver); 806 } 807 subsys_initcall(davinci_i2c_init_driver); 808 809 static void __exit davinci_i2c_exit_driver(void) 810 { 811 platform_driver_unregister(&davinci_i2c_driver); 812 } 813 module_exit(davinci_i2c_exit_driver); 814 815 MODULE_AUTHOR("Texas Instruments India"); 816 MODULE_DESCRIPTION("TI DaVinci I2C bus adapter"); 817 MODULE_LICENSE("GPL"); 818