1 /* 2 * TI DAVINCI I2C adapter driver. 3 * 4 * Copyright (C) 2006 Texas Instruments. 5 * Copyright (C) 2007 MontaVista Software Inc. 6 * 7 * Updated by Vinod & Sudhakar Feb 2005 8 * 9 * ---------------------------------------------------------------------------- 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * ---------------------------------------------------------------------------- 21 * 22 */ 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/delay.h> 26 #include <linux/i2c.h> 27 #include <linux/clk.h> 28 #include <linux/errno.h> 29 #include <linux/sched.h> 30 #include <linux/err.h> 31 #include <linux/interrupt.h> 32 #include <linux/platform_device.h> 33 #include <linux/io.h> 34 #include <linux/slab.h> 35 #include <linux/cpufreq.h> 36 #include <linux/gpio.h> 37 #include <linux/of_device.h> 38 #include <linux/platform_data/i2c-davinci.h> 39 #include <linux/pm_runtime.h> 40 41 /* ----- global defines ----------------------------------------------- */ 42 43 #define DAVINCI_I2C_TIMEOUT (1*HZ) 44 #define DAVINCI_I2C_MAX_TRIES 2 45 #define DAVINCI_I2C_OWN_ADDRESS 0x08 46 #define I2C_DAVINCI_INTR_ALL (DAVINCI_I2C_IMR_SCD | \ 47 DAVINCI_I2C_IMR_ARDY | \ 48 DAVINCI_I2C_IMR_NACK | \ 49 DAVINCI_I2C_IMR_AL) 50 51 #define DAVINCI_I2C_OAR_REG 0x00 52 #define DAVINCI_I2C_IMR_REG 0x04 53 #define DAVINCI_I2C_STR_REG 0x08 54 #define DAVINCI_I2C_CLKL_REG 0x0c 55 #define DAVINCI_I2C_CLKH_REG 0x10 56 #define DAVINCI_I2C_CNT_REG 0x14 57 #define DAVINCI_I2C_DRR_REG 0x18 58 #define DAVINCI_I2C_SAR_REG 0x1c 59 #define DAVINCI_I2C_DXR_REG 0x20 60 #define DAVINCI_I2C_MDR_REG 0x24 61 #define DAVINCI_I2C_IVR_REG 0x28 62 #define DAVINCI_I2C_EMDR_REG 0x2c 63 #define DAVINCI_I2C_PSC_REG 0x30 64 #define DAVINCI_I2C_FUNC_REG 0x48 65 #define DAVINCI_I2C_DIR_REG 0x4c 66 #define DAVINCI_I2C_DIN_REG 0x50 67 #define DAVINCI_I2C_DOUT_REG 0x54 68 #define DAVINCI_I2C_DSET_REG 0x58 69 #define DAVINCI_I2C_DCLR_REG 0x5c 70 71 #define DAVINCI_I2C_IVR_AAS 0x07 72 #define DAVINCI_I2C_IVR_SCD 0x06 73 #define DAVINCI_I2C_IVR_XRDY 0x05 74 #define DAVINCI_I2C_IVR_RDR 0x04 75 #define DAVINCI_I2C_IVR_ARDY 0x03 76 #define DAVINCI_I2C_IVR_NACK 0x02 77 #define DAVINCI_I2C_IVR_AL 0x01 78 79 #define DAVINCI_I2C_STR_BB BIT(12) 80 #define DAVINCI_I2C_STR_RSFULL BIT(11) 81 #define DAVINCI_I2C_STR_SCD BIT(5) 82 #define DAVINCI_I2C_STR_ARDY BIT(2) 83 #define DAVINCI_I2C_STR_NACK BIT(1) 84 #define DAVINCI_I2C_STR_AL BIT(0) 85 86 #define DAVINCI_I2C_MDR_NACK BIT(15) 87 #define DAVINCI_I2C_MDR_STT BIT(13) 88 #define DAVINCI_I2C_MDR_STP BIT(11) 89 #define DAVINCI_I2C_MDR_MST BIT(10) 90 #define DAVINCI_I2C_MDR_TRX BIT(9) 91 #define DAVINCI_I2C_MDR_XA BIT(8) 92 #define DAVINCI_I2C_MDR_RM BIT(7) 93 #define DAVINCI_I2C_MDR_IRS BIT(5) 94 95 #define DAVINCI_I2C_IMR_AAS BIT(6) 96 #define DAVINCI_I2C_IMR_SCD BIT(5) 97 #define DAVINCI_I2C_IMR_XRDY BIT(4) 98 #define DAVINCI_I2C_IMR_RRDY BIT(3) 99 #define DAVINCI_I2C_IMR_ARDY BIT(2) 100 #define DAVINCI_I2C_IMR_NACK BIT(1) 101 #define DAVINCI_I2C_IMR_AL BIT(0) 102 103 /* set SDA and SCL as GPIO */ 104 #define DAVINCI_I2C_FUNC_PFUNC0 BIT(0) 105 106 /* set SCL as output when used as GPIO*/ 107 #define DAVINCI_I2C_DIR_PDIR0 BIT(0) 108 /* set SDA as output when used as GPIO*/ 109 #define DAVINCI_I2C_DIR_PDIR1 BIT(1) 110 111 /* read SCL GPIO level */ 112 #define DAVINCI_I2C_DIN_PDIN0 BIT(0) 113 /* read SDA GPIO level */ 114 #define DAVINCI_I2C_DIN_PDIN1 BIT(1) 115 116 /*set the SCL GPIO high */ 117 #define DAVINCI_I2C_DSET_PDSET0 BIT(0) 118 /*set the SDA GPIO high */ 119 #define DAVINCI_I2C_DSET_PDSET1 BIT(1) 120 121 /* set the SCL GPIO low */ 122 #define DAVINCI_I2C_DCLR_PDCLR0 BIT(0) 123 /* set the SDA GPIO low */ 124 #define DAVINCI_I2C_DCLR_PDCLR1 BIT(1) 125 126 /* timeout for pm runtime autosuspend */ 127 #define DAVINCI_I2C_PM_TIMEOUT 1000 /* ms */ 128 129 struct davinci_i2c_dev { 130 struct device *dev; 131 void __iomem *base; 132 struct completion cmd_complete; 133 struct clk *clk; 134 int cmd_err; 135 u8 *buf; 136 size_t buf_len; 137 int irq; 138 int stop; 139 u8 terminate; 140 struct i2c_adapter adapter; 141 #ifdef CONFIG_CPU_FREQ 142 struct completion xfr_complete; 143 struct notifier_block freq_transition; 144 #endif 145 struct davinci_i2c_platform_data *pdata; 146 }; 147 148 /* default platform data to use if not supplied in the platform_device */ 149 static struct davinci_i2c_platform_data davinci_i2c_platform_data_default = { 150 .bus_freq = 100, 151 .bus_delay = 0, 152 }; 153 154 static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev, 155 int reg, u16 val) 156 { 157 writew_relaxed(val, i2c_dev->base + reg); 158 } 159 160 static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg) 161 { 162 return readw_relaxed(i2c_dev->base + reg); 163 } 164 165 static inline void davinci_i2c_reset_ctrl(struct davinci_i2c_dev *i2c_dev, 166 int val) 167 { 168 u16 w; 169 170 w = davinci_i2c_read_reg(i2c_dev, DAVINCI_I2C_MDR_REG); 171 if (!val) /* put I2C into reset */ 172 w &= ~DAVINCI_I2C_MDR_IRS; 173 else /* take I2C out of reset */ 174 w |= DAVINCI_I2C_MDR_IRS; 175 176 davinci_i2c_write_reg(i2c_dev, DAVINCI_I2C_MDR_REG, w); 177 } 178 179 static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev) 180 { 181 struct davinci_i2c_platform_data *pdata = dev->pdata; 182 u16 psc; 183 u32 clk; 184 u32 d; 185 u32 clkh; 186 u32 clkl; 187 u32 input_clock = clk_get_rate(dev->clk); 188 struct device_node *of_node = dev->dev->of_node; 189 190 /* NOTE: I2C Clock divider programming info 191 * As per I2C specs the following formulas provide prescaler 192 * and low/high divider values 193 * input clk --> PSC Div -----------> ICCL/H Div --> output clock 194 * module clk 195 * 196 * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ] 197 * 198 * Thus, 199 * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d; 200 * 201 * where if PSC == 0, d = 7, 202 * if PSC == 1, d = 6 203 * if PSC > 1 , d = 5 204 * 205 * Note: 206 * d is always 6 on Keystone I2C controller 207 */ 208 209 /* 210 * Both Davinci and current Keystone User Guides recommend a value 211 * between 7MHz and 12MHz. In reality 7MHz module clock doesn't 212 * always produce enough margin between SDA and SCL transitions. 213 * Measurements show that the higher the module clock is, the 214 * bigger is the margin, providing more reliable communication. 215 * So we better target for 12MHz. 216 */ 217 psc = (input_clock / 12000000) - 1; 218 if ((input_clock / (psc + 1)) > 12000000) 219 psc++; /* better to run under spec than over */ 220 d = (psc >= 2) ? 5 : 7 - psc; 221 222 if (of_node && of_device_is_compatible(of_node, "ti,keystone-i2c")) 223 d = 6; 224 225 clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000)); 226 /* Avoid driving the bus too fast because of rounding errors above */ 227 if (input_clock / (psc + 1) / clk > pdata->bus_freq * 1000) 228 clk++; 229 /* 230 * According to I2C-BUS Spec 2.1, in FAST-MODE LOW period should be at 231 * least 1.3uS, which is not the case with 50% duty cycle. Driving HIGH 232 * to LOW ratio as 1 to 2 is more safe. 233 */ 234 if (pdata->bus_freq > 100) 235 clkl = (clk << 1) / 3; 236 else 237 clkl = (clk >> 1); 238 /* 239 * It's not always possible to have 1 to 2 ratio when d=7, so fall back 240 * to minimal possible clkh in this case. 241 */ 242 if (clk >= clkl + d) { 243 clkh = clk - clkl - d; 244 clkl -= d; 245 } else { 246 clkh = 0; 247 clkl = clk - (d << 1); 248 } 249 250 davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc); 251 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh); 252 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl); 253 254 dev_dbg(dev->dev, "input_clock = %d, CLK = %d\n", input_clock, clk); 255 } 256 257 /* 258 * This function configures I2C and brings I2C out of reset. 259 * This function is called during I2C init function. This function 260 * also gets called if I2C encounters any errors. 261 */ 262 static int i2c_davinci_init(struct davinci_i2c_dev *dev) 263 { 264 struct davinci_i2c_platform_data *pdata = dev->pdata; 265 266 /* put I2C into reset */ 267 davinci_i2c_reset_ctrl(dev, 0); 268 269 /* compute clock dividers */ 270 i2c_davinci_calc_clk_dividers(dev); 271 272 /* Respond at reserved "SMBus Host" slave address" (and zero); 273 * we seem to have no option to not respond... 274 */ 275 davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, DAVINCI_I2C_OWN_ADDRESS); 276 277 dev_dbg(dev->dev, "PSC = %d\n", 278 davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG)); 279 dev_dbg(dev->dev, "CLKL = %d\n", 280 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG)); 281 dev_dbg(dev->dev, "CLKH = %d\n", 282 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG)); 283 dev_dbg(dev->dev, "bus_freq = %dkHz, bus_delay = %d\n", 284 pdata->bus_freq, pdata->bus_delay); 285 286 287 /* Take the I2C module out of reset: */ 288 davinci_i2c_reset_ctrl(dev, 1); 289 290 /* Enable interrupts */ 291 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL); 292 293 return 0; 294 } 295 296 /* 297 * This routine does i2c bus recovery by using i2c_generic_gpio_recovery 298 * which is provided by I2C Bus recovery infrastructure. 299 */ 300 static void davinci_i2c_prepare_recovery(struct i2c_adapter *adap) 301 { 302 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap); 303 304 /* Disable interrupts */ 305 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, 0); 306 307 /* put I2C into reset */ 308 davinci_i2c_reset_ctrl(dev, 0); 309 } 310 311 static void davinci_i2c_unprepare_recovery(struct i2c_adapter *adap) 312 { 313 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap); 314 315 i2c_davinci_init(dev); 316 } 317 318 static struct i2c_bus_recovery_info davinci_i2c_gpio_recovery_info = { 319 .recover_bus = i2c_generic_gpio_recovery, 320 .prepare_recovery = davinci_i2c_prepare_recovery, 321 .unprepare_recovery = davinci_i2c_unprepare_recovery, 322 }; 323 324 static void davinci_i2c_set_scl(struct i2c_adapter *adap, int val) 325 { 326 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap); 327 328 if (val) 329 davinci_i2c_write_reg(dev, DAVINCI_I2C_DSET_REG, 330 DAVINCI_I2C_DSET_PDSET0); 331 else 332 davinci_i2c_write_reg(dev, DAVINCI_I2C_DCLR_REG, 333 DAVINCI_I2C_DCLR_PDCLR0); 334 } 335 336 static int davinci_i2c_get_scl(struct i2c_adapter *adap) 337 { 338 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap); 339 int val; 340 341 /* read the state of SCL */ 342 val = davinci_i2c_read_reg(dev, DAVINCI_I2C_DIN_REG); 343 return val & DAVINCI_I2C_DIN_PDIN0; 344 } 345 346 static int davinci_i2c_get_sda(struct i2c_adapter *adap) 347 { 348 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap); 349 int val; 350 351 /* read the state of SDA */ 352 val = davinci_i2c_read_reg(dev, DAVINCI_I2C_DIN_REG); 353 return val & DAVINCI_I2C_DIN_PDIN1; 354 } 355 356 static void davinci_i2c_scl_prepare_recovery(struct i2c_adapter *adap) 357 { 358 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap); 359 360 davinci_i2c_prepare_recovery(adap); 361 362 /* SCL output, SDA input */ 363 davinci_i2c_write_reg(dev, DAVINCI_I2C_DIR_REG, DAVINCI_I2C_DIR_PDIR0); 364 365 /* change to GPIO mode */ 366 davinci_i2c_write_reg(dev, DAVINCI_I2C_FUNC_REG, 367 DAVINCI_I2C_FUNC_PFUNC0); 368 } 369 370 static void davinci_i2c_scl_unprepare_recovery(struct i2c_adapter *adap) 371 { 372 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap); 373 374 /* change back to I2C mode */ 375 davinci_i2c_write_reg(dev, DAVINCI_I2C_FUNC_REG, 0); 376 377 davinci_i2c_unprepare_recovery(adap); 378 } 379 380 static struct i2c_bus_recovery_info davinci_i2c_scl_recovery_info = { 381 .recover_bus = i2c_generic_scl_recovery, 382 .set_scl = davinci_i2c_set_scl, 383 .get_scl = davinci_i2c_get_scl, 384 .get_sda = davinci_i2c_get_sda, 385 .prepare_recovery = davinci_i2c_scl_prepare_recovery, 386 .unprepare_recovery = davinci_i2c_scl_unprepare_recovery, 387 }; 388 389 /* 390 * Waiting for bus not busy 391 */ 392 static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev) 393 { 394 unsigned long timeout = jiffies + dev->adapter.timeout; 395 396 do { 397 if (!(davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) & DAVINCI_I2C_STR_BB)) 398 return 0; 399 schedule_timeout_uninterruptible(1); 400 } while (time_before_eq(jiffies, timeout)); 401 402 dev_warn(dev->dev, "timeout waiting for bus ready\n"); 403 i2c_recover_bus(&dev->adapter); 404 405 /* 406 * if bus is still "busy" here, it's most probably a HW problem like 407 * short-circuit 408 */ 409 if (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) & DAVINCI_I2C_STR_BB) 410 return -EIO; 411 412 return 0; 413 } 414 415 /* 416 * Low level master read/write transaction. This function is called 417 * from i2c_davinci_xfer. 418 */ 419 static int 420 i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop) 421 { 422 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap); 423 struct davinci_i2c_platform_data *pdata = dev->pdata; 424 u32 flag; 425 u16 w; 426 unsigned long time_left; 427 428 if (msg->addr == DAVINCI_I2C_OWN_ADDRESS) { 429 dev_warn(dev->dev, "transfer to own address aborted\n"); 430 return -EADDRNOTAVAIL; 431 } 432 433 /* Introduce a delay, required for some boards (e.g Davinci EVM) */ 434 if (pdata->bus_delay) 435 udelay(pdata->bus_delay); 436 437 /* set the slave address */ 438 davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr); 439 440 dev->buf = msg->buf; 441 dev->buf_len = msg->len; 442 dev->stop = stop; 443 444 davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len); 445 446 reinit_completion(&dev->cmd_complete); 447 dev->cmd_err = 0; 448 449 /* Take I2C out of reset and configure it as master */ 450 flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST; 451 452 /* if the slave address is ten bit address, enable XA bit */ 453 if (msg->flags & I2C_M_TEN) 454 flag |= DAVINCI_I2C_MDR_XA; 455 if (!(msg->flags & I2C_M_RD)) 456 flag |= DAVINCI_I2C_MDR_TRX; 457 if (msg->len == 0) 458 flag |= DAVINCI_I2C_MDR_RM; 459 460 /* Enable receive or transmit interrupts */ 461 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG); 462 if (msg->flags & I2C_M_RD) 463 w |= DAVINCI_I2C_IMR_RRDY; 464 else 465 w |= DAVINCI_I2C_IMR_XRDY; 466 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w); 467 468 dev->terminate = 0; 469 470 /* 471 * Write mode register first as needed for correct behaviour 472 * on OMAP-L138, but don't set STT yet to avoid a race with XRDY 473 * occurring before we have loaded DXR 474 */ 475 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); 476 477 /* 478 * First byte should be set here, not after interrupt, 479 * because transmit-data-ready interrupt can come before 480 * NACK-interrupt during sending of previous message and 481 * ICDXR may have wrong data 482 * It also saves us one interrupt, slightly faster 483 */ 484 if ((!(msg->flags & I2C_M_RD)) && dev->buf_len) { 485 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++); 486 dev->buf_len--; 487 } 488 489 /* Set STT to begin transmit now DXR is loaded */ 490 flag |= DAVINCI_I2C_MDR_STT; 491 if (stop && msg->len != 0) 492 flag |= DAVINCI_I2C_MDR_STP; 493 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); 494 495 time_left = wait_for_completion_timeout(&dev->cmd_complete, 496 dev->adapter.timeout); 497 if (!time_left) { 498 dev_err(dev->dev, "controller timed out\n"); 499 i2c_recover_bus(adap); 500 dev->buf_len = 0; 501 return -ETIMEDOUT; 502 } 503 if (dev->buf_len) { 504 /* This should be 0 if all bytes were transferred 505 * or dev->cmd_err denotes an error. 506 */ 507 dev_err(dev->dev, "abnormal termination buf_len=%zu\n", 508 dev->buf_len); 509 dev->terminate = 1; 510 wmb(); 511 dev->buf_len = 0; 512 return -EREMOTEIO; 513 } 514 515 /* no error */ 516 if (likely(!dev->cmd_err)) 517 return msg->len; 518 519 /* We have an error */ 520 if (dev->cmd_err & DAVINCI_I2C_STR_AL) { 521 i2c_davinci_init(dev); 522 return -EIO; 523 } 524 525 if (dev->cmd_err & DAVINCI_I2C_STR_NACK) { 526 if (msg->flags & I2C_M_IGNORE_NAK) 527 return msg->len; 528 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); 529 w |= DAVINCI_I2C_MDR_STP; 530 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); 531 return -EREMOTEIO; 532 } 533 return -EIO; 534 } 535 536 /* 537 * Prepare controller for a transaction and call i2c_davinci_xfer_msg 538 */ 539 static int 540 i2c_davinci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) 541 { 542 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap); 543 int i; 544 int ret; 545 546 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); 547 548 ret = pm_runtime_get_sync(dev->dev); 549 if (ret < 0) { 550 dev_err(dev->dev, "Failed to runtime_get device: %d\n", ret); 551 pm_runtime_put_noidle(dev->dev); 552 return ret; 553 } 554 555 ret = i2c_davinci_wait_bus_not_busy(dev); 556 if (ret < 0) { 557 dev_warn(dev->dev, "timeout waiting for bus ready\n"); 558 goto out; 559 } 560 561 for (i = 0; i < num; i++) { 562 ret = i2c_davinci_xfer_msg(adap, &msgs[i], (i == (num - 1))); 563 dev_dbg(dev->dev, "%s [%d/%d] ret: %d\n", __func__, i + 1, num, 564 ret); 565 if (ret < 0) 566 goto out; 567 } 568 569 ret = num; 570 #ifdef CONFIG_CPU_FREQ 571 complete(&dev->xfr_complete); 572 #endif 573 574 out: 575 pm_runtime_mark_last_busy(dev->dev); 576 pm_runtime_put_autosuspend(dev->dev); 577 578 return ret; 579 } 580 581 static u32 i2c_davinci_func(struct i2c_adapter *adap) 582 { 583 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 584 } 585 586 static void terminate_read(struct davinci_i2c_dev *dev) 587 { 588 u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); 589 w |= DAVINCI_I2C_MDR_NACK; 590 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); 591 592 /* Throw away data */ 593 davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG); 594 if (!dev->terminate) 595 dev_err(dev->dev, "RDR IRQ while no data requested\n"); 596 } 597 static void terminate_write(struct davinci_i2c_dev *dev) 598 { 599 u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); 600 w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP; 601 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); 602 603 if (!dev->terminate) 604 dev_dbg(dev->dev, "TDR IRQ while no data to send\n"); 605 } 606 607 /* 608 * Interrupt service routine. This gets called whenever an I2C interrupt 609 * occurs. 610 */ 611 static irqreturn_t i2c_davinci_isr(int this_irq, void *dev_id) 612 { 613 struct davinci_i2c_dev *dev = dev_id; 614 u32 stat; 615 int count = 0; 616 u16 w; 617 618 if (pm_runtime_suspended(dev->dev)) 619 return IRQ_NONE; 620 621 while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) { 622 dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat); 623 if (count++ == 100) { 624 dev_warn(dev->dev, "Too much work in one IRQ\n"); 625 break; 626 } 627 628 switch (stat) { 629 case DAVINCI_I2C_IVR_AL: 630 /* Arbitration lost, must retry */ 631 dev->cmd_err |= DAVINCI_I2C_STR_AL; 632 dev->buf_len = 0; 633 complete(&dev->cmd_complete); 634 break; 635 636 case DAVINCI_I2C_IVR_NACK: 637 dev->cmd_err |= DAVINCI_I2C_STR_NACK; 638 dev->buf_len = 0; 639 complete(&dev->cmd_complete); 640 break; 641 642 case DAVINCI_I2C_IVR_ARDY: 643 davinci_i2c_write_reg(dev, 644 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY); 645 if (((dev->buf_len == 0) && (dev->stop != 0)) || 646 (dev->cmd_err & DAVINCI_I2C_STR_NACK)) { 647 w = davinci_i2c_read_reg(dev, 648 DAVINCI_I2C_MDR_REG); 649 w |= DAVINCI_I2C_MDR_STP; 650 davinci_i2c_write_reg(dev, 651 DAVINCI_I2C_MDR_REG, w); 652 } 653 complete(&dev->cmd_complete); 654 break; 655 656 case DAVINCI_I2C_IVR_RDR: 657 if (dev->buf_len) { 658 *dev->buf++ = 659 davinci_i2c_read_reg(dev, 660 DAVINCI_I2C_DRR_REG); 661 dev->buf_len--; 662 if (dev->buf_len) 663 continue; 664 665 davinci_i2c_write_reg(dev, 666 DAVINCI_I2C_STR_REG, 667 DAVINCI_I2C_IMR_RRDY); 668 } else { 669 /* signal can terminate transfer */ 670 terminate_read(dev); 671 } 672 break; 673 674 case DAVINCI_I2C_IVR_XRDY: 675 if (dev->buf_len) { 676 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, 677 *dev->buf++); 678 dev->buf_len--; 679 if (dev->buf_len) 680 continue; 681 682 w = davinci_i2c_read_reg(dev, 683 DAVINCI_I2C_IMR_REG); 684 w &= ~DAVINCI_I2C_IMR_XRDY; 685 davinci_i2c_write_reg(dev, 686 DAVINCI_I2C_IMR_REG, 687 w); 688 } else { 689 /* signal can terminate transfer */ 690 terminate_write(dev); 691 } 692 break; 693 694 case DAVINCI_I2C_IVR_SCD: 695 davinci_i2c_write_reg(dev, 696 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD); 697 complete(&dev->cmd_complete); 698 break; 699 700 case DAVINCI_I2C_IVR_AAS: 701 dev_dbg(dev->dev, "Address as slave interrupt\n"); 702 break; 703 704 default: 705 dev_warn(dev->dev, "Unrecognized irq stat %d\n", stat); 706 break; 707 } 708 } 709 710 return count ? IRQ_HANDLED : IRQ_NONE; 711 } 712 713 #ifdef CONFIG_CPU_FREQ 714 static int i2c_davinci_cpufreq_transition(struct notifier_block *nb, 715 unsigned long val, void *data) 716 { 717 struct davinci_i2c_dev *dev; 718 719 dev = container_of(nb, struct davinci_i2c_dev, freq_transition); 720 if (val == CPUFREQ_PRECHANGE) { 721 wait_for_completion(&dev->xfr_complete); 722 davinci_i2c_reset_ctrl(dev, 0); 723 } else if (val == CPUFREQ_POSTCHANGE) { 724 i2c_davinci_calc_clk_dividers(dev); 725 davinci_i2c_reset_ctrl(dev, 1); 726 } 727 728 return 0; 729 } 730 731 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev) 732 { 733 dev->freq_transition.notifier_call = i2c_davinci_cpufreq_transition; 734 735 return cpufreq_register_notifier(&dev->freq_transition, 736 CPUFREQ_TRANSITION_NOTIFIER); 737 } 738 739 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev) 740 { 741 cpufreq_unregister_notifier(&dev->freq_transition, 742 CPUFREQ_TRANSITION_NOTIFIER); 743 } 744 #else 745 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev) 746 { 747 return 0; 748 } 749 750 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev) 751 { 752 } 753 #endif 754 755 static const struct i2c_algorithm i2c_davinci_algo = { 756 .master_xfer = i2c_davinci_xfer, 757 .functionality = i2c_davinci_func, 758 }; 759 760 static const struct of_device_id davinci_i2c_of_match[] = { 761 {.compatible = "ti,davinci-i2c", }, 762 {.compatible = "ti,keystone-i2c", }, 763 {}, 764 }; 765 MODULE_DEVICE_TABLE(of, davinci_i2c_of_match); 766 767 static int davinci_i2c_probe(struct platform_device *pdev) 768 { 769 struct davinci_i2c_dev *dev; 770 struct i2c_adapter *adap; 771 struct resource *mem; 772 int r, irq; 773 774 irq = platform_get_irq(pdev, 0); 775 if (irq <= 0) { 776 if (!irq) 777 irq = -ENXIO; 778 if (irq != -EPROBE_DEFER) 779 dev_err(&pdev->dev, 780 "can't get irq resource ret=%d\n", irq); 781 return irq; 782 } 783 784 dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_i2c_dev), 785 GFP_KERNEL); 786 if (!dev) { 787 dev_err(&pdev->dev, "Memory allocation failed\n"); 788 return -ENOMEM; 789 } 790 791 init_completion(&dev->cmd_complete); 792 #ifdef CONFIG_CPU_FREQ 793 init_completion(&dev->xfr_complete); 794 #endif 795 dev->dev = &pdev->dev; 796 dev->irq = irq; 797 dev->pdata = dev_get_platdata(&pdev->dev); 798 platform_set_drvdata(pdev, dev); 799 800 if (!dev->pdata && pdev->dev.of_node) { 801 u32 prop; 802 803 dev->pdata = devm_kzalloc(&pdev->dev, 804 sizeof(struct davinci_i2c_platform_data), GFP_KERNEL); 805 if (!dev->pdata) 806 return -ENOMEM; 807 808 memcpy(dev->pdata, &davinci_i2c_platform_data_default, 809 sizeof(struct davinci_i2c_platform_data)); 810 if (!of_property_read_u32(pdev->dev.of_node, "clock-frequency", 811 &prop)) 812 dev->pdata->bus_freq = prop / 1000; 813 814 dev->pdata->has_pfunc = 815 of_property_read_bool(pdev->dev.of_node, 816 "ti,has-pfunc"); 817 } else if (!dev->pdata) { 818 dev->pdata = &davinci_i2c_platform_data_default; 819 } 820 821 dev->clk = devm_clk_get(&pdev->dev, NULL); 822 if (IS_ERR(dev->clk)) 823 return PTR_ERR(dev->clk); 824 825 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 826 dev->base = devm_ioremap_resource(&pdev->dev, mem); 827 if (IS_ERR(dev->base)) { 828 return PTR_ERR(dev->base); 829 } 830 831 pm_runtime_set_autosuspend_delay(dev->dev, 832 DAVINCI_I2C_PM_TIMEOUT); 833 pm_runtime_use_autosuspend(dev->dev); 834 835 pm_runtime_enable(dev->dev); 836 837 r = pm_runtime_get_sync(dev->dev); 838 if (r < 0) { 839 dev_err(dev->dev, "failed to runtime_get device: %d\n", r); 840 pm_runtime_put_noidle(dev->dev); 841 return r; 842 } 843 844 i2c_davinci_init(dev); 845 846 r = devm_request_irq(&pdev->dev, dev->irq, i2c_davinci_isr, 0, 847 pdev->name, dev); 848 if (r) { 849 dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq); 850 goto err_unuse_clocks; 851 } 852 853 r = i2c_davinci_cpufreq_register(dev); 854 if (r) { 855 dev_err(&pdev->dev, "failed to register cpufreq\n"); 856 goto err_unuse_clocks; 857 } 858 859 adap = &dev->adapter; 860 i2c_set_adapdata(adap, dev); 861 adap->owner = THIS_MODULE; 862 adap->class = I2C_CLASS_DEPRECATED; 863 strlcpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name)); 864 adap->algo = &i2c_davinci_algo; 865 adap->dev.parent = &pdev->dev; 866 adap->timeout = DAVINCI_I2C_TIMEOUT; 867 adap->dev.of_node = pdev->dev.of_node; 868 869 if (dev->pdata->has_pfunc) 870 adap->bus_recovery_info = &davinci_i2c_scl_recovery_info; 871 else if (dev->pdata->scl_pin) { 872 adap->bus_recovery_info = &davinci_i2c_gpio_recovery_info; 873 adap->bus_recovery_info->scl_gpio = dev->pdata->scl_pin; 874 adap->bus_recovery_info->sda_gpio = dev->pdata->sda_pin; 875 } 876 877 adap->nr = pdev->id; 878 r = i2c_add_numbered_adapter(adap); 879 if (r) 880 goto err_unuse_clocks; 881 882 pm_runtime_mark_last_busy(dev->dev); 883 pm_runtime_put_autosuspend(dev->dev); 884 885 return 0; 886 887 err_unuse_clocks: 888 pm_runtime_dont_use_autosuspend(dev->dev); 889 pm_runtime_put_sync(dev->dev); 890 pm_runtime_disable(dev->dev); 891 892 return r; 893 } 894 895 static int davinci_i2c_remove(struct platform_device *pdev) 896 { 897 struct davinci_i2c_dev *dev = platform_get_drvdata(pdev); 898 int ret; 899 900 i2c_davinci_cpufreq_deregister(dev); 901 902 i2c_del_adapter(&dev->adapter); 903 904 ret = pm_runtime_get_sync(&pdev->dev); 905 if (ret < 0) { 906 pm_runtime_put_noidle(&pdev->dev); 907 return ret; 908 } 909 910 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, 0); 911 912 pm_runtime_dont_use_autosuspend(dev->dev); 913 pm_runtime_put_sync(dev->dev); 914 pm_runtime_disable(dev->dev); 915 916 return 0; 917 } 918 919 #ifdef CONFIG_PM 920 static int davinci_i2c_suspend(struct device *dev) 921 { 922 struct davinci_i2c_dev *i2c_dev = dev_get_drvdata(dev); 923 924 /* put I2C into reset */ 925 davinci_i2c_reset_ctrl(i2c_dev, 0); 926 927 return 0; 928 } 929 930 static int davinci_i2c_resume(struct device *dev) 931 { 932 struct davinci_i2c_dev *i2c_dev = dev_get_drvdata(dev); 933 934 /* take I2C out of reset */ 935 davinci_i2c_reset_ctrl(i2c_dev, 1); 936 937 return 0; 938 } 939 940 static const struct dev_pm_ops davinci_i2c_pm = { 941 .suspend = davinci_i2c_suspend, 942 .resume = davinci_i2c_resume, 943 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 944 pm_runtime_force_resume) 945 }; 946 947 #define davinci_i2c_pm_ops (&davinci_i2c_pm) 948 #else 949 #define davinci_i2c_pm_ops NULL 950 #endif 951 952 /* work with hotplug and coldplug */ 953 MODULE_ALIAS("platform:i2c_davinci"); 954 955 static struct platform_driver davinci_i2c_driver = { 956 .probe = davinci_i2c_probe, 957 .remove = davinci_i2c_remove, 958 .driver = { 959 .name = "i2c_davinci", 960 .pm = davinci_i2c_pm_ops, 961 .of_match_table = davinci_i2c_of_match, 962 }, 963 }; 964 965 /* I2C may be needed to bring up other drivers */ 966 static int __init davinci_i2c_init_driver(void) 967 { 968 return platform_driver_register(&davinci_i2c_driver); 969 } 970 subsys_initcall(davinci_i2c_init_driver); 971 972 static void __exit davinci_i2c_exit_driver(void) 973 { 974 platform_driver_unregister(&davinci_i2c_driver); 975 } 976 module_exit(davinci_i2c_exit_driver); 977 978 MODULE_AUTHOR("Texas Instruments India"); 979 MODULE_DESCRIPTION("TI DaVinci I2C bus adapter"); 980 MODULE_LICENSE("GPL"); 981