1 /* 2 * TI DAVINCI I2C adapter driver. 3 * 4 * Copyright (C) 2006 Texas Instruments. 5 * Copyright (C) 2007 MontaVista Software Inc. 6 * 7 * Updated by Vinod & Sudhakar Feb 2005 8 * 9 * ---------------------------------------------------------------------------- 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * ---------------------------------------------------------------------------- 21 * 22 */ 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/delay.h> 26 #include <linux/i2c.h> 27 #include <linux/clk.h> 28 #include <linux/errno.h> 29 #include <linux/sched.h> 30 #include <linux/err.h> 31 #include <linux/interrupt.h> 32 #include <linux/platform_device.h> 33 #include <linux/io.h> 34 #include <linux/slab.h> 35 #include <linux/cpufreq.h> 36 #include <linux/gpio/consumer.h> 37 #include <linux/of_device.h> 38 #include <linux/platform_data/i2c-davinci.h> 39 #include <linux/pm_runtime.h> 40 41 /* ----- global defines ----------------------------------------------- */ 42 43 #define DAVINCI_I2C_TIMEOUT (1*HZ) 44 #define DAVINCI_I2C_MAX_TRIES 2 45 #define DAVINCI_I2C_OWN_ADDRESS 0x08 46 #define I2C_DAVINCI_INTR_ALL (DAVINCI_I2C_IMR_SCD | \ 47 DAVINCI_I2C_IMR_ARDY | \ 48 DAVINCI_I2C_IMR_NACK | \ 49 DAVINCI_I2C_IMR_AL) 50 51 #define DAVINCI_I2C_OAR_REG 0x00 52 #define DAVINCI_I2C_IMR_REG 0x04 53 #define DAVINCI_I2C_STR_REG 0x08 54 #define DAVINCI_I2C_CLKL_REG 0x0c 55 #define DAVINCI_I2C_CLKH_REG 0x10 56 #define DAVINCI_I2C_CNT_REG 0x14 57 #define DAVINCI_I2C_DRR_REG 0x18 58 #define DAVINCI_I2C_SAR_REG 0x1c 59 #define DAVINCI_I2C_DXR_REG 0x20 60 #define DAVINCI_I2C_MDR_REG 0x24 61 #define DAVINCI_I2C_IVR_REG 0x28 62 #define DAVINCI_I2C_EMDR_REG 0x2c 63 #define DAVINCI_I2C_PSC_REG 0x30 64 #define DAVINCI_I2C_FUNC_REG 0x48 65 #define DAVINCI_I2C_DIR_REG 0x4c 66 #define DAVINCI_I2C_DIN_REG 0x50 67 #define DAVINCI_I2C_DOUT_REG 0x54 68 #define DAVINCI_I2C_DSET_REG 0x58 69 #define DAVINCI_I2C_DCLR_REG 0x5c 70 71 #define DAVINCI_I2C_IVR_AAS 0x07 72 #define DAVINCI_I2C_IVR_SCD 0x06 73 #define DAVINCI_I2C_IVR_XRDY 0x05 74 #define DAVINCI_I2C_IVR_RDR 0x04 75 #define DAVINCI_I2C_IVR_ARDY 0x03 76 #define DAVINCI_I2C_IVR_NACK 0x02 77 #define DAVINCI_I2C_IVR_AL 0x01 78 79 #define DAVINCI_I2C_STR_BB BIT(12) 80 #define DAVINCI_I2C_STR_RSFULL BIT(11) 81 #define DAVINCI_I2C_STR_SCD BIT(5) 82 #define DAVINCI_I2C_STR_ARDY BIT(2) 83 #define DAVINCI_I2C_STR_NACK BIT(1) 84 #define DAVINCI_I2C_STR_AL BIT(0) 85 86 #define DAVINCI_I2C_MDR_NACK BIT(15) 87 #define DAVINCI_I2C_MDR_STT BIT(13) 88 #define DAVINCI_I2C_MDR_STP BIT(11) 89 #define DAVINCI_I2C_MDR_MST BIT(10) 90 #define DAVINCI_I2C_MDR_TRX BIT(9) 91 #define DAVINCI_I2C_MDR_XA BIT(8) 92 #define DAVINCI_I2C_MDR_RM BIT(7) 93 #define DAVINCI_I2C_MDR_IRS BIT(5) 94 95 #define DAVINCI_I2C_IMR_AAS BIT(6) 96 #define DAVINCI_I2C_IMR_SCD BIT(5) 97 #define DAVINCI_I2C_IMR_XRDY BIT(4) 98 #define DAVINCI_I2C_IMR_RRDY BIT(3) 99 #define DAVINCI_I2C_IMR_ARDY BIT(2) 100 #define DAVINCI_I2C_IMR_NACK BIT(1) 101 #define DAVINCI_I2C_IMR_AL BIT(0) 102 103 /* set SDA and SCL as GPIO */ 104 #define DAVINCI_I2C_FUNC_PFUNC0 BIT(0) 105 106 /* set SCL as output when used as GPIO*/ 107 #define DAVINCI_I2C_DIR_PDIR0 BIT(0) 108 /* set SDA as output when used as GPIO*/ 109 #define DAVINCI_I2C_DIR_PDIR1 BIT(1) 110 111 /* read SCL GPIO level */ 112 #define DAVINCI_I2C_DIN_PDIN0 BIT(0) 113 /* read SDA GPIO level */ 114 #define DAVINCI_I2C_DIN_PDIN1 BIT(1) 115 116 /*set the SCL GPIO high */ 117 #define DAVINCI_I2C_DSET_PDSET0 BIT(0) 118 /*set the SDA GPIO high */ 119 #define DAVINCI_I2C_DSET_PDSET1 BIT(1) 120 121 /* set the SCL GPIO low */ 122 #define DAVINCI_I2C_DCLR_PDCLR0 BIT(0) 123 /* set the SDA GPIO low */ 124 #define DAVINCI_I2C_DCLR_PDCLR1 BIT(1) 125 126 /* timeout for pm runtime autosuspend */ 127 #define DAVINCI_I2C_PM_TIMEOUT 1000 /* ms */ 128 129 struct davinci_i2c_dev { 130 struct device *dev; 131 void __iomem *base; 132 struct completion cmd_complete; 133 struct clk *clk; 134 int cmd_err; 135 u8 *buf; 136 size_t buf_len; 137 int irq; 138 int stop; 139 u8 terminate; 140 struct i2c_adapter adapter; 141 #ifdef CONFIG_CPU_FREQ 142 struct notifier_block freq_transition; 143 #endif 144 struct davinci_i2c_platform_data *pdata; 145 }; 146 147 /* default platform data to use if not supplied in the platform_device */ 148 static struct davinci_i2c_platform_data davinci_i2c_platform_data_default = { 149 .bus_freq = 100, 150 .bus_delay = 0, 151 }; 152 153 static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev, 154 int reg, u16 val) 155 { 156 writew_relaxed(val, i2c_dev->base + reg); 157 } 158 159 static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg) 160 { 161 return readw_relaxed(i2c_dev->base + reg); 162 } 163 164 static inline void davinci_i2c_reset_ctrl(struct davinci_i2c_dev *i2c_dev, 165 int val) 166 { 167 u16 w; 168 169 w = davinci_i2c_read_reg(i2c_dev, DAVINCI_I2C_MDR_REG); 170 if (!val) /* put I2C into reset */ 171 w &= ~DAVINCI_I2C_MDR_IRS; 172 else /* take I2C out of reset */ 173 w |= DAVINCI_I2C_MDR_IRS; 174 175 davinci_i2c_write_reg(i2c_dev, DAVINCI_I2C_MDR_REG, w); 176 } 177 178 static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev) 179 { 180 struct davinci_i2c_platform_data *pdata = dev->pdata; 181 u16 psc; 182 u32 clk; 183 u32 d; 184 u32 clkh; 185 u32 clkl; 186 u32 input_clock = clk_get_rate(dev->clk); 187 struct device_node *of_node = dev->dev->of_node; 188 189 /* NOTE: I2C Clock divider programming info 190 * As per I2C specs the following formulas provide prescaler 191 * and low/high divider values 192 * input clk --> PSC Div -----------> ICCL/H Div --> output clock 193 * module clk 194 * 195 * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ] 196 * 197 * Thus, 198 * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d; 199 * 200 * where if PSC == 0, d = 7, 201 * if PSC == 1, d = 6 202 * if PSC > 1 , d = 5 203 * 204 * Note: 205 * d is always 6 on Keystone I2C controller 206 */ 207 208 /* 209 * Both Davinci and current Keystone User Guides recommend a value 210 * between 7MHz and 12MHz. In reality 7MHz module clock doesn't 211 * always produce enough margin between SDA and SCL transitions. 212 * Measurements show that the higher the module clock is, the 213 * bigger is the margin, providing more reliable communication. 214 * So we better target for 12MHz. 215 */ 216 psc = (input_clock / 12000000) - 1; 217 if ((input_clock / (psc + 1)) > 12000000) 218 psc++; /* better to run under spec than over */ 219 d = (psc >= 2) ? 5 : 7 - psc; 220 221 if (of_node && of_device_is_compatible(of_node, "ti,keystone-i2c")) 222 d = 6; 223 224 clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000)); 225 /* Avoid driving the bus too fast because of rounding errors above */ 226 if (input_clock / (psc + 1) / clk > pdata->bus_freq * 1000) 227 clk++; 228 /* 229 * According to I2C-BUS Spec 2.1, in FAST-MODE LOW period should be at 230 * least 1.3uS, which is not the case with 50% duty cycle. Driving HIGH 231 * to LOW ratio as 1 to 2 is more safe. 232 */ 233 if (pdata->bus_freq > 100) 234 clkl = (clk << 1) / 3; 235 else 236 clkl = (clk >> 1); 237 /* 238 * It's not always possible to have 1 to 2 ratio when d=7, so fall back 239 * to minimal possible clkh in this case. 240 */ 241 if (clk >= clkl + d) { 242 clkh = clk - clkl - d; 243 clkl -= d; 244 } else { 245 clkh = 0; 246 clkl = clk - (d << 1); 247 } 248 249 davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc); 250 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh); 251 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl); 252 253 dev_dbg(dev->dev, "input_clock = %d, CLK = %d\n", input_clock, clk); 254 } 255 256 /* 257 * This function configures I2C and brings I2C out of reset. 258 * This function is called during I2C init function. This function 259 * also gets called if I2C encounters any errors. 260 */ 261 static int i2c_davinci_init(struct davinci_i2c_dev *dev) 262 { 263 struct davinci_i2c_platform_data *pdata = dev->pdata; 264 265 /* put I2C into reset */ 266 davinci_i2c_reset_ctrl(dev, 0); 267 268 /* compute clock dividers */ 269 i2c_davinci_calc_clk_dividers(dev); 270 271 /* Respond at reserved "SMBus Host" slave address" (and zero); 272 * we seem to have no option to not respond... 273 */ 274 davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, DAVINCI_I2C_OWN_ADDRESS); 275 276 dev_dbg(dev->dev, "PSC = %d\n", 277 davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG)); 278 dev_dbg(dev->dev, "CLKL = %d\n", 279 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG)); 280 dev_dbg(dev->dev, "CLKH = %d\n", 281 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG)); 282 dev_dbg(dev->dev, "bus_freq = %dkHz, bus_delay = %d\n", 283 pdata->bus_freq, pdata->bus_delay); 284 285 286 /* Take the I2C module out of reset: */ 287 davinci_i2c_reset_ctrl(dev, 1); 288 289 /* Enable interrupts */ 290 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL); 291 292 return 0; 293 } 294 295 /* 296 * This routine does i2c bus recovery by using i2c_generic_scl_recovery 297 * which is provided by I2C Bus recovery infrastructure. 298 */ 299 static void davinci_i2c_prepare_recovery(struct i2c_adapter *adap) 300 { 301 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap); 302 303 /* Disable interrupts */ 304 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, 0); 305 306 /* put I2C into reset */ 307 davinci_i2c_reset_ctrl(dev, 0); 308 } 309 310 static void davinci_i2c_unprepare_recovery(struct i2c_adapter *adap) 311 { 312 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap); 313 314 i2c_davinci_init(dev); 315 } 316 317 static struct i2c_bus_recovery_info davinci_i2c_gpio_recovery_info = { 318 .recover_bus = i2c_generic_scl_recovery, 319 .prepare_recovery = davinci_i2c_prepare_recovery, 320 .unprepare_recovery = davinci_i2c_unprepare_recovery, 321 }; 322 323 static void davinci_i2c_set_scl(struct i2c_adapter *adap, int val) 324 { 325 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap); 326 327 if (val) 328 davinci_i2c_write_reg(dev, DAVINCI_I2C_DSET_REG, 329 DAVINCI_I2C_DSET_PDSET0); 330 else 331 davinci_i2c_write_reg(dev, DAVINCI_I2C_DCLR_REG, 332 DAVINCI_I2C_DCLR_PDCLR0); 333 } 334 335 static int davinci_i2c_get_scl(struct i2c_adapter *adap) 336 { 337 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap); 338 int val; 339 340 /* read the state of SCL */ 341 val = davinci_i2c_read_reg(dev, DAVINCI_I2C_DIN_REG); 342 return val & DAVINCI_I2C_DIN_PDIN0; 343 } 344 345 static int davinci_i2c_get_sda(struct i2c_adapter *adap) 346 { 347 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap); 348 int val; 349 350 /* read the state of SDA */ 351 val = davinci_i2c_read_reg(dev, DAVINCI_I2C_DIN_REG); 352 return val & DAVINCI_I2C_DIN_PDIN1; 353 } 354 355 static void davinci_i2c_scl_prepare_recovery(struct i2c_adapter *adap) 356 { 357 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap); 358 359 davinci_i2c_prepare_recovery(adap); 360 361 /* SCL output, SDA input */ 362 davinci_i2c_write_reg(dev, DAVINCI_I2C_DIR_REG, DAVINCI_I2C_DIR_PDIR0); 363 364 /* change to GPIO mode */ 365 davinci_i2c_write_reg(dev, DAVINCI_I2C_FUNC_REG, 366 DAVINCI_I2C_FUNC_PFUNC0); 367 } 368 369 static void davinci_i2c_scl_unprepare_recovery(struct i2c_adapter *adap) 370 { 371 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap); 372 373 /* change back to I2C mode */ 374 davinci_i2c_write_reg(dev, DAVINCI_I2C_FUNC_REG, 0); 375 376 davinci_i2c_unprepare_recovery(adap); 377 } 378 379 static struct i2c_bus_recovery_info davinci_i2c_scl_recovery_info = { 380 .recover_bus = i2c_generic_scl_recovery, 381 .set_scl = davinci_i2c_set_scl, 382 .get_scl = davinci_i2c_get_scl, 383 .get_sda = davinci_i2c_get_sda, 384 .prepare_recovery = davinci_i2c_scl_prepare_recovery, 385 .unprepare_recovery = davinci_i2c_scl_unprepare_recovery, 386 }; 387 388 /* 389 * Waiting for bus not busy 390 */ 391 static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev) 392 { 393 unsigned long timeout = jiffies + dev->adapter.timeout; 394 395 do { 396 if (!(davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) & DAVINCI_I2C_STR_BB)) 397 return 0; 398 schedule_timeout_uninterruptible(1); 399 } while (time_before_eq(jiffies, timeout)); 400 401 dev_warn(dev->dev, "timeout waiting for bus ready\n"); 402 i2c_recover_bus(&dev->adapter); 403 404 /* 405 * if bus is still "busy" here, it's most probably a HW problem like 406 * short-circuit 407 */ 408 if (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) & DAVINCI_I2C_STR_BB) 409 return -EIO; 410 411 return 0; 412 } 413 414 /* 415 * Low level master read/write transaction. This function is called 416 * from i2c_davinci_xfer. 417 */ 418 static int 419 i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop) 420 { 421 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap); 422 struct davinci_i2c_platform_data *pdata = dev->pdata; 423 u32 flag; 424 u16 w; 425 unsigned long time_left; 426 427 if (msg->addr == DAVINCI_I2C_OWN_ADDRESS) { 428 dev_warn(dev->dev, "transfer to own address aborted\n"); 429 return -EADDRNOTAVAIL; 430 } 431 432 /* Introduce a delay, required for some boards (e.g Davinci EVM) */ 433 if (pdata->bus_delay) 434 udelay(pdata->bus_delay); 435 436 /* set the slave address */ 437 davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr); 438 439 dev->buf = msg->buf; 440 dev->buf_len = msg->len; 441 dev->stop = stop; 442 443 davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len); 444 445 reinit_completion(&dev->cmd_complete); 446 dev->cmd_err = 0; 447 448 /* Take I2C out of reset and configure it as master */ 449 flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST; 450 451 /* if the slave address is ten bit address, enable XA bit */ 452 if (msg->flags & I2C_M_TEN) 453 flag |= DAVINCI_I2C_MDR_XA; 454 if (!(msg->flags & I2C_M_RD)) 455 flag |= DAVINCI_I2C_MDR_TRX; 456 if (msg->len == 0) 457 flag |= DAVINCI_I2C_MDR_RM; 458 459 /* Enable receive or transmit interrupts */ 460 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG); 461 if (msg->flags & I2C_M_RD) 462 w |= DAVINCI_I2C_IMR_RRDY; 463 else 464 w |= DAVINCI_I2C_IMR_XRDY; 465 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w); 466 467 dev->terminate = 0; 468 469 /* 470 * Write mode register first as needed for correct behaviour 471 * on OMAP-L138, but don't set STT yet to avoid a race with XRDY 472 * occurring before we have loaded DXR 473 */ 474 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); 475 476 /* 477 * First byte should be set here, not after interrupt, 478 * because transmit-data-ready interrupt can come before 479 * NACK-interrupt during sending of previous message and 480 * ICDXR may have wrong data 481 * It also saves us one interrupt, slightly faster 482 */ 483 if ((!(msg->flags & I2C_M_RD)) && dev->buf_len) { 484 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++); 485 dev->buf_len--; 486 } 487 488 /* Set STT to begin transmit now DXR is loaded */ 489 flag |= DAVINCI_I2C_MDR_STT; 490 if (stop && msg->len != 0) 491 flag |= DAVINCI_I2C_MDR_STP; 492 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); 493 494 time_left = wait_for_completion_timeout(&dev->cmd_complete, 495 dev->adapter.timeout); 496 if (!time_left) { 497 dev_err(dev->dev, "controller timed out\n"); 498 i2c_recover_bus(adap); 499 dev->buf_len = 0; 500 return -ETIMEDOUT; 501 } 502 if (dev->buf_len) { 503 /* This should be 0 if all bytes were transferred 504 * or dev->cmd_err denotes an error. 505 */ 506 dev_err(dev->dev, "abnormal termination buf_len=%zu\n", 507 dev->buf_len); 508 dev->terminate = 1; 509 wmb(); 510 dev->buf_len = 0; 511 return -EREMOTEIO; 512 } 513 514 /* no error */ 515 if (likely(!dev->cmd_err)) 516 return msg->len; 517 518 /* We have an error */ 519 if (dev->cmd_err & DAVINCI_I2C_STR_AL) { 520 i2c_davinci_init(dev); 521 return -EIO; 522 } 523 524 if (dev->cmd_err & DAVINCI_I2C_STR_NACK) { 525 if (msg->flags & I2C_M_IGNORE_NAK) 526 return msg->len; 527 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); 528 w |= DAVINCI_I2C_MDR_STP; 529 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); 530 return -EREMOTEIO; 531 } 532 return -EIO; 533 } 534 535 /* 536 * Prepare controller for a transaction and call i2c_davinci_xfer_msg 537 */ 538 static int 539 i2c_davinci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) 540 { 541 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap); 542 int i; 543 int ret; 544 545 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); 546 547 ret = pm_runtime_get_sync(dev->dev); 548 if (ret < 0) { 549 dev_err(dev->dev, "Failed to runtime_get device: %d\n", ret); 550 pm_runtime_put_noidle(dev->dev); 551 return ret; 552 } 553 554 ret = i2c_davinci_wait_bus_not_busy(dev); 555 if (ret < 0) { 556 dev_warn(dev->dev, "timeout waiting for bus ready\n"); 557 goto out; 558 } 559 560 for (i = 0; i < num; i++) { 561 ret = i2c_davinci_xfer_msg(adap, &msgs[i], (i == (num - 1))); 562 dev_dbg(dev->dev, "%s [%d/%d] ret: %d\n", __func__, i + 1, num, 563 ret); 564 if (ret < 0) 565 goto out; 566 } 567 568 ret = num; 569 570 out: 571 pm_runtime_mark_last_busy(dev->dev); 572 pm_runtime_put_autosuspend(dev->dev); 573 574 return ret; 575 } 576 577 static u32 i2c_davinci_func(struct i2c_adapter *adap) 578 { 579 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 580 } 581 582 static void terminate_read(struct davinci_i2c_dev *dev) 583 { 584 u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); 585 w |= DAVINCI_I2C_MDR_NACK; 586 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); 587 588 /* Throw away data */ 589 davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG); 590 if (!dev->terminate) 591 dev_err(dev->dev, "RDR IRQ while no data requested\n"); 592 } 593 static void terminate_write(struct davinci_i2c_dev *dev) 594 { 595 u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); 596 w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP; 597 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); 598 599 if (!dev->terminate) 600 dev_dbg(dev->dev, "TDR IRQ while no data to send\n"); 601 } 602 603 /* 604 * Interrupt service routine. This gets called whenever an I2C interrupt 605 * occurs. 606 */ 607 static irqreturn_t i2c_davinci_isr(int this_irq, void *dev_id) 608 { 609 struct davinci_i2c_dev *dev = dev_id; 610 u32 stat; 611 int count = 0; 612 u16 w; 613 614 if (pm_runtime_suspended(dev->dev)) 615 return IRQ_NONE; 616 617 while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) { 618 dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat); 619 if (count++ == 100) { 620 dev_warn(dev->dev, "Too much work in one IRQ\n"); 621 break; 622 } 623 624 switch (stat) { 625 case DAVINCI_I2C_IVR_AL: 626 /* Arbitration lost, must retry */ 627 dev->cmd_err |= DAVINCI_I2C_STR_AL; 628 dev->buf_len = 0; 629 complete(&dev->cmd_complete); 630 break; 631 632 case DAVINCI_I2C_IVR_NACK: 633 dev->cmd_err |= DAVINCI_I2C_STR_NACK; 634 dev->buf_len = 0; 635 complete(&dev->cmd_complete); 636 break; 637 638 case DAVINCI_I2C_IVR_ARDY: 639 davinci_i2c_write_reg(dev, 640 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY); 641 if (((dev->buf_len == 0) && (dev->stop != 0)) || 642 (dev->cmd_err & DAVINCI_I2C_STR_NACK)) { 643 w = davinci_i2c_read_reg(dev, 644 DAVINCI_I2C_MDR_REG); 645 w |= DAVINCI_I2C_MDR_STP; 646 davinci_i2c_write_reg(dev, 647 DAVINCI_I2C_MDR_REG, w); 648 } 649 complete(&dev->cmd_complete); 650 break; 651 652 case DAVINCI_I2C_IVR_RDR: 653 if (dev->buf_len) { 654 *dev->buf++ = 655 davinci_i2c_read_reg(dev, 656 DAVINCI_I2C_DRR_REG); 657 dev->buf_len--; 658 if (dev->buf_len) 659 continue; 660 661 davinci_i2c_write_reg(dev, 662 DAVINCI_I2C_STR_REG, 663 DAVINCI_I2C_IMR_RRDY); 664 } else { 665 /* signal can terminate transfer */ 666 terminate_read(dev); 667 } 668 break; 669 670 case DAVINCI_I2C_IVR_XRDY: 671 if (dev->buf_len) { 672 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, 673 *dev->buf++); 674 dev->buf_len--; 675 if (dev->buf_len) 676 continue; 677 678 w = davinci_i2c_read_reg(dev, 679 DAVINCI_I2C_IMR_REG); 680 w &= ~DAVINCI_I2C_IMR_XRDY; 681 davinci_i2c_write_reg(dev, 682 DAVINCI_I2C_IMR_REG, 683 w); 684 } else { 685 /* signal can terminate transfer */ 686 terminate_write(dev); 687 } 688 break; 689 690 case DAVINCI_I2C_IVR_SCD: 691 davinci_i2c_write_reg(dev, 692 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD); 693 complete(&dev->cmd_complete); 694 break; 695 696 case DAVINCI_I2C_IVR_AAS: 697 dev_dbg(dev->dev, "Address as slave interrupt\n"); 698 break; 699 700 default: 701 dev_warn(dev->dev, "Unrecognized irq stat %d\n", stat); 702 break; 703 } 704 } 705 706 return count ? IRQ_HANDLED : IRQ_NONE; 707 } 708 709 #ifdef CONFIG_CPU_FREQ 710 static int i2c_davinci_cpufreq_transition(struct notifier_block *nb, 711 unsigned long val, void *data) 712 { 713 struct davinci_i2c_dev *dev; 714 715 dev = container_of(nb, struct davinci_i2c_dev, freq_transition); 716 717 i2c_lock_adapter(&dev->adapter); 718 if (val == CPUFREQ_PRECHANGE) { 719 davinci_i2c_reset_ctrl(dev, 0); 720 } else if (val == CPUFREQ_POSTCHANGE) { 721 i2c_davinci_calc_clk_dividers(dev); 722 davinci_i2c_reset_ctrl(dev, 1); 723 } 724 i2c_unlock_adapter(&dev->adapter); 725 726 return 0; 727 } 728 729 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev) 730 { 731 dev->freq_transition.notifier_call = i2c_davinci_cpufreq_transition; 732 733 return cpufreq_register_notifier(&dev->freq_transition, 734 CPUFREQ_TRANSITION_NOTIFIER); 735 } 736 737 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev) 738 { 739 cpufreq_unregister_notifier(&dev->freq_transition, 740 CPUFREQ_TRANSITION_NOTIFIER); 741 } 742 #else 743 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev) 744 { 745 return 0; 746 } 747 748 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev) 749 { 750 } 751 #endif 752 753 static const struct i2c_algorithm i2c_davinci_algo = { 754 .master_xfer = i2c_davinci_xfer, 755 .functionality = i2c_davinci_func, 756 }; 757 758 static const struct of_device_id davinci_i2c_of_match[] = { 759 {.compatible = "ti,davinci-i2c", }, 760 {.compatible = "ti,keystone-i2c", }, 761 {}, 762 }; 763 MODULE_DEVICE_TABLE(of, davinci_i2c_of_match); 764 765 static int davinci_i2c_probe(struct platform_device *pdev) 766 { 767 struct davinci_i2c_dev *dev; 768 struct i2c_adapter *adap; 769 struct resource *mem; 770 struct i2c_bus_recovery_info *rinfo; 771 int r, irq; 772 773 irq = platform_get_irq(pdev, 0); 774 if (irq <= 0) { 775 if (!irq) 776 irq = -ENXIO; 777 if (irq != -EPROBE_DEFER) 778 dev_err(&pdev->dev, 779 "can't get irq resource ret=%d\n", irq); 780 return irq; 781 } 782 783 dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_i2c_dev), 784 GFP_KERNEL); 785 if (!dev) { 786 dev_err(&pdev->dev, "Memory allocation failed\n"); 787 return -ENOMEM; 788 } 789 790 init_completion(&dev->cmd_complete); 791 792 dev->dev = &pdev->dev; 793 dev->irq = irq; 794 dev->pdata = dev_get_platdata(&pdev->dev); 795 platform_set_drvdata(pdev, dev); 796 797 if (!dev->pdata && pdev->dev.of_node) { 798 u32 prop; 799 800 dev->pdata = devm_kzalloc(&pdev->dev, 801 sizeof(struct davinci_i2c_platform_data), GFP_KERNEL); 802 if (!dev->pdata) 803 return -ENOMEM; 804 805 memcpy(dev->pdata, &davinci_i2c_platform_data_default, 806 sizeof(struct davinci_i2c_platform_data)); 807 if (!of_property_read_u32(pdev->dev.of_node, "clock-frequency", 808 &prop)) 809 dev->pdata->bus_freq = prop / 1000; 810 811 dev->pdata->has_pfunc = 812 of_property_read_bool(pdev->dev.of_node, 813 "ti,has-pfunc"); 814 } else if (!dev->pdata) { 815 dev->pdata = &davinci_i2c_platform_data_default; 816 } 817 818 dev->clk = devm_clk_get(&pdev->dev, NULL); 819 if (IS_ERR(dev->clk)) 820 return PTR_ERR(dev->clk); 821 822 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 823 dev->base = devm_ioremap_resource(&pdev->dev, mem); 824 if (IS_ERR(dev->base)) { 825 return PTR_ERR(dev->base); 826 } 827 828 pm_runtime_set_autosuspend_delay(dev->dev, 829 DAVINCI_I2C_PM_TIMEOUT); 830 pm_runtime_use_autosuspend(dev->dev); 831 832 pm_runtime_enable(dev->dev); 833 834 r = pm_runtime_get_sync(dev->dev); 835 if (r < 0) { 836 dev_err(dev->dev, "failed to runtime_get device: %d\n", r); 837 pm_runtime_put_noidle(dev->dev); 838 return r; 839 } 840 841 i2c_davinci_init(dev); 842 843 r = devm_request_irq(&pdev->dev, dev->irq, i2c_davinci_isr, 0, 844 pdev->name, dev); 845 if (r) { 846 dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq); 847 goto err_unuse_clocks; 848 } 849 850 r = i2c_davinci_cpufreq_register(dev); 851 if (r) { 852 dev_err(&pdev->dev, "failed to register cpufreq\n"); 853 goto err_unuse_clocks; 854 } 855 856 adap = &dev->adapter; 857 i2c_set_adapdata(adap, dev); 858 adap->owner = THIS_MODULE; 859 adap->class = I2C_CLASS_DEPRECATED; 860 strlcpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name)); 861 adap->algo = &i2c_davinci_algo; 862 adap->dev.parent = &pdev->dev; 863 adap->timeout = DAVINCI_I2C_TIMEOUT; 864 adap->dev.of_node = pdev->dev.of_node; 865 866 if (dev->pdata->has_pfunc) 867 adap->bus_recovery_info = &davinci_i2c_scl_recovery_info; 868 else if (dev->pdata->gpio_recovery) { 869 rinfo = &davinci_i2c_gpio_recovery_info; 870 adap->bus_recovery_info = rinfo; 871 rinfo->scl_gpiod = devm_gpiod_get(&pdev->dev, "scl", 872 GPIOD_OUT_HIGH_OPEN_DRAIN); 873 if (IS_ERR(rinfo->scl_gpiod)) { 874 r = PTR_ERR(rinfo->scl_gpiod); 875 goto err_unuse_clocks; 876 } 877 rinfo->sda_gpiod = devm_gpiod_get(&pdev->dev, "sda", GPIOD_IN); 878 if (IS_ERR(rinfo->sda_gpiod)) { 879 r = PTR_ERR(rinfo->sda_gpiod); 880 goto err_unuse_clocks; 881 } 882 } 883 884 adap->nr = pdev->id; 885 r = i2c_add_numbered_adapter(adap); 886 if (r) 887 goto err_unuse_clocks; 888 889 pm_runtime_mark_last_busy(dev->dev); 890 pm_runtime_put_autosuspend(dev->dev); 891 892 return 0; 893 894 err_unuse_clocks: 895 pm_runtime_dont_use_autosuspend(dev->dev); 896 pm_runtime_put_sync(dev->dev); 897 pm_runtime_disable(dev->dev); 898 899 return r; 900 } 901 902 static int davinci_i2c_remove(struct platform_device *pdev) 903 { 904 struct davinci_i2c_dev *dev = platform_get_drvdata(pdev); 905 int ret; 906 907 i2c_davinci_cpufreq_deregister(dev); 908 909 i2c_del_adapter(&dev->adapter); 910 911 ret = pm_runtime_get_sync(&pdev->dev); 912 if (ret < 0) { 913 pm_runtime_put_noidle(&pdev->dev); 914 return ret; 915 } 916 917 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, 0); 918 919 pm_runtime_dont_use_autosuspend(dev->dev); 920 pm_runtime_put_sync(dev->dev); 921 pm_runtime_disable(dev->dev); 922 923 return 0; 924 } 925 926 #ifdef CONFIG_PM 927 static int davinci_i2c_suspend(struct device *dev) 928 { 929 struct davinci_i2c_dev *i2c_dev = dev_get_drvdata(dev); 930 931 /* put I2C into reset */ 932 davinci_i2c_reset_ctrl(i2c_dev, 0); 933 934 return 0; 935 } 936 937 static int davinci_i2c_resume(struct device *dev) 938 { 939 struct davinci_i2c_dev *i2c_dev = dev_get_drvdata(dev); 940 941 /* take I2C out of reset */ 942 davinci_i2c_reset_ctrl(i2c_dev, 1); 943 944 return 0; 945 } 946 947 static const struct dev_pm_ops davinci_i2c_pm = { 948 .suspend = davinci_i2c_suspend, 949 .resume = davinci_i2c_resume, 950 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 951 pm_runtime_force_resume) 952 }; 953 954 #define davinci_i2c_pm_ops (&davinci_i2c_pm) 955 #else 956 #define davinci_i2c_pm_ops NULL 957 #endif 958 959 /* work with hotplug and coldplug */ 960 MODULE_ALIAS("platform:i2c_davinci"); 961 962 static struct platform_driver davinci_i2c_driver = { 963 .probe = davinci_i2c_probe, 964 .remove = davinci_i2c_remove, 965 .driver = { 966 .name = "i2c_davinci", 967 .pm = davinci_i2c_pm_ops, 968 .of_match_table = davinci_i2c_of_match, 969 }, 970 }; 971 972 /* I2C may be needed to bring up other drivers */ 973 static int __init davinci_i2c_init_driver(void) 974 { 975 return platform_driver_register(&davinci_i2c_driver); 976 } 977 subsys_initcall(davinci_i2c_init_driver); 978 979 static void __exit davinci_i2c_exit_driver(void) 980 { 981 platform_driver_unregister(&davinci_i2c_driver); 982 } 983 module_exit(davinci_i2c_exit_driver); 984 985 MODULE_AUTHOR("Texas Instruments India"); 986 MODULE_DESCRIPTION("TI DaVinci I2C bus adapter"); 987 MODULE_LICENSE("GPL"); 988