1 /* 2 * Freescale CPM1/CPM2 I2C interface. 3 * Copyright (c) 1999 Dan Malek (dmalek@jlc.net). 4 * 5 * moved into proper i2c interface; 6 * Brad Parker (brad@heeltoe.com) 7 * 8 * Parts from dbox2_i2c.c (cvs.tuxbox.org) 9 * (C) 2000-2001 Felix Domke (tmbinc@gmx.net), Gillem (htoa@gmx.net) 10 * 11 * (C) 2007 Montavista Software, Inc. 12 * Vitaly Bordug <vitb@kernel.crashing.org> 13 * 14 * Converted to of_platform_device. Renamed to i2c-cpm.c. 15 * (C) 2007,2008 Jochen Friedrich <jochen@scram.de> 16 * 17 * This program is free software; you can redistribute it and/or modify 18 * it under the terms of the GNU General Public License as published by 19 * the Free Software Foundation; either version 2 of the License, or 20 * (at your option) any later version. 21 * 22 * This program is distributed in the hope that it will be useful, 23 * but WITHOUT ANY WARRANTY; without even the implied warranty of 24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 * GNU General Public License for more details. 26 * 27 * You should have received a copy of the GNU General Public License 28 * along with this program; if not, write to the Free Software 29 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 30 */ 31 32 #include <linux/kernel.h> 33 #include <linux/module.h> 34 #include <linux/delay.h> 35 #include <linux/slab.h> 36 #include <linux/init.h> 37 #include <linux/interrupt.h> 38 #include <linux/errno.h> 39 #include <linux/stddef.h> 40 #include <linux/i2c.h> 41 #include <linux/io.h> 42 #include <linux/dma-mapping.h> 43 #include <linux/of_device.h> 44 #include <linux/of_platform.h> 45 #include <sysdev/fsl_soc.h> 46 #include <asm/cpm.h> 47 48 /* Try to define this if you have an older CPU (earlier than rev D4) */ 49 /* However, better use a GPIO based bitbang driver in this case :/ */ 50 #undef I2C_CHIP_ERRATA 51 52 #define CPM_MAX_READ 513 53 #define CPM_MAXBD 4 54 55 #define I2C_EB (0x10) /* Big endian mode */ 56 #define I2C_EB_CPM2 (0x30) /* Big endian mode, memory snoop */ 57 58 #define DPRAM_BASE ((u8 __iomem __force *)cpm_muram_addr(0)) 59 60 /* I2C parameter RAM. */ 61 struct i2c_ram { 62 ushort rbase; /* Rx Buffer descriptor base address */ 63 ushort tbase; /* Tx Buffer descriptor base address */ 64 u_char rfcr; /* Rx function code */ 65 u_char tfcr; /* Tx function code */ 66 ushort mrblr; /* Max receive buffer length */ 67 uint rstate; /* Internal */ 68 uint rdp; /* Internal */ 69 ushort rbptr; /* Rx Buffer descriptor pointer */ 70 ushort rbc; /* Internal */ 71 uint rxtmp; /* Internal */ 72 uint tstate; /* Internal */ 73 uint tdp; /* Internal */ 74 ushort tbptr; /* Tx Buffer descriptor pointer */ 75 ushort tbc; /* Internal */ 76 uint txtmp; /* Internal */ 77 char res1[4]; /* Reserved */ 78 ushort rpbase; /* Relocation pointer */ 79 char res2[2]; /* Reserved */ 80 }; 81 82 #define I2COM_START 0x80 83 #define I2COM_MASTER 0x01 84 #define I2CER_TXE 0x10 85 #define I2CER_BUSY 0x04 86 #define I2CER_TXB 0x02 87 #define I2CER_RXB 0x01 88 #define I2MOD_EN 0x01 89 90 /* I2C Registers */ 91 struct i2c_reg { 92 u8 i2mod; 93 u8 res1[3]; 94 u8 i2add; 95 u8 res2[3]; 96 u8 i2brg; 97 u8 res3[3]; 98 u8 i2com; 99 u8 res4[3]; 100 u8 i2cer; 101 u8 res5[3]; 102 u8 i2cmr; 103 }; 104 105 struct cpm_i2c { 106 char *base; 107 struct platform_device *ofdev; 108 struct i2c_adapter adap; 109 uint dp_addr; 110 int version; /* CPM1=1, CPM2=2 */ 111 int irq; 112 int cp_command; 113 int freq; 114 struct i2c_reg __iomem *i2c_reg; 115 struct i2c_ram __iomem *i2c_ram; 116 u16 i2c_addr; 117 wait_queue_head_t i2c_wait; 118 cbd_t __iomem *tbase; 119 cbd_t __iomem *rbase; 120 u_char *txbuf[CPM_MAXBD]; 121 u_char *rxbuf[CPM_MAXBD]; 122 u32 txdma[CPM_MAXBD]; 123 u32 rxdma[CPM_MAXBD]; 124 }; 125 126 static irqreturn_t cpm_i2c_interrupt(int irq, void *dev_id) 127 { 128 struct cpm_i2c *cpm; 129 struct i2c_reg __iomem *i2c_reg; 130 struct i2c_adapter *adap = dev_id; 131 int i; 132 133 cpm = i2c_get_adapdata(dev_id); 134 i2c_reg = cpm->i2c_reg; 135 136 /* Clear interrupt. */ 137 i = in_8(&i2c_reg->i2cer); 138 out_8(&i2c_reg->i2cer, i); 139 140 dev_dbg(&adap->dev, "Interrupt: %x\n", i); 141 142 wake_up(&cpm->i2c_wait); 143 144 return i ? IRQ_HANDLED : IRQ_NONE; 145 } 146 147 static void cpm_reset_i2c_params(struct cpm_i2c *cpm) 148 { 149 struct i2c_ram __iomem *i2c_ram = cpm->i2c_ram; 150 151 /* Set up the I2C parameters in the parameter ram. */ 152 out_be16(&i2c_ram->tbase, (u8 __iomem *)cpm->tbase - DPRAM_BASE); 153 out_be16(&i2c_ram->rbase, (u8 __iomem *)cpm->rbase - DPRAM_BASE); 154 155 if (cpm->version == 1) { 156 out_8(&i2c_ram->tfcr, I2C_EB); 157 out_8(&i2c_ram->rfcr, I2C_EB); 158 } else { 159 out_8(&i2c_ram->tfcr, I2C_EB_CPM2); 160 out_8(&i2c_ram->rfcr, I2C_EB_CPM2); 161 } 162 163 out_be16(&i2c_ram->mrblr, CPM_MAX_READ); 164 165 out_be32(&i2c_ram->rstate, 0); 166 out_be32(&i2c_ram->rdp, 0); 167 out_be16(&i2c_ram->rbptr, 0); 168 out_be16(&i2c_ram->rbc, 0); 169 out_be32(&i2c_ram->rxtmp, 0); 170 out_be32(&i2c_ram->tstate, 0); 171 out_be32(&i2c_ram->tdp, 0); 172 out_be16(&i2c_ram->tbptr, 0); 173 out_be16(&i2c_ram->tbc, 0); 174 out_be32(&i2c_ram->txtmp, 0); 175 } 176 177 static void cpm_i2c_force_close(struct i2c_adapter *adap) 178 { 179 struct cpm_i2c *cpm = i2c_get_adapdata(adap); 180 struct i2c_reg __iomem *i2c_reg = cpm->i2c_reg; 181 182 dev_dbg(&adap->dev, "cpm_i2c_force_close()\n"); 183 184 cpm_command(cpm->cp_command, CPM_CR_CLOSE_RX_BD); 185 186 out_8(&i2c_reg->i2cmr, 0x00); /* Disable all interrupts */ 187 out_8(&i2c_reg->i2cer, 0xff); 188 } 189 190 static void cpm_i2c_parse_message(struct i2c_adapter *adap, 191 struct i2c_msg *pmsg, int num, int tx, int rx) 192 { 193 cbd_t __iomem *tbdf; 194 cbd_t __iomem *rbdf; 195 u_char addr; 196 u_char *tb; 197 u_char *rb; 198 struct cpm_i2c *cpm = i2c_get_adapdata(adap); 199 200 tbdf = cpm->tbase + tx; 201 rbdf = cpm->rbase + rx; 202 203 addr = pmsg->addr << 1; 204 if (pmsg->flags & I2C_M_RD) 205 addr |= 1; 206 207 tb = cpm->txbuf[tx]; 208 rb = cpm->rxbuf[rx]; 209 210 /* Align read buffer */ 211 rb = (u_char *) (((ulong) rb + 1) & ~1); 212 213 tb[0] = addr; /* Device address byte w/rw flag */ 214 215 out_be16(&tbdf->cbd_datlen, pmsg->len + 1); 216 out_be16(&tbdf->cbd_sc, 0); 217 218 if (!(pmsg->flags & I2C_M_NOSTART)) 219 setbits16(&tbdf->cbd_sc, BD_I2C_START); 220 221 if (tx + 1 == num) 222 setbits16(&tbdf->cbd_sc, BD_SC_LAST | BD_SC_WRAP); 223 224 if (pmsg->flags & I2C_M_RD) { 225 /* 226 * To read, we need an empty buffer of the proper length. 227 * All that is used is the first byte for address, the remainder 228 * is just used for timing (and doesn't really have to exist). 229 */ 230 231 dev_dbg(&adap->dev, "cpm_i2c_read(abyte=0x%x)\n", addr); 232 233 out_be16(&rbdf->cbd_datlen, 0); 234 out_be16(&rbdf->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT); 235 236 if (rx + 1 == CPM_MAXBD) 237 setbits16(&rbdf->cbd_sc, BD_SC_WRAP); 238 239 eieio(); 240 setbits16(&tbdf->cbd_sc, BD_SC_READY); 241 } else { 242 dev_dbg(&adap->dev, "cpm_i2c_write(abyte=0x%x)\n", addr); 243 244 memcpy(tb+1, pmsg->buf, pmsg->len); 245 246 eieio(); 247 setbits16(&tbdf->cbd_sc, BD_SC_READY | BD_SC_INTRPT); 248 } 249 } 250 251 static int cpm_i2c_check_message(struct i2c_adapter *adap, 252 struct i2c_msg *pmsg, int tx, int rx) 253 { 254 cbd_t __iomem *tbdf; 255 cbd_t __iomem *rbdf; 256 u_char *tb; 257 u_char *rb; 258 struct cpm_i2c *cpm = i2c_get_adapdata(adap); 259 260 tbdf = cpm->tbase + tx; 261 rbdf = cpm->rbase + rx; 262 263 tb = cpm->txbuf[tx]; 264 rb = cpm->rxbuf[rx]; 265 266 /* Align read buffer */ 267 rb = (u_char *) (((uint) rb + 1) & ~1); 268 269 eieio(); 270 if (pmsg->flags & I2C_M_RD) { 271 dev_dbg(&adap->dev, "tx sc 0x%04x, rx sc 0x%04x\n", 272 in_be16(&tbdf->cbd_sc), in_be16(&rbdf->cbd_sc)); 273 274 if (in_be16(&tbdf->cbd_sc) & BD_SC_NAK) { 275 dev_dbg(&adap->dev, "I2C read; No ack\n"); 276 return -ENXIO; 277 } 278 if (in_be16(&rbdf->cbd_sc) & BD_SC_EMPTY) { 279 dev_err(&adap->dev, 280 "I2C read; complete but rbuf empty\n"); 281 return -EREMOTEIO; 282 } 283 if (in_be16(&rbdf->cbd_sc) & BD_SC_OV) { 284 dev_err(&adap->dev, "I2C read; Overrun\n"); 285 return -EREMOTEIO; 286 } 287 memcpy(pmsg->buf, rb, pmsg->len); 288 } else { 289 dev_dbg(&adap->dev, "tx sc %d 0x%04x\n", tx, 290 in_be16(&tbdf->cbd_sc)); 291 292 if (in_be16(&tbdf->cbd_sc) & BD_SC_NAK) { 293 dev_dbg(&adap->dev, "I2C write; No ack\n"); 294 return -ENXIO; 295 } 296 if (in_be16(&tbdf->cbd_sc) & BD_SC_UN) { 297 dev_err(&adap->dev, "I2C write; Underrun\n"); 298 return -EIO; 299 } 300 if (in_be16(&tbdf->cbd_sc) & BD_SC_CL) { 301 dev_err(&adap->dev, "I2C write; Collision\n"); 302 return -EIO; 303 } 304 } 305 return 0; 306 } 307 308 static int cpm_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 309 { 310 struct cpm_i2c *cpm = i2c_get_adapdata(adap); 311 struct i2c_reg __iomem *i2c_reg = cpm->i2c_reg; 312 struct i2c_ram __iomem *i2c_ram = cpm->i2c_ram; 313 struct i2c_msg *pmsg; 314 int ret, i; 315 int tptr; 316 int rptr; 317 cbd_t __iomem *tbdf; 318 cbd_t __iomem *rbdf; 319 320 if (num > CPM_MAXBD) 321 return -EINVAL; 322 323 /* Check if we have any oversized READ requests */ 324 for (i = 0; i < num; i++) { 325 pmsg = &msgs[i]; 326 if (pmsg->len >= CPM_MAX_READ) 327 return -EINVAL; 328 } 329 330 /* Reset to use first buffer */ 331 out_be16(&i2c_ram->rbptr, in_be16(&i2c_ram->rbase)); 332 out_be16(&i2c_ram->tbptr, in_be16(&i2c_ram->tbase)); 333 334 tbdf = cpm->tbase; 335 rbdf = cpm->rbase; 336 337 tptr = 0; 338 rptr = 0; 339 340 /* 341 * If there was a collision in the last i2c transaction, 342 * Set I2COM_MASTER as it was cleared during collision. 343 */ 344 if (in_be16(&tbdf->cbd_sc) & BD_SC_CL) { 345 out_8(&cpm->i2c_reg->i2com, I2COM_MASTER); 346 } 347 348 while (tptr < num) { 349 pmsg = &msgs[tptr]; 350 dev_dbg(&adap->dev, "R: %d T: %d\n", rptr, tptr); 351 352 cpm_i2c_parse_message(adap, pmsg, num, tptr, rptr); 353 if (pmsg->flags & I2C_M_RD) 354 rptr++; 355 tptr++; 356 } 357 /* Start transfer now */ 358 /* Enable RX/TX/Error interupts */ 359 out_8(&i2c_reg->i2cmr, I2CER_TXE | I2CER_TXB | I2CER_RXB); 360 out_8(&i2c_reg->i2cer, 0xff); /* Clear interrupt status */ 361 /* Chip bug, set enable here */ 362 setbits8(&i2c_reg->i2mod, I2MOD_EN); /* Enable */ 363 /* Begin transmission */ 364 setbits8(&i2c_reg->i2com, I2COM_START); 365 366 tptr = 0; 367 rptr = 0; 368 369 while (tptr < num) { 370 /* Check for outstanding messages */ 371 dev_dbg(&adap->dev, "test ready.\n"); 372 pmsg = &msgs[tptr]; 373 if (pmsg->flags & I2C_M_RD) 374 ret = wait_event_timeout(cpm->i2c_wait, 375 (in_be16(&tbdf[tptr].cbd_sc) & BD_SC_NAK) || 376 !(in_be16(&rbdf[rptr].cbd_sc) & BD_SC_EMPTY), 377 1 * HZ); 378 else 379 ret = wait_event_timeout(cpm->i2c_wait, 380 !(in_be16(&tbdf[tptr].cbd_sc) & BD_SC_READY), 381 1 * HZ); 382 if (ret == 0) { 383 ret = -EREMOTEIO; 384 dev_err(&adap->dev, "I2C transfer: timeout\n"); 385 goto out_err; 386 } 387 if (ret > 0) { 388 dev_dbg(&adap->dev, "ready.\n"); 389 ret = cpm_i2c_check_message(adap, pmsg, tptr, rptr); 390 tptr++; 391 if (pmsg->flags & I2C_M_RD) 392 rptr++; 393 if (ret) 394 goto out_err; 395 } 396 } 397 #ifdef I2C_CHIP_ERRATA 398 /* 399 * Chip errata, clear enable. This is not needed on rev D4 CPUs. 400 * Disabling I2C too early may cause too short stop condition 401 */ 402 udelay(4); 403 clrbits8(&i2c_reg->i2mod, I2MOD_EN); 404 #endif 405 return (num); 406 407 out_err: 408 cpm_i2c_force_close(adap); 409 #ifdef I2C_CHIP_ERRATA 410 /* 411 * Chip errata, clear enable. This is not needed on rev D4 CPUs. 412 */ 413 clrbits8(&i2c_reg->i2mod, I2MOD_EN); 414 #endif 415 return ret; 416 } 417 418 static u32 cpm_i2c_func(struct i2c_adapter *adap) 419 { 420 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 421 } 422 423 /* -----exported algorithm data: ------------------------------------- */ 424 425 static const struct i2c_algorithm cpm_i2c_algo = { 426 .master_xfer = cpm_i2c_xfer, 427 .functionality = cpm_i2c_func, 428 }; 429 430 static const struct i2c_adapter cpm_ops = { 431 .owner = THIS_MODULE, 432 .name = "i2c-cpm", 433 .algo = &cpm_i2c_algo, 434 }; 435 436 static int cpm_i2c_setup(struct cpm_i2c *cpm) 437 { 438 struct platform_device *ofdev = cpm->ofdev; 439 const u32 *data; 440 int len, ret, i; 441 void __iomem *i2c_base; 442 cbd_t __iomem *tbdf; 443 cbd_t __iomem *rbdf; 444 unsigned char brg; 445 446 dev_dbg(&cpm->ofdev->dev, "cpm_i2c_setup()\n"); 447 448 init_waitqueue_head(&cpm->i2c_wait); 449 450 cpm->irq = irq_of_parse_and_map(ofdev->dev.of_node, 0); 451 if (!cpm->irq) 452 return -EINVAL; 453 454 /* Install interrupt handler. */ 455 ret = request_irq(cpm->irq, cpm_i2c_interrupt, 0, "cpm_i2c", 456 &cpm->adap); 457 if (ret) 458 return ret; 459 460 /* I2C parameter RAM */ 461 i2c_base = of_iomap(ofdev->dev.of_node, 1); 462 if (i2c_base == NULL) { 463 ret = -EINVAL; 464 goto out_irq; 465 } 466 467 if (of_device_is_compatible(ofdev->dev.of_node, "fsl,cpm1-i2c")) { 468 469 /* Check for and use a microcode relocation patch. */ 470 cpm->i2c_ram = i2c_base; 471 cpm->i2c_addr = in_be16(&cpm->i2c_ram->rpbase); 472 473 /* 474 * Maybe should use cpm_muram_alloc instead of hardcoding 475 * this in micropatch.c 476 */ 477 if (cpm->i2c_addr) { 478 cpm->i2c_ram = cpm_muram_addr(cpm->i2c_addr); 479 iounmap(i2c_base); 480 } 481 482 cpm->version = 1; 483 484 } else if (of_device_is_compatible(ofdev->dev.of_node, "fsl,cpm2-i2c")) { 485 cpm->i2c_addr = cpm_muram_alloc(sizeof(struct i2c_ram), 64); 486 cpm->i2c_ram = cpm_muram_addr(cpm->i2c_addr); 487 out_be16(i2c_base, cpm->i2c_addr); 488 iounmap(i2c_base); 489 490 cpm->version = 2; 491 492 } else { 493 iounmap(i2c_base); 494 ret = -EINVAL; 495 goto out_irq; 496 } 497 498 /* I2C control/status registers */ 499 cpm->i2c_reg = of_iomap(ofdev->dev.of_node, 0); 500 if (cpm->i2c_reg == NULL) { 501 ret = -EINVAL; 502 goto out_ram; 503 } 504 505 data = of_get_property(ofdev->dev.of_node, "fsl,cpm-command", &len); 506 if (!data || len != 4) { 507 ret = -EINVAL; 508 goto out_reg; 509 } 510 cpm->cp_command = *data; 511 512 data = of_get_property(ofdev->dev.of_node, "linux,i2c-class", &len); 513 if (data && len == 4) 514 cpm->adap.class = *data; 515 516 data = of_get_property(ofdev->dev.of_node, "clock-frequency", &len); 517 if (data && len == 4) 518 cpm->freq = *data; 519 else 520 cpm->freq = 60000; /* use 60kHz i2c clock by default */ 521 522 /* 523 * Allocate space for CPM_MAXBD transmit and receive buffer 524 * descriptors in the DP ram. 525 */ 526 cpm->dp_addr = cpm_muram_alloc(sizeof(cbd_t) * 2 * CPM_MAXBD, 8); 527 if (!cpm->dp_addr) { 528 ret = -ENOMEM; 529 goto out_reg; 530 } 531 532 cpm->tbase = cpm_muram_addr(cpm->dp_addr); 533 cpm->rbase = cpm_muram_addr(cpm->dp_addr + sizeof(cbd_t) * CPM_MAXBD); 534 535 /* Allocate TX and RX buffers */ 536 537 tbdf = cpm->tbase; 538 rbdf = cpm->rbase; 539 540 for (i = 0; i < CPM_MAXBD; i++) { 541 cpm->rxbuf[i] = dma_alloc_coherent(&cpm->ofdev->dev, 542 CPM_MAX_READ + 1, 543 &cpm->rxdma[i], GFP_KERNEL); 544 if (!cpm->rxbuf[i]) { 545 ret = -ENOMEM; 546 goto out_muram; 547 } 548 out_be32(&rbdf[i].cbd_bufaddr, ((cpm->rxdma[i] + 1) & ~1)); 549 550 cpm->txbuf[i] = (unsigned char *)dma_alloc_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1, &cpm->txdma[i], GFP_KERNEL); 551 if (!cpm->txbuf[i]) { 552 ret = -ENOMEM; 553 goto out_muram; 554 } 555 out_be32(&tbdf[i].cbd_bufaddr, cpm->txdma[i]); 556 } 557 558 /* Initialize Tx/Rx parameters. */ 559 560 cpm_reset_i2c_params(cpm); 561 562 dev_dbg(&cpm->ofdev->dev, "i2c_ram 0x%p, i2c_addr 0x%04x, freq %d\n", 563 cpm->i2c_ram, cpm->i2c_addr, cpm->freq); 564 dev_dbg(&cpm->ofdev->dev, "tbase 0x%04x, rbase 0x%04x\n", 565 (u8 __iomem *)cpm->tbase - DPRAM_BASE, 566 (u8 __iomem *)cpm->rbase - DPRAM_BASE); 567 568 cpm_command(cpm->cp_command, CPM_CR_INIT_TRX); 569 570 /* 571 * Select an invalid address. Just make sure we don't use loopback mode 572 */ 573 out_8(&cpm->i2c_reg->i2add, 0x7f << 1); 574 575 /* 576 * PDIV is set to 00 in i2mod, so brgclk/32 is used as input to the 577 * i2c baud rate generator. This is divided by 2 x (DIV + 3) to get 578 * the actual i2c bus frequency. 579 */ 580 brg = get_brgfreq() / (32 * 2 * cpm->freq) - 3; 581 out_8(&cpm->i2c_reg->i2brg, brg); 582 583 out_8(&cpm->i2c_reg->i2mod, 0x00); 584 out_8(&cpm->i2c_reg->i2com, I2COM_MASTER); /* Master mode */ 585 586 /* Disable interrupts. */ 587 out_8(&cpm->i2c_reg->i2cmr, 0); 588 out_8(&cpm->i2c_reg->i2cer, 0xff); 589 590 return 0; 591 592 out_muram: 593 for (i = 0; i < CPM_MAXBD; i++) { 594 if (cpm->rxbuf[i]) 595 dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1, 596 cpm->rxbuf[i], cpm->rxdma[i]); 597 if (cpm->txbuf[i]) 598 dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1, 599 cpm->txbuf[i], cpm->txdma[i]); 600 } 601 cpm_muram_free(cpm->dp_addr); 602 out_reg: 603 iounmap(cpm->i2c_reg); 604 out_ram: 605 if ((cpm->version == 1) && (!cpm->i2c_addr)) 606 iounmap(cpm->i2c_ram); 607 if (cpm->version == 2) 608 cpm_muram_free(cpm->i2c_addr); 609 out_irq: 610 free_irq(cpm->irq, &cpm->adap); 611 return ret; 612 } 613 614 static void cpm_i2c_shutdown(struct cpm_i2c *cpm) 615 { 616 int i; 617 618 /* Shut down I2C. */ 619 clrbits8(&cpm->i2c_reg->i2mod, I2MOD_EN); 620 621 /* Disable interrupts */ 622 out_8(&cpm->i2c_reg->i2cmr, 0); 623 out_8(&cpm->i2c_reg->i2cer, 0xff); 624 625 free_irq(cpm->irq, &cpm->adap); 626 627 /* Free all memory */ 628 for (i = 0; i < CPM_MAXBD; i++) { 629 dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1, 630 cpm->rxbuf[i], cpm->rxdma[i]); 631 dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1, 632 cpm->txbuf[i], cpm->txdma[i]); 633 } 634 635 cpm_muram_free(cpm->dp_addr); 636 iounmap(cpm->i2c_reg); 637 638 if ((cpm->version == 1) && (!cpm->i2c_addr)) 639 iounmap(cpm->i2c_ram); 640 if (cpm->version == 2) 641 cpm_muram_free(cpm->i2c_addr); 642 } 643 644 static int cpm_i2c_probe(struct platform_device *ofdev) 645 { 646 int result, len; 647 struct cpm_i2c *cpm; 648 const u32 *data; 649 650 cpm = kzalloc(sizeof(struct cpm_i2c), GFP_KERNEL); 651 if (!cpm) 652 return -ENOMEM; 653 654 cpm->ofdev = ofdev; 655 656 platform_set_drvdata(ofdev, cpm); 657 658 cpm->adap = cpm_ops; 659 i2c_set_adapdata(&cpm->adap, cpm); 660 cpm->adap.dev.parent = &ofdev->dev; 661 cpm->adap.dev.of_node = of_node_get(ofdev->dev.of_node); 662 663 result = cpm_i2c_setup(cpm); 664 if (result) { 665 dev_err(&ofdev->dev, "Unable to init hardware\n"); 666 goto out_free; 667 } 668 669 /* register new adapter to i2c module... */ 670 671 data = of_get_property(ofdev->dev.of_node, "linux,i2c-index", &len); 672 cpm->adap.nr = (data && len == 4) ? be32_to_cpup(data) : -1; 673 result = i2c_add_numbered_adapter(&cpm->adap); 674 675 if (result < 0) { 676 dev_err(&ofdev->dev, "Unable to register with I2C\n"); 677 goto out_shut; 678 } 679 680 dev_dbg(&ofdev->dev, "hw routines for %s registered.\n", 681 cpm->adap.name); 682 683 return 0; 684 out_shut: 685 cpm_i2c_shutdown(cpm); 686 out_free: 687 kfree(cpm); 688 689 return result; 690 } 691 692 static int cpm_i2c_remove(struct platform_device *ofdev) 693 { 694 struct cpm_i2c *cpm = platform_get_drvdata(ofdev); 695 696 i2c_del_adapter(&cpm->adap); 697 698 cpm_i2c_shutdown(cpm); 699 700 kfree(cpm); 701 702 return 0; 703 } 704 705 static const struct of_device_id cpm_i2c_match[] = { 706 { 707 .compatible = "fsl,cpm1-i2c", 708 }, 709 { 710 .compatible = "fsl,cpm2-i2c", 711 }, 712 {}, 713 }; 714 715 MODULE_DEVICE_TABLE(of, cpm_i2c_match); 716 717 static struct platform_driver cpm_i2c_driver = { 718 .probe = cpm_i2c_probe, 719 .remove = cpm_i2c_remove, 720 .driver = { 721 .name = "fsl-i2c-cpm", 722 .owner = THIS_MODULE, 723 .of_match_table = cpm_i2c_match, 724 }, 725 }; 726 727 module_platform_driver(cpm_i2c_driver); 728 729 MODULE_AUTHOR("Jochen Friedrich <jochen@scram.de>"); 730 MODULE_DESCRIPTION("I2C-Bus adapter routines for CPM boards"); 731 MODULE_LICENSE("GPL"); 732