1 /* 2 * Freescale CPM1/CPM2 I2C interface. 3 * Copyright (c) 1999 Dan Malek (dmalek@jlc.net). 4 * 5 * moved into proper i2c interface; 6 * Brad Parker (brad@heeltoe.com) 7 * 8 * Parts from dbox2_i2c.c (cvs.tuxbox.org) 9 * (C) 2000-2001 Felix Domke (tmbinc@gmx.net), Gillem (htoa@gmx.net) 10 * 11 * (C) 2007 Montavista Software, Inc. 12 * Vitaly Bordug <vitb@kernel.crashing.org> 13 * 14 * Converted to of_platform_device. Renamed to i2c-cpm.c. 15 * (C) 2007,2008 Jochen Friedrich <jochen@scram.de> 16 * 17 * This program is free software; you can redistribute it and/or modify 18 * it under the terms of the GNU General Public License as published by 19 * the Free Software Foundation; either version 2 of the License, or 20 * (at your option) any later version. 21 * 22 * This program is distributed in the hope that it will be useful, 23 * but WITHOUT ANY WARRANTY; without even the implied warranty of 24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 * GNU General Public License for more details. 26 */ 27 28 #include <linux/kernel.h> 29 #include <linux/module.h> 30 #include <linux/delay.h> 31 #include <linux/slab.h> 32 #include <linux/interrupt.h> 33 #include <linux/errno.h> 34 #include <linux/stddef.h> 35 #include <linux/i2c.h> 36 #include <linux/io.h> 37 #include <linux/dma-mapping.h> 38 #include <linux/of_address.h> 39 #include <linux/of_device.h> 40 #include <linux/of_irq.h> 41 #include <linux/of_platform.h> 42 #include <sysdev/fsl_soc.h> 43 #include <asm/cpm.h> 44 45 /* Try to define this if you have an older CPU (earlier than rev D4) */ 46 /* However, better use a GPIO based bitbang driver in this case :/ */ 47 #undef I2C_CHIP_ERRATA 48 49 #define CPM_MAX_READ 513 50 #define CPM_MAXBD 4 51 52 #define I2C_EB (0x10) /* Big endian mode */ 53 #define I2C_EB_CPM2 (0x30) /* Big endian mode, memory snoop */ 54 55 #define DPRAM_BASE ((u8 __iomem __force *)cpm_muram_addr(0)) 56 57 /* I2C parameter RAM. */ 58 struct i2c_ram { 59 ushort rbase; /* Rx Buffer descriptor base address */ 60 ushort tbase; /* Tx Buffer descriptor base address */ 61 u_char rfcr; /* Rx function code */ 62 u_char tfcr; /* Tx function code */ 63 ushort mrblr; /* Max receive buffer length */ 64 uint rstate; /* Internal */ 65 uint rdp; /* Internal */ 66 ushort rbptr; /* Rx Buffer descriptor pointer */ 67 ushort rbc; /* Internal */ 68 uint rxtmp; /* Internal */ 69 uint tstate; /* Internal */ 70 uint tdp; /* Internal */ 71 ushort tbptr; /* Tx Buffer descriptor pointer */ 72 ushort tbc; /* Internal */ 73 uint txtmp; /* Internal */ 74 char res1[4]; /* Reserved */ 75 ushort rpbase; /* Relocation pointer */ 76 char res2[2]; /* Reserved */ 77 }; 78 79 #define I2COM_START 0x80 80 #define I2COM_MASTER 0x01 81 #define I2CER_TXE 0x10 82 #define I2CER_BUSY 0x04 83 #define I2CER_TXB 0x02 84 #define I2CER_RXB 0x01 85 #define I2MOD_EN 0x01 86 87 /* I2C Registers */ 88 struct i2c_reg { 89 u8 i2mod; 90 u8 res1[3]; 91 u8 i2add; 92 u8 res2[3]; 93 u8 i2brg; 94 u8 res3[3]; 95 u8 i2com; 96 u8 res4[3]; 97 u8 i2cer; 98 u8 res5[3]; 99 u8 i2cmr; 100 }; 101 102 struct cpm_i2c { 103 char *base; 104 struct platform_device *ofdev; 105 struct i2c_adapter adap; 106 uint dp_addr; 107 int version; /* CPM1=1, CPM2=2 */ 108 int irq; 109 int cp_command; 110 int freq; 111 struct i2c_reg __iomem *i2c_reg; 112 struct i2c_ram __iomem *i2c_ram; 113 u16 i2c_addr; 114 wait_queue_head_t i2c_wait; 115 cbd_t __iomem *tbase; 116 cbd_t __iomem *rbase; 117 u_char *txbuf[CPM_MAXBD]; 118 u_char *rxbuf[CPM_MAXBD]; 119 dma_addr_t txdma[CPM_MAXBD]; 120 dma_addr_t rxdma[CPM_MAXBD]; 121 }; 122 123 static irqreturn_t cpm_i2c_interrupt(int irq, void *dev_id) 124 { 125 struct cpm_i2c *cpm; 126 struct i2c_reg __iomem *i2c_reg; 127 struct i2c_adapter *adap = dev_id; 128 int i; 129 130 cpm = i2c_get_adapdata(dev_id); 131 i2c_reg = cpm->i2c_reg; 132 133 /* Clear interrupt. */ 134 i = in_8(&i2c_reg->i2cer); 135 out_8(&i2c_reg->i2cer, i); 136 137 dev_dbg(&adap->dev, "Interrupt: %x\n", i); 138 139 wake_up(&cpm->i2c_wait); 140 141 return i ? IRQ_HANDLED : IRQ_NONE; 142 } 143 144 static void cpm_reset_i2c_params(struct cpm_i2c *cpm) 145 { 146 struct i2c_ram __iomem *i2c_ram = cpm->i2c_ram; 147 148 /* Set up the I2C parameters in the parameter ram. */ 149 out_be16(&i2c_ram->tbase, (u8 __iomem *)cpm->tbase - DPRAM_BASE); 150 out_be16(&i2c_ram->rbase, (u8 __iomem *)cpm->rbase - DPRAM_BASE); 151 152 if (cpm->version == 1) { 153 out_8(&i2c_ram->tfcr, I2C_EB); 154 out_8(&i2c_ram->rfcr, I2C_EB); 155 } else { 156 out_8(&i2c_ram->tfcr, I2C_EB_CPM2); 157 out_8(&i2c_ram->rfcr, I2C_EB_CPM2); 158 } 159 160 out_be16(&i2c_ram->mrblr, CPM_MAX_READ); 161 162 out_be32(&i2c_ram->rstate, 0); 163 out_be32(&i2c_ram->rdp, 0); 164 out_be16(&i2c_ram->rbptr, 0); 165 out_be16(&i2c_ram->rbc, 0); 166 out_be32(&i2c_ram->rxtmp, 0); 167 out_be32(&i2c_ram->tstate, 0); 168 out_be32(&i2c_ram->tdp, 0); 169 out_be16(&i2c_ram->tbptr, 0); 170 out_be16(&i2c_ram->tbc, 0); 171 out_be32(&i2c_ram->txtmp, 0); 172 } 173 174 static void cpm_i2c_force_close(struct i2c_adapter *adap) 175 { 176 struct cpm_i2c *cpm = i2c_get_adapdata(adap); 177 struct i2c_reg __iomem *i2c_reg = cpm->i2c_reg; 178 179 dev_dbg(&adap->dev, "cpm_i2c_force_close()\n"); 180 181 cpm_command(cpm->cp_command, CPM_CR_CLOSE_RX_BD); 182 183 out_8(&i2c_reg->i2cmr, 0x00); /* Disable all interrupts */ 184 out_8(&i2c_reg->i2cer, 0xff); 185 } 186 187 static void cpm_i2c_parse_message(struct i2c_adapter *adap, 188 struct i2c_msg *pmsg, int num, int tx, int rx) 189 { 190 cbd_t __iomem *tbdf; 191 cbd_t __iomem *rbdf; 192 u_char addr; 193 u_char *tb; 194 u_char *rb; 195 struct cpm_i2c *cpm = i2c_get_adapdata(adap); 196 197 tbdf = cpm->tbase + tx; 198 rbdf = cpm->rbase + rx; 199 200 addr = i2c_8bit_addr_from_msg(pmsg); 201 202 tb = cpm->txbuf[tx]; 203 rb = cpm->rxbuf[rx]; 204 205 /* Align read buffer */ 206 rb = (u_char *) (((ulong) rb + 1) & ~1); 207 208 tb[0] = addr; /* Device address byte w/rw flag */ 209 210 out_be16(&tbdf->cbd_datlen, pmsg->len + 1); 211 out_be16(&tbdf->cbd_sc, 0); 212 213 if (!(pmsg->flags & I2C_M_NOSTART)) 214 setbits16(&tbdf->cbd_sc, BD_I2C_START); 215 216 if (tx + 1 == num) 217 setbits16(&tbdf->cbd_sc, BD_SC_LAST | BD_SC_WRAP); 218 219 if (pmsg->flags & I2C_M_RD) { 220 /* 221 * To read, we need an empty buffer of the proper length. 222 * All that is used is the first byte for address, the remainder 223 * is just used for timing (and doesn't really have to exist). 224 */ 225 226 dev_dbg(&adap->dev, "cpm_i2c_read(abyte=0x%x)\n", addr); 227 228 out_be16(&rbdf->cbd_datlen, 0); 229 out_be16(&rbdf->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT); 230 231 if (rx + 1 == CPM_MAXBD) 232 setbits16(&rbdf->cbd_sc, BD_SC_WRAP); 233 234 eieio(); 235 setbits16(&tbdf->cbd_sc, BD_SC_READY); 236 } else { 237 dev_dbg(&adap->dev, "cpm_i2c_write(abyte=0x%x)\n", addr); 238 239 memcpy(tb+1, pmsg->buf, pmsg->len); 240 241 eieio(); 242 setbits16(&tbdf->cbd_sc, BD_SC_READY | BD_SC_INTRPT); 243 } 244 } 245 246 static int cpm_i2c_check_message(struct i2c_adapter *adap, 247 struct i2c_msg *pmsg, int tx, int rx) 248 { 249 cbd_t __iomem *tbdf; 250 cbd_t __iomem *rbdf; 251 u_char *tb; 252 u_char *rb; 253 struct cpm_i2c *cpm = i2c_get_adapdata(adap); 254 255 tbdf = cpm->tbase + tx; 256 rbdf = cpm->rbase + rx; 257 258 tb = cpm->txbuf[tx]; 259 rb = cpm->rxbuf[rx]; 260 261 /* Align read buffer */ 262 rb = (u_char *) (((uint) rb + 1) & ~1); 263 264 eieio(); 265 if (pmsg->flags & I2C_M_RD) { 266 dev_dbg(&adap->dev, "tx sc 0x%04x, rx sc 0x%04x\n", 267 in_be16(&tbdf->cbd_sc), in_be16(&rbdf->cbd_sc)); 268 269 if (in_be16(&tbdf->cbd_sc) & BD_SC_NAK) { 270 dev_dbg(&adap->dev, "I2C read; No ack\n"); 271 return -ENXIO; 272 } 273 if (in_be16(&rbdf->cbd_sc) & BD_SC_EMPTY) { 274 dev_err(&adap->dev, 275 "I2C read; complete but rbuf empty\n"); 276 return -EREMOTEIO; 277 } 278 if (in_be16(&rbdf->cbd_sc) & BD_SC_OV) { 279 dev_err(&adap->dev, "I2C read; Overrun\n"); 280 return -EREMOTEIO; 281 } 282 memcpy(pmsg->buf, rb, pmsg->len); 283 } else { 284 dev_dbg(&adap->dev, "tx sc %d 0x%04x\n", tx, 285 in_be16(&tbdf->cbd_sc)); 286 287 if (in_be16(&tbdf->cbd_sc) & BD_SC_NAK) { 288 dev_dbg(&adap->dev, "I2C write; No ack\n"); 289 return -ENXIO; 290 } 291 if (in_be16(&tbdf->cbd_sc) & BD_SC_UN) { 292 dev_err(&adap->dev, "I2C write; Underrun\n"); 293 return -EIO; 294 } 295 if (in_be16(&tbdf->cbd_sc) & BD_SC_CL) { 296 dev_err(&adap->dev, "I2C write; Collision\n"); 297 return -EIO; 298 } 299 } 300 return 0; 301 } 302 303 static int cpm_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 304 { 305 struct cpm_i2c *cpm = i2c_get_adapdata(adap); 306 struct i2c_reg __iomem *i2c_reg = cpm->i2c_reg; 307 struct i2c_ram __iomem *i2c_ram = cpm->i2c_ram; 308 struct i2c_msg *pmsg; 309 int ret; 310 int tptr; 311 int rptr; 312 cbd_t __iomem *tbdf; 313 cbd_t __iomem *rbdf; 314 315 /* Reset to use first buffer */ 316 out_be16(&i2c_ram->rbptr, in_be16(&i2c_ram->rbase)); 317 out_be16(&i2c_ram->tbptr, in_be16(&i2c_ram->tbase)); 318 319 tbdf = cpm->tbase; 320 rbdf = cpm->rbase; 321 322 tptr = 0; 323 rptr = 0; 324 325 /* 326 * If there was a collision in the last i2c transaction, 327 * Set I2COM_MASTER as it was cleared during collision. 328 */ 329 if (in_be16(&tbdf->cbd_sc) & BD_SC_CL) { 330 out_8(&cpm->i2c_reg->i2com, I2COM_MASTER); 331 } 332 333 while (tptr < num) { 334 pmsg = &msgs[tptr]; 335 dev_dbg(&adap->dev, "R: %d T: %d\n", rptr, tptr); 336 337 cpm_i2c_parse_message(adap, pmsg, num, tptr, rptr); 338 if (pmsg->flags & I2C_M_RD) 339 rptr++; 340 tptr++; 341 } 342 /* Start transfer now */ 343 /* Enable RX/TX/Error interupts */ 344 out_8(&i2c_reg->i2cmr, I2CER_TXE | I2CER_TXB | I2CER_RXB); 345 out_8(&i2c_reg->i2cer, 0xff); /* Clear interrupt status */ 346 /* Chip bug, set enable here */ 347 setbits8(&i2c_reg->i2mod, I2MOD_EN); /* Enable */ 348 /* Begin transmission */ 349 setbits8(&i2c_reg->i2com, I2COM_START); 350 351 tptr = 0; 352 rptr = 0; 353 354 while (tptr < num) { 355 /* Check for outstanding messages */ 356 dev_dbg(&adap->dev, "test ready.\n"); 357 pmsg = &msgs[tptr]; 358 if (pmsg->flags & I2C_M_RD) 359 ret = wait_event_timeout(cpm->i2c_wait, 360 (in_be16(&tbdf[tptr].cbd_sc) & BD_SC_NAK) || 361 !(in_be16(&rbdf[rptr].cbd_sc) & BD_SC_EMPTY), 362 1 * HZ); 363 else 364 ret = wait_event_timeout(cpm->i2c_wait, 365 !(in_be16(&tbdf[tptr].cbd_sc) & BD_SC_READY), 366 1 * HZ); 367 if (ret == 0) { 368 ret = -EREMOTEIO; 369 dev_err(&adap->dev, "I2C transfer: timeout\n"); 370 goto out_err; 371 } 372 if (ret > 0) { 373 dev_dbg(&adap->dev, "ready.\n"); 374 ret = cpm_i2c_check_message(adap, pmsg, tptr, rptr); 375 tptr++; 376 if (pmsg->flags & I2C_M_RD) 377 rptr++; 378 if (ret) 379 goto out_err; 380 } 381 } 382 #ifdef I2C_CHIP_ERRATA 383 /* 384 * Chip errata, clear enable. This is not needed on rev D4 CPUs. 385 * Disabling I2C too early may cause too short stop condition 386 */ 387 udelay(4); 388 clrbits8(&i2c_reg->i2mod, I2MOD_EN); 389 #endif 390 return (num); 391 392 out_err: 393 cpm_i2c_force_close(adap); 394 #ifdef I2C_CHIP_ERRATA 395 /* 396 * Chip errata, clear enable. This is not needed on rev D4 CPUs. 397 */ 398 clrbits8(&i2c_reg->i2mod, I2MOD_EN); 399 #endif 400 return ret; 401 } 402 403 static u32 cpm_i2c_func(struct i2c_adapter *adap) 404 { 405 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 406 } 407 408 /* -----exported algorithm data: ------------------------------------- */ 409 410 static const struct i2c_algorithm cpm_i2c_algo = { 411 .master_xfer = cpm_i2c_xfer, 412 .functionality = cpm_i2c_func, 413 }; 414 415 /* CPM_MAX_READ is also limiting writes according to the code! */ 416 static struct i2c_adapter_quirks cpm_i2c_quirks = { 417 .max_num_msgs = CPM_MAXBD, 418 .max_read_len = CPM_MAX_READ, 419 .max_write_len = CPM_MAX_READ, 420 }; 421 422 static const struct i2c_adapter cpm_ops = { 423 .owner = THIS_MODULE, 424 .name = "i2c-cpm", 425 .algo = &cpm_i2c_algo, 426 .quirks = &cpm_i2c_quirks, 427 }; 428 429 static int cpm_i2c_setup(struct cpm_i2c *cpm) 430 { 431 struct platform_device *ofdev = cpm->ofdev; 432 const u32 *data; 433 int len, ret, i; 434 void __iomem *i2c_base; 435 cbd_t __iomem *tbdf; 436 cbd_t __iomem *rbdf; 437 unsigned char brg; 438 439 dev_dbg(&cpm->ofdev->dev, "cpm_i2c_setup()\n"); 440 441 init_waitqueue_head(&cpm->i2c_wait); 442 443 cpm->irq = irq_of_parse_and_map(ofdev->dev.of_node, 0); 444 if (!cpm->irq) 445 return -EINVAL; 446 447 /* Install interrupt handler. */ 448 ret = request_irq(cpm->irq, cpm_i2c_interrupt, 0, "cpm_i2c", 449 &cpm->adap); 450 if (ret) 451 return ret; 452 453 /* I2C parameter RAM */ 454 i2c_base = of_iomap(ofdev->dev.of_node, 1); 455 if (i2c_base == NULL) { 456 ret = -EINVAL; 457 goto out_irq; 458 } 459 460 if (of_device_is_compatible(ofdev->dev.of_node, "fsl,cpm1-i2c")) { 461 462 /* Check for and use a microcode relocation patch. */ 463 cpm->i2c_ram = i2c_base; 464 cpm->i2c_addr = in_be16(&cpm->i2c_ram->rpbase); 465 466 /* 467 * Maybe should use cpm_muram_alloc instead of hardcoding 468 * this in micropatch.c 469 */ 470 if (cpm->i2c_addr) { 471 cpm->i2c_ram = cpm_muram_addr(cpm->i2c_addr); 472 iounmap(i2c_base); 473 } 474 475 cpm->version = 1; 476 477 } else if (of_device_is_compatible(ofdev->dev.of_node, "fsl,cpm2-i2c")) { 478 cpm->i2c_addr = cpm_muram_alloc(sizeof(struct i2c_ram), 64); 479 cpm->i2c_ram = cpm_muram_addr(cpm->i2c_addr); 480 out_be16(i2c_base, cpm->i2c_addr); 481 iounmap(i2c_base); 482 483 cpm->version = 2; 484 485 } else { 486 iounmap(i2c_base); 487 ret = -EINVAL; 488 goto out_irq; 489 } 490 491 /* I2C control/status registers */ 492 cpm->i2c_reg = of_iomap(ofdev->dev.of_node, 0); 493 if (cpm->i2c_reg == NULL) { 494 ret = -EINVAL; 495 goto out_ram; 496 } 497 498 data = of_get_property(ofdev->dev.of_node, "fsl,cpm-command", &len); 499 if (!data || len != 4) { 500 ret = -EINVAL; 501 goto out_reg; 502 } 503 cpm->cp_command = *data; 504 505 data = of_get_property(ofdev->dev.of_node, "linux,i2c-class", &len); 506 if (data && len == 4) 507 cpm->adap.class = *data; 508 509 data = of_get_property(ofdev->dev.of_node, "clock-frequency", &len); 510 if (data && len == 4) 511 cpm->freq = *data; 512 else 513 cpm->freq = 60000; /* use 60kHz i2c clock by default */ 514 515 /* 516 * Allocate space for CPM_MAXBD transmit and receive buffer 517 * descriptors in the DP ram. 518 */ 519 cpm->dp_addr = cpm_muram_alloc(sizeof(cbd_t) * 2 * CPM_MAXBD, 8); 520 if (!cpm->dp_addr) { 521 ret = -ENOMEM; 522 goto out_reg; 523 } 524 525 cpm->tbase = cpm_muram_addr(cpm->dp_addr); 526 cpm->rbase = cpm_muram_addr(cpm->dp_addr + sizeof(cbd_t) * CPM_MAXBD); 527 528 /* Allocate TX and RX buffers */ 529 530 tbdf = cpm->tbase; 531 rbdf = cpm->rbase; 532 533 for (i = 0; i < CPM_MAXBD; i++) { 534 cpm->rxbuf[i] = dma_alloc_coherent(&cpm->ofdev->dev, 535 CPM_MAX_READ + 1, 536 &cpm->rxdma[i], GFP_KERNEL); 537 if (!cpm->rxbuf[i]) { 538 ret = -ENOMEM; 539 goto out_muram; 540 } 541 out_be32(&rbdf[i].cbd_bufaddr, ((cpm->rxdma[i] + 1) & ~1)); 542 543 cpm->txbuf[i] = (unsigned char *)dma_alloc_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1, &cpm->txdma[i], GFP_KERNEL); 544 if (!cpm->txbuf[i]) { 545 ret = -ENOMEM; 546 goto out_muram; 547 } 548 out_be32(&tbdf[i].cbd_bufaddr, cpm->txdma[i]); 549 } 550 551 /* Initialize Tx/Rx parameters. */ 552 553 cpm_reset_i2c_params(cpm); 554 555 dev_dbg(&cpm->ofdev->dev, "i2c_ram 0x%p, i2c_addr 0x%04x, freq %d\n", 556 cpm->i2c_ram, cpm->i2c_addr, cpm->freq); 557 dev_dbg(&cpm->ofdev->dev, "tbase 0x%04x, rbase 0x%04x\n", 558 (u8 __iomem *)cpm->tbase - DPRAM_BASE, 559 (u8 __iomem *)cpm->rbase - DPRAM_BASE); 560 561 cpm_command(cpm->cp_command, CPM_CR_INIT_TRX); 562 563 /* 564 * Select an invalid address. Just make sure we don't use loopback mode 565 */ 566 out_8(&cpm->i2c_reg->i2add, 0x7f << 1); 567 568 /* 569 * PDIV is set to 00 in i2mod, so brgclk/32 is used as input to the 570 * i2c baud rate generator. This is divided by 2 x (DIV + 3) to get 571 * the actual i2c bus frequency. 572 */ 573 brg = get_brgfreq() / (32 * 2 * cpm->freq) - 3; 574 out_8(&cpm->i2c_reg->i2brg, brg); 575 576 out_8(&cpm->i2c_reg->i2mod, 0x00); 577 out_8(&cpm->i2c_reg->i2com, I2COM_MASTER); /* Master mode */ 578 579 /* Disable interrupts. */ 580 out_8(&cpm->i2c_reg->i2cmr, 0); 581 out_8(&cpm->i2c_reg->i2cer, 0xff); 582 583 return 0; 584 585 out_muram: 586 for (i = 0; i < CPM_MAXBD; i++) { 587 if (cpm->rxbuf[i]) 588 dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1, 589 cpm->rxbuf[i], cpm->rxdma[i]); 590 if (cpm->txbuf[i]) 591 dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1, 592 cpm->txbuf[i], cpm->txdma[i]); 593 } 594 cpm_muram_free(cpm->dp_addr); 595 out_reg: 596 iounmap(cpm->i2c_reg); 597 out_ram: 598 if ((cpm->version == 1) && (!cpm->i2c_addr)) 599 iounmap(cpm->i2c_ram); 600 if (cpm->version == 2) 601 cpm_muram_free(cpm->i2c_addr); 602 out_irq: 603 free_irq(cpm->irq, &cpm->adap); 604 return ret; 605 } 606 607 static void cpm_i2c_shutdown(struct cpm_i2c *cpm) 608 { 609 int i; 610 611 /* Shut down I2C. */ 612 clrbits8(&cpm->i2c_reg->i2mod, I2MOD_EN); 613 614 /* Disable interrupts */ 615 out_8(&cpm->i2c_reg->i2cmr, 0); 616 out_8(&cpm->i2c_reg->i2cer, 0xff); 617 618 free_irq(cpm->irq, &cpm->adap); 619 620 /* Free all memory */ 621 for (i = 0; i < CPM_MAXBD; i++) { 622 dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1, 623 cpm->rxbuf[i], cpm->rxdma[i]); 624 dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1, 625 cpm->txbuf[i], cpm->txdma[i]); 626 } 627 628 cpm_muram_free(cpm->dp_addr); 629 iounmap(cpm->i2c_reg); 630 631 if ((cpm->version == 1) && (!cpm->i2c_addr)) 632 iounmap(cpm->i2c_ram); 633 if (cpm->version == 2) 634 cpm_muram_free(cpm->i2c_addr); 635 } 636 637 static int cpm_i2c_probe(struct platform_device *ofdev) 638 { 639 int result, len; 640 struct cpm_i2c *cpm; 641 const u32 *data; 642 643 cpm = kzalloc(sizeof(struct cpm_i2c), GFP_KERNEL); 644 if (!cpm) 645 return -ENOMEM; 646 647 cpm->ofdev = ofdev; 648 649 platform_set_drvdata(ofdev, cpm); 650 651 cpm->adap = cpm_ops; 652 i2c_set_adapdata(&cpm->adap, cpm); 653 cpm->adap.dev.parent = &ofdev->dev; 654 cpm->adap.dev.of_node = of_node_get(ofdev->dev.of_node); 655 656 result = cpm_i2c_setup(cpm); 657 if (result) { 658 dev_err(&ofdev->dev, "Unable to init hardware\n"); 659 goto out_free; 660 } 661 662 /* register new adapter to i2c module... */ 663 664 data = of_get_property(ofdev->dev.of_node, "linux,i2c-index", &len); 665 cpm->adap.nr = (data && len == 4) ? be32_to_cpup(data) : -1; 666 result = i2c_add_numbered_adapter(&cpm->adap); 667 668 if (result < 0) { 669 dev_err(&ofdev->dev, "Unable to register with I2C\n"); 670 goto out_shut; 671 } 672 673 dev_dbg(&ofdev->dev, "hw routines for %s registered.\n", 674 cpm->adap.name); 675 676 return 0; 677 out_shut: 678 cpm_i2c_shutdown(cpm); 679 out_free: 680 kfree(cpm); 681 682 return result; 683 } 684 685 static int cpm_i2c_remove(struct platform_device *ofdev) 686 { 687 struct cpm_i2c *cpm = platform_get_drvdata(ofdev); 688 689 i2c_del_adapter(&cpm->adap); 690 691 cpm_i2c_shutdown(cpm); 692 693 kfree(cpm); 694 695 return 0; 696 } 697 698 static const struct of_device_id cpm_i2c_match[] = { 699 { 700 .compatible = "fsl,cpm1-i2c", 701 }, 702 { 703 .compatible = "fsl,cpm2-i2c", 704 }, 705 {}, 706 }; 707 708 MODULE_DEVICE_TABLE(of, cpm_i2c_match); 709 710 static struct platform_driver cpm_i2c_driver = { 711 .probe = cpm_i2c_probe, 712 .remove = cpm_i2c_remove, 713 .driver = { 714 .name = "fsl-i2c-cpm", 715 .of_match_table = cpm_i2c_match, 716 }, 717 }; 718 719 module_platform_driver(cpm_i2c_driver); 720 721 MODULE_AUTHOR("Jochen Friedrich <jochen@scram.de>"); 722 MODULE_DESCRIPTION("I2C-Bus adapter routines for CPM boards"); 723 MODULE_LICENSE("GPL"); 724