1 /* 2 * Intel CHT Whiskey Cove PMIC I2C Master driver 3 * Copyright (C) 2017 Hans de Goede <hdegoede@redhat.com> 4 * 5 * Based on various non upstream patches to support the CHT Whiskey Cove PMIC: 6 * Copyright (C) 2011 - 2014 Intel Corporation. All rights reserved. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License version 10 * 2 as published by the Free Software Foundation, or (at your option) 11 * any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include <linux/completion.h> 20 #include <linux/delay.h> 21 #include <linux/i2c.h> 22 #include <linux/interrupt.h> 23 #include <linux/irq.h> 24 #include <linux/irqdomain.h> 25 #include <linux/mfd/intel_soc_pmic.h> 26 #include <linux/module.h> 27 #include <linux/platform_device.h> 28 #include <linux/slab.h> 29 30 #define CHT_WC_I2C_CTRL 0x5e24 31 #define CHT_WC_I2C_CTRL_WR BIT(0) 32 #define CHT_WC_I2C_CTRL_RD BIT(1) 33 #define CHT_WC_I2C_CLIENT_ADDR 0x5e25 34 #define CHT_WC_I2C_REG_OFFSET 0x5e26 35 #define CHT_WC_I2C_WRDATA 0x5e27 36 #define CHT_WC_I2C_RDDATA 0x5e28 37 38 #define CHT_WC_EXTCHGRIRQ 0x6e0a 39 #define CHT_WC_EXTCHGRIRQ_CLIENT_IRQ BIT(0) 40 #define CHT_WC_EXTCHGRIRQ_WRITE_IRQ BIT(1) 41 #define CHT_WC_EXTCHGRIRQ_READ_IRQ BIT(2) 42 #define CHT_WC_EXTCHGRIRQ_NACK_IRQ BIT(3) 43 #define CHT_WC_EXTCHGRIRQ_ADAP_IRQMASK ((u8)GENMASK(3, 1)) 44 #define CHT_WC_EXTCHGRIRQ_MSK 0x6e17 45 46 struct cht_wc_i2c_adap { 47 struct i2c_adapter adapter; 48 wait_queue_head_t wait; 49 struct irq_chip irqchip; 50 struct mutex adap_lock; 51 struct mutex irqchip_lock; 52 struct regmap *regmap; 53 struct irq_domain *irq_domain; 54 struct i2c_client *client; 55 int client_irq; 56 u8 irq_mask; 57 u8 old_irq_mask; 58 int read_data; 59 bool io_error; 60 bool done; 61 }; 62 63 static irqreturn_t cht_wc_i2c_adap_thread_handler(int id, void *data) 64 { 65 struct cht_wc_i2c_adap *adap = data; 66 int ret, reg; 67 68 mutex_lock(&adap->adap_lock); 69 70 /* Read IRQs */ 71 ret = regmap_read(adap->regmap, CHT_WC_EXTCHGRIRQ, ®); 72 if (ret) { 73 dev_err(&adap->adapter.dev, "Error reading extchgrirq reg\n"); 74 mutex_unlock(&adap->adap_lock); 75 return IRQ_NONE; 76 } 77 78 reg &= ~adap->irq_mask; 79 80 /* Reads must be acked after reading the received data. */ 81 ret = regmap_read(adap->regmap, CHT_WC_I2C_RDDATA, &adap->read_data); 82 if (ret) 83 adap->io_error = true; 84 85 /* 86 * Immediately ack IRQs, so that if new IRQs arrives while we're 87 * handling the previous ones our irq will re-trigger when we're done. 88 */ 89 ret = regmap_write(adap->regmap, CHT_WC_EXTCHGRIRQ, reg); 90 if (ret) 91 dev_err(&adap->adapter.dev, "Error writing extchgrirq reg\n"); 92 93 if (reg & CHT_WC_EXTCHGRIRQ_ADAP_IRQMASK) { 94 adap->io_error |= !!(reg & CHT_WC_EXTCHGRIRQ_NACK_IRQ); 95 adap->done = true; 96 } 97 98 mutex_unlock(&adap->adap_lock); 99 100 if (reg & CHT_WC_EXTCHGRIRQ_ADAP_IRQMASK) 101 wake_up(&adap->wait); 102 103 /* 104 * Do NOT use handle_nested_irq here, the client irq handler will 105 * likely want to do i2c transfers and the i2c controller uses this 106 * interrupt handler as well, so running the client irq handler from 107 * this thread will cause things to lock up. 108 */ 109 if (reg & CHT_WC_EXTCHGRIRQ_CLIENT_IRQ) { 110 /* 111 * generic_handle_irq expects local IRQs to be disabled 112 * as normally it is called from interrupt context. 113 */ 114 local_irq_disable(); 115 generic_handle_irq(adap->client_irq); 116 local_irq_enable(); 117 } 118 119 return IRQ_HANDLED; 120 } 121 122 static u32 cht_wc_i2c_adap_master_func(struct i2c_adapter *adap) 123 { 124 /* This i2c adapter only supports SMBUS byte transfers */ 125 return I2C_FUNC_SMBUS_BYTE_DATA; 126 } 127 128 static int cht_wc_i2c_adap_smbus_xfer(struct i2c_adapter *_adap, u16 addr, 129 unsigned short flags, char read_write, 130 u8 command, int size, 131 union i2c_smbus_data *data) 132 { 133 struct cht_wc_i2c_adap *adap = i2c_get_adapdata(_adap); 134 int ret; 135 136 mutex_lock(&adap->adap_lock); 137 adap->io_error = false; 138 adap->done = false; 139 mutex_unlock(&adap->adap_lock); 140 141 ret = regmap_write(adap->regmap, CHT_WC_I2C_CLIENT_ADDR, addr); 142 if (ret) 143 return ret; 144 145 if (read_write == I2C_SMBUS_WRITE) { 146 ret = regmap_write(adap->regmap, CHT_WC_I2C_WRDATA, data->byte); 147 if (ret) 148 return ret; 149 } 150 151 ret = regmap_write(adap->regmap, CHT_WC_I2C_REG_OFFSET, command); 152 if (ret) 153 return ret; 154 155 ret = regmap_write(adap->regmap, CHT_WC_I2C_CTRL, 156 (read_write == I2C_SMBUS_WRITE) ? 157 CHT_WC_I2C_CTRL_WR : CHT_WC_I2C_CTRL_RD); 158 if (ret) 159 return ret; 160 161 ret = wait_event_timeout(adap->wait, adap->done, msecs_to_jiffies(30)); 162 if (ret == 0) { 163 /* 164 * The CHT GPIO controller serializes all IRQs, sometimes 165 * causing significant delays, check status manually. 166 */ 167 cht_wc_i2c_adap_thread_handler(0, adap); 168 if (!adap->done) 169 return -ETIMEDOUT; 170 } 171 172 ret = 0; 173 mutex_lock(&adap->adap_lock); 174 if (adap->io_error) 175 ret = -EIO; 176 else if (read_write == I2C_SMBUS_READ) 177 data->byte = adap->read_data; 178 mutex_unlock(&adap->adap_lock); 179 180 return ret; 181 } 182 183 static const struct i2c_algorithm cht_wc_i2c_adap_algo = { 184 .functionality = cht_wc_i2c_adap_master_func, 185 .smbus_xfer = cht_wc_i2c_adap_smbus_xfer, 186 }; 187 188 /**** irqchip for the client connected to the extchgr i2c adapter ****/ 189 static void cht_wc_i2c_irq_lock(struct irq_data *data) 190 { 191 struct cht_wc_i2c_adap *adap = irq_data_get_irq_chip_data(data); 192 193 mutex_lock(&adap->irqchip_lock); 194 } 195 196 static void cht_wc_i2c_irq_sync_unlock(struct irq_data *data) 197 { 198 struct cht_wc_i2c_adap *adap = irq_data_get_irq_chip_data(data); 199 int ret; 200 201 if (adap->irq_mask != adap->old_irq_mask) { 202 ret = regmap_write(adap->regmap, CHT_WC_EXTCHGRIRQ_MSK, 203 adap->irq_mask); 204 if (ret == 0) 205 adap->old_irq_mask = adap->irq_mask; 206 else 207 dev_err(&adap->adapter.dev, "Error writing EXTCHGRIRQ_MSK\n"); 208 } 209 210 mutex_unlock(&adap->irqchip_lock); 211 } 212 213 static void cht_wc_i2c_irq_enable(struct irq_data *data) 214 { 215 struct cht_wc_i2c_adap *adap = irq_data_get_irq_chip_data(data); 216 217 adap->irq_mask &= ~CHT_WC_EXTCHGRIRQ_CLIENT_IRQ; 218 } 219 220 static void cht_wc_i2c_irq_disable(struct irq_data *data) 221 { 222 struct cht_wc_i2c_adap *adap = irq_data_get_irq_chip_data(data); 223 224 adap->irq_mask |= CHT_WC_EXTCHGRIRQ_CLIENT_IRQ; 225 } 226 227 static const struct irq_chip cht_wc_i2c_irq_chip = { 228 .irq_bus_lock = cht_wc_i2c_irq_lock, 229 .irq_bus_sync_unlock = cht_wc_i2c_irq_sync_unlock, 230 .irq_disable = cht_wc_i2c_irq_disable, 231 .irq_enable = cht_wc_i2c_irq_enable, 232 .name = "cht_wc_ext_chrg_irq_chip", 233 }; 234 235 static const struct property_entry bq24190_props[] = { 236 PROPERTY_ENTRY_STRING("extcon-name", "cht_wcove_pwrsrc"), 237 PROPERTY_ENTRY_BOOL("omit-battery-class"), 238 PROPERTY_ENTRY_BOOL("disable-reset"), 239 { } 240 }; 241 242 static int cht_wc_i2c_adap_i2c_probe(struct platform_device *pdev) 243 { 244 struct intel_soc_pmic *pmic = dev_get_drvdata(pdev->dev.parent); 245 struct cht_wc_i2c_adap *adap; 246 struct i2c_board_info board_info = { 247 .type = "bq24190", 248 .addr = 0x6b, 249 .properties = bq24190_props, 250 }; 251 int ret, reg, irq; 252 253 irq = platform_get_irq(pdev, 0); 254 if (irq < 0) { 255 dev_err(&pdev->dev, "Error missing irq resource\n"); 256 return -EINVAL; 257 } 258 259 adap = devm_kzalloc(&pdev->dev, sizeof(*adap), GFP_KERNEL); 260 if (!adap) 261 return -ENOMEM; 262 263 init_waitqueue_head(&adap->wait); 264 mutex_init(&adap->adap_lock); 265 mutex_init(&adap->irqchip_lock); 266 adap->irqchip = cht_wc_i2c_irq_chip; 267 adap->regmap = pmic->regmap; 268 adap->adapter.owner = THIS_MODULE; 269 adap->adapter.class = I2C_CLASS_HWMON; 270 adap->adapter.algo = &cht_wc_i2c_adap_algo; 271 strlcpy(adap->adapter.name, "PMIC I2C Adapter", 272 sizeof(adap->adapter.name)); 273 adap->adapter.dev.parent = &pdev->dev; 274 275 /* Clear and activate i2c-adapter interrupts, disable client IRQ */ 276 adap->old_irq_mask = adap->irq_mask = ~CHT_WC_EXTCHGRIRQ_ADAP_IRQMASK; 277 278 ret = regmap_read(adap->regmap, CHT_WC_I2C_RDDATA, ®); 279 if (ret) 280 return ret; 281 282 ret = regmap_write(adap->regmap, CHT_WC_EXTCHGRIRQ, ~adap->irq_mask); 283 if (ret) 284 return ret; 285 286 ret = regmap_write(adap->regmap, CHT_WC_EXTCHGRIRQ_MSK, adap->irq_mask); 287 if (ret) 288 return ret; 289 290 /* Alloc and register client IRQ */ 291 adap->irq_domain = irq_domain_add_linear(pdev->dev.of_node, 1, 292 &irq_domain_simple_ops, NULL); 293 if (!adap->irq_domain) 294 return -ENOMEM; 295 296 adap->client_irq = irq_create_mapping(adap->irq_domain, 0); 297 if (!adap->client_irq) { 298 ret = -ENOMEM; 299 goto remove_irq_domain; 300 } 301 302 irq_set_chip_data(adap->client_irq, adap); 303 irq_set_chip_and_handler(adap->client_irq, &adap->irqchip, 304 handle_simple_irq); 305 306 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 307 cht_wc_i2c_adap_thread_handler, 308 IRQF_ONESHOT, "PMIC I2C Adapter", adap); 309 if (ret) 310 goto remove_irq_domain; 311 312 i2c_set_adapdata(&adap->adapter, adap); 313 ret = i2c_add_adapter(&adap->adapter); 314 if (ret) 315 goto remove_irq_domain; 316 317 board_info.irq = adap->client_irq; 318 adap->client = i2c_new_device(&adap->adapter, &board_info); 319 if (!adap->client) { 320 ret = -ENOMEM; 321 goto del_adapter; 322 } 323 324 platform_set_drvdata(pdev, adap); 325 return 0; 326 327 del_adapter: 328 i2c_del_adapter(&adap->adapter); 329 remove_irq_domain: 330 irq_domain_remove(adap->irq_domain); 331 return ret; 332 } 333 334 static int cht_wc_i2c_adap_i2c_remove(struct platform_device *pdev) 335 { 336 struct cht_wc_i2c_adap *adap = platform_get_drvdata(pdev); 337 338 i2c_unregister_device(adap->client); 339 i2c_del_adapter(&adap->adapter); 340 irq_domain_remove(adap->irq_domain); 341 342 return 0; 343 } 344 345 static struct platform_device_id cht_wc_i2c_adap_id_table[] = { 346 { .name = "cht_wcove_ext_chgr" }, 347 {}, 348 }; 349 MODULE_DEVICE_TABLE(platform, cht_wc_i2c_adap_id_table); 350 351 static struct platform_driver cht_wc_i2c_adap_driver = { 352 .probe = cht_wc_i2c_adap_i2c_probe, 353 .remove = cht_wc_i2c_adap_i2c_remove, 354 .driver = { 355 .name = "cht_wcove_ext_chgr", 356 }, 357 .id_table = cht_wc_i2c_adap_id_table, 358 }; 359 module_platform_driver(cht_wc_i2c_adap_driver); 360 361 MODULE_DESCRIPTION("Intel CHT Whiskey Cove PMIC I2C Master driver"); 362 MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>"); 363 MODULE_LICENSE("GPL"); 364