1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * I2C bus driver for the Cadence I2C controller. 4 * 5 * Copyright (C) 2009 - 2014 Xilinx, Inc. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/i2c.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/module.h> 14 #include <linux/platform_device.h> 15 #include <linux/of.h> 16 #include <linux/pm_runtime.h> 17 18 /* Register offsets for the I2C device. */ 19 #define CDNS_I2C_CR_OFFSET 0x00 /* Control Register, RW */ 20 #define CDNS_I2C_SR_OFFSET 0x04 /* Status Register, RO */ 21 #define CDNS_I2C_ADDR_OFFSET 0x08 /* I2C Address Register, RW */ 22 #define CDNS_I2C_DATA_OFFSET 0x0C /* I2C Data Register, RW */ 23 #define CDNS_I2C_ISR_OFFSET 0x10 /* IRQ Status Register, RW */ 24 #define CDNS_I2C_XFER_SIZE_OFFSET 0x14 /* Transfer Size Register, RW */ 25 #define CDNS_I2C_TIME_OUT_OFFSET 0x1C /* Time Out Register, RW */ 26 #define CDNS_I2C_IMR_OFFSET 0x20 /* IRQ Mask Register, RO */ 27 #define CDNS_I2C_IER_OFFSET 0x24 /* IRQ Enable Register, WO */ 28 #define CDNS_I2C_IDR_OFFSET 0x28 /* IRQ Disable Register, WO */ 29 30 /* Control Register Bit mask definitions */ 31 #define CDNS_I2C_CR_HOLD BIT(4) /* Hold Bus bit */ 32 #define CDNS_I2C_CR_ACK_EN BIT(3) 33 #define CDNS_I2C_CR_NEA BIT(2) 34 #define CDNS_I2C_CR_MS BIT(1) 35 /* Read or Write Master transfer 0 = Transmitter, 1 = Receiver */ 36 #define CDNS_I2C_CR_RW BIT(0) 37 /* 1 = Auto init FIFO to zeroes */ 38 #define CDNS_I2C_CR_CLR_FIFO BIT(6) 39 #define CDNS_I2C_CR_DIVA_SHIFT 14 40 #define CDNS_I2C_CR_DIVA_MASK (3 << CDNS_I2C_CR_DIVA_SHIFT) 41 #define CDNS_I2C_CR_DIVB_SHIFT 8 42 #define CDNS_I2C_CR_DIVB_MASK (0x3f << CDNS_I2C_CR_DIVB_SHIFT) 43 44 #define CDNS_I2C_CR_MASTER_EN_MASK (CDNS_I2C_CR_NEA | \ 45 CDNS_I2C_CR_ACK_EN | \ 46 CDNS_I2C_CR_MS) 47 48 #define CDNS_I2C_CR_SLAVE_EN_MASK ~CDNS_I2C_CR_MASTER_EN_MASK 49 50 /* Status Register Bit mask definitions */ 51 #define CDNS_I2C_SR_BA BIT(8) 52 #define CDNS_I2C_SR_TXDV BIT(6) 53 #define CDNS_I2C_SR_RXDV BIT(5) 54 #define CDNS_I2C_SR_RXRW BIT(3) 55 56 /* 57 * I2C Address Register Bit mask definitions 58 * Normal addressing mode uses [6:0] bits. Extended addressing mode uses [9:0] 59 * bits. A write access to this register always initiates a transfer if the I2C 60 * is in master mode. 61 */ 62 #define CDNS_I2C_ADDR_MASK 0x000003FF /* I2C Address Mask */ 63 64 /* 65 * I2C Interrupt Registers Bit mask definitions 66 * All the four interrupt registers (Status/Mask/Enable/Disable) have the same 67 * bit definitions. 68 */ 69 #define CDNS_I2C_IXR_ARB_LOST BIT(9) 70 #define CDNS_I2C_IXR_RX_UNF BIT(7) 71 #define CDNS_I2C_IXR_TX_OVF BIT(6) 72 #define CDNS_I2C_IXR_RX_OVF BIT(5) 73 #define CDNS_I2C_IXR_SLV_RDY BIT(4) 74 #define CDNS_I2C_IXR_TO BIT(3) 75 #define CDNS_I2C_IXR_NACK BIT(2) 76 #define CDNS_I2C_IXR_DATA BIT(1) 77 #define CDNS_I2C_IXR_COMP BIT(0) 78 79 #define CDNS_I2C_IXR_ALL_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \ 80 CDNS_I2C_IXR_RX_UNF | \ 81 CDNS_I2C_IXR_TX_OVF | \ 82 CDNS_I2C_IXR_RX_OVF | \ 83 CDNS_I2C_IXR_SLV_RDY | \ 84 CDNS_I2C_IXR_TO | \ 85 CDNS_I2C_IXR_NACK | \ 86 CDNS_I2C_IXR_DATA | \ 87 CDNS_I2C_IXR_COMP) 88 89 #define CDNS_I2C_IXR_ERR_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \ 90 CDNS_I2C_IXR_RX_UNF | \ 91 CDNS_I2C_IXR_TX_OVF | \ 92 CDNS_I2C_IXR_RX_OVF | \ 93 CDNS_I2C_IXR_NACK) 94 95 #define CDNS_I2C_ENABLED_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \ 96 CDNS_I2C_IXR_RX_UNF | \ 97 CDNS_I2C_IXR_TX_OVF | \ 98 CDNS_I2C_IXR_RX_OVF | \ 99 CDNS_I2C_IXR_NACK | \ 100 CDNS_I2C_IXR_DATA | \ 101 CDNS_I2C_IXR_COMP) 102 103 #define CDNS_I2C_IXR_SLAVE_INTR_MASK (CDNS_I2C_IXR_RX_UNF | \ 104 CDNS_I2C_IXR_TX_OVF | \ 105 CDNS_I2C_IXR_RX_OVF | \ 106 CDNS_I2C_IXR_TO | \ 107 CDNS_I2C_IXR_NACK | \ 108 CDNS_I2C_IXR_DATA | \ 109 CDNS_I2C_IXR_COMP) 110 111 #define CDNS_I2C_TIMEOUT msecs_to_jiffies(1000) 112 /* timeout for pm runtime autosuspend */ 113 #define CNDS_I2C_PM_TIMEOUT 1000 /* ms */ 114 115 #define CDNS_I2C_FIFO_DEPTH 16 116 /* FIFO depth at which the DATA interrupt occurs */ 117 #define CDNS_I2C_DATA_INTR_DEPTH (CDNS_I2C_FIFO_DEPTH - 2) 118 #define CDNS_I2C_MAX_TRANSFER_SIZE 255 119 /* Transfer size in multiples of data interrupt depth */ 120 #define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_MAX_TRANSFER_SIZE - 3) 121 122 #define DRIVER_NAME "cdns-i2c" 123 124 #define CDNS_I2C_DIVA_MAX 4 125 #define CDNS_I2C_DIVB_MAX 64 126 127 #define CDNS_I2C_TIMEOUT_MAX 0xFF 128 129 #define CDNS_I2C_BROKEN_HOLD_BIT BIT(0) 130 131 #define cdns_i2c_readreg(offset) readl_relaxed(id->membase + offset) 132 #define cdns_i2c_writereg(val, offset) writel_relaxed(val, id->membase + offset) 133 134 #if IS_ENABLED(CONFIG_I2C_SLAVE) 135 /** 136 * enum cdns_i2c_mode - I2C Controller current operating mode 137 * 138 * @CDNS_I2C_MODE_SLAVE: I2C controller operating in slave mode 139 * @CDNS_I2C_MODE_MASTER: I2C Controller operating in master mode 140 */ 141 enum cdns_i2c_mode { 142 CDNS_I2C_MODE_SLAVE, 143 CDNS_I2C_MODE_MASTER, 144 }; 145 146 /** 147 * enum cdns_i2c_slave_state - Slave state when I2C is operating in slave mode 148 * 149 * @CDNS_I2C_SLAVE_STATE_IDLE: I2C slave idle 150 * @CDNS_I2C_SLAVE_STATE_SEND: I2C slave sending data to master 151 * @CDNS_I2C_SLAVE_STATE_RECV: I2C slave receiving data from master 152 */ 153 enum cdns_i2c_slave_state { 154 CDNS_I2C_SLAVE_STATE_IDLE, 155 CDNS_I2C_SLAVE_STATE_SEND, 156 CDNS_I2C_SLAVE_STATE_RECV, 157 }; 158 #endif 159 160 /** 161 * struct cdns_i2c - I2C device private data structure 162 * 163 * @dev: Pointer to device structure 164 * @membase: Base address of the I2C device 165 * @adap: I2C adapter instance 166 * @p_msg: Message pointer 167 * @err_status: Error status in Interrupt Status Register 168 * @xfer_done: Transfer complete status 169 * @p_send_buf: Pointer to transmit buffer 170 * @p_recv_buf: Pointer to receive buffer 171 * @send_count: Number of bytes still expected to send 172 * @recv_count: Number of bytes still expected to receive 173 * @curr_recv_count: Number of bytes to be received in current transfer 174 * @irq: IRQ number 175 * @input_clk: Input clock to I2C controller 176 * @i2c_clk: Maximum I2C clock speed 177 * @bus_hold_flag: Flag used in repeated start for clearing HOLD bit 178 * @clk: Pointer to struct clk 179 * @clk_rate_change_nb: Notifier block for clock rate changes 180 * @quirks: flag for broken hold bit usage in r1p10 181 * @ctrl_reg: Cached value of the control register. 182 * @ctrl_reg_diva_divb: value of fields DIV_A and DIV_B from CR register 183 * @slave: Registered slave instance. 184 * @dev_mode: I2C operating role(master/slave). 185 * @slave_state: I2C Slave state(idle/read/write). 186 */ 187 struct cdns_i2c { 188 struct device *dev; 189 void __iomem *membase; 190 struct i2c_adapter adap; 191 struct i2c_msg *p_msg; 192 int err_status; 193 struct completion xfer_done; 194 unsigned char *p_send_buf; 195 unsigned char *p_recv_buf; 196 unsigned int send_count; 197 unsigned int recv_count; 198 unsigned int curr_recv_count; 199 int irq; 200 unsigned long input_clk; 201 unsigned int i2c_clk; 202 unsigned int bus_hold_flag; 203 struct clk *clk; 204 struct notifier_block clk_rate_change_nb; 205 u32 quirks; 206 u32 ctrl_reg; 207 #if IS_ENABLED(CONFIG_I2C_SLAVE) 208 u16 ctrl_reg_diva_divb; 209 struct i2c_client *slave; 210 enum cdns_i2c_mode dev_mode; 211 enum cdns_i2c_slave_state slave_state; 212 #endif 213 }; 214 215 struct cdns_platform_data { 216 u32 quirks; 217 }; 218 219 #define to_cdns_i2c(_nb) container_of(_nb, struct cdns_i2c, \ 220 clk_rate_change_nb) 221 222 /** 223 * cdns_i2c_clear_bus_hold - Clear bus hold bit 224 * @id: Pointer to driver data struct 225 * 226 * Helper to clear the controller's bus hold bit. 227 */ 228 static void cdns_i2c_clear_bus_hold(struct cdns_i2c *id) 229 { 230 u32 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 231 if (reg & CDNS_I2C_CR_HOLD) 232 cdns_i2c_writereg(reg & ~CDNS_I2C_CR_HOLD, CDNS_I2C_CR_OFFSET); 233 } 234 235 static inline bool cdns_is_holdquirk(struct cdns_i2c *id, bool hold_wrkaround) 236 { 237 return (hold_wrkaround && 238 (id->curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1)); 239 } 240 241 #if IS_ENABLED(CONFIG_I2C_SLAVE) 242 static void cdns_i2c_set_mode(enum cdns_i2c_mode mode, struct cdns_i2c *id) 243 { 244 /* Disable all interrupts */ 245 cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, CDNS_I2C_IDR_OFFSET); 246 247 /* Clear FIFO and transfer size */ 248 cdns_i2c_writereg(CDNS_I2C_CR_CLR_FIFO, CDNS_I2C_CR_OFFSET); 249 250 /* Update device mode and state */ 251 id->dev_mode = mode; 252 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE; 253 254 switch (mode) { 255 case CDNS_I2C_MODE_MASTER: 256 /* Enable i2c master */ 257 cdns_i2c_writereg(id->ctrl_reg_diva_divb | 258 CDNS_I2C_CR_MASTER_EN_MASK, 259 CDNS_I2C_CR_OFFSET); 260 /* 261 * This delay is needed to give the IP some time to switch to 262 * the master mode. With lower values(like 110 us) i2cdetect 263 * will not detect any slave and without this delay, the IP will 264 * trigger a timeout interrupt. 265 */ 266 usleep_range(115, 125); 267 break; 268 case CDNS_I2C_MODE_SLAVE: 269 /* Enable i2c slave */ 270 cdns_i2c_writereg(id->ctrl_reg_diva_divb & 271 CDNS_I2C_CR_SLAVE_EN_MASK, 272 CDNS_I2C_CR_OFFSET); 273 274 /* Setting slave address */ 275 cdns_i2c_writereg(id->slave->addr & CDNS_I2C_ADDR_MASK, 276 CDNS_I2C_ADDR_OFFSET); 277 278 /* Enable slave send/receive interrupts */ 279 cdns_i2c_writereg(CDNS_I2C_IXR_SLAVE_INTR_MASK, 280 CDNS_I2C_IER_OFFSET); 281 break; 282 } 283 } 284 285 static void cdns_i2c_slave_rcv_data(struct cdns_i2c *id) 286 { 287 u8 bytes; 288 unsigned char data; 289 290 /* Prepare backend for data reception */ 291 if (id->slave_state == CDNS_I2C_SLAVE_STATE_IDLE) { 292 id->slave_state = CDNS_I2C_SLAVE_STATE_RECV; 293 i2c_slave_event(id->slave, I2C_SLAVE_WRITE_REQUESTED, NULL); 294 } 295 296 /* Fetch number of bytes to receive */ 297 bytes = cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET); 298 299 /* Read data and send to backend */ 300 while (bytes--) { 301 data = cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET); 302 i2c_slave_event(id->slave, I2C_SLAVE_WRITE_RECEIVED, &data); 303 } 304 } 305 306 static void cdns_i2c_slave_send_data(struct cdns_i2c *id) 307 { 308 u8 data; 309 310 /* Prepare backend for data transmission */ 311 if (id->slave_state == CDNS_I2C_SLAVE_STATE_IDLE) { 312 id->slave_state = CDNS_I2C_SLAVE_STATE_SEND; 313 i2c_slave_event(id->slave, I2C_SLAVE_READ_REQUESTED, &data); 314 } else { 315 i2c_slave_event(id->slave, I2C_SLAVE_READ_PROCESSED, &data); 316 } 317 318 /* Send data over bus */ 319 cdns_i2c_writereg(data, CDNS_I2C_DATA_OFFSET); 320 } 321 322 /** 323 * cdns_i2c_slave_isr - Interrupt handler for the I2C device in slave role 324 * @ptr: Pointer to I2C device private data 325 * 326 * This function handles the data interrupt and transfer complete interrupt of 327 * the I2C device in slave role. 328 * 329 * Return: IRQ_HANDLED always 330 */ 331 static irqreturn_t cdns_i2c_slave_isr(void *ptr) 332 { 333 struct cdns_i2c *id = ptr; 334 unsigned int isr_status, i2c_status; 335 336 /* Fetch the interrupt status */ 337 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); 338 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET); 339 340 /* Ignore masked interrupts */ 341 isr_status &= ~cdns_i2c_readreg(CDNS_I2C_IMR_OFFSET); 342 343 /* Fetch transfer mode (send/receive) */ 344 i2c_status = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET); 345 346 /* Handle data send/receive */ 347 if (i2c_status & CDNS_I2C_SR_RXRW) { 348 /* Send data to master */ 349 if (isr_status & CDNS_I2C_IXR_DATA) 350 cdns_i2c_slave_send_data(id); 351 352 if (isr_status & CDNS_I2C_IXR_COMP) { 353 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE; 354 i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL); 355 } 356 } else { 357 /* Receive data from master */ 358 if (isr_status & CDNS_I2C_IXR_DATA) 359 cdns_i2c_slave_rcv_data(id); 360 361 if (isr_status & CDNS_I2C_IXR_COMP) { 362 cdns_i2c_slave_rcv_data(id); 363 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE; 364 i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL); 365 } 366 } 367 368 /* Master indicated xfer stop or fifo underflow/overflow */ 369 if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_RX_OVF | 370 CDNS_I2C_IXR_RX_UNF | CDNS_I2C_IXR_TX_OVF)) { 371 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE; 372 i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL); 373 cdns_i2c_writereg(CDNS_I2C_CR_CLR_FIFO, CDNS_I2C_CR_OFFSET); 374 } 375 376 return IRQ_HANDLED; 377 } 378 #endif 379 380 /** 381 * cdns_i2c_master_isr - Interrupt handler for the I2C device in master role 382 * @ptr: Pointer to I2C device private data 383 * 384 * This function handles the data interrupt, transfer complete interrupt and 385 * the error interrupts of the I2C device in master role. 386 * 387 * Return: IRQ_HANDLED always 388 */ 389 static irqreturn_t cdns_i2c_master_isr(void *ptr) 390 { 391 unsigned int isr_status, avail_bytes, updatetx; 392 unsigned int bytes_to_send; 393 bool hold_quirk; 394 struct cdns_i2c *id = ptr; 395 /* Signal completion only after everything is updated */ 396 int done_flag = 0; 397 irqreturn_t status = IRQ_NONE; 398 399 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); 400 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET); 401 id->err_status = 0; 402 403 /* Handling nack and arbitration lost interrupt */ 404 if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_ARB_LOST)) { 405 done_flag = 1; 406 status = IRQ_HANDLED; 407 } 408 409 /* 410 * Check if transfer size register needs to be updated again for a 411 * large data receive operation. 412 */ 413 updatetx = 0; 414 if (id->recv_count > id->curr_recv_count) 415 updatetx = 1; 416 417 hold_quirk = (id->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx; 418 419 /* When receiving, handle data interrupt and completion interrupt */ 420 if (id->p_recv_buf && 421 ((isr_status & CDNS_I2C_IXR_COMP) || 422 (isr_status & CDNS_I2C_IXR_DATA))) { 423 /* Read data if receive data valid is set */ 424 while (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) & 425 CDNS_I2C_SR_RXDV) { 426 if (id->recv_count > 0) { 427 *(id->p_recv_buf)++ = 428 cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET); 429 id->recv_count--; 430 id->curr_recv_count--; 431 432 /* 433 * Clear hold bit that was set for FIFO control 434 * if RX data left is less than or equal to 435 * FIFO DEPTH unless repeated start is selected 436 */ 437 if (id->recv_count <= CDNS_I2C_FIFO_DEPTH && 438 !id->bus_hold_flag) 439 cdns_i2c_clear_bus_hold(id); 440 441 } else { 442 dev_err(id->adap.dev.parent, 443 "xfer_size reg rollover. xfer aborted!\n"); 444 id->err_status |= CDNS_I2C_IXR_TO; 445 break; 446 } 447 448 if (cdns_is_holdquirk(id, hold_quirk)) 449 break; 450 } 451 452 /* 453 * The controller sends NACK to the slave when transfer size 454 * register reaches zero without considering the HOLD bit. 455 * This workaround is implemented for large data transfers to 456 * maintain transfer size non-zero while performing a large 457 * receive operation. 458 */ 459 if (cdns_is_holdquirk(id, hold_quirk)) { 460 /* wait while fifo is full */ 461 while (cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET) != 462 (id->curr_recv_count - CDNS_I2C_FIFO_DEPTH)) 463 ; 464 465 /* 466 * Check number of bytes to be received against maximum 467 * transfer size and update register accordingly. 468 */ 469 if (((int)(id->recv_count) - CDNS_I2C_FIFO_DEPTH) > 470 CDNS_I2C_TRANSFER_SIZE) { 471 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE, 472 CDNS_I2C_XFER_SIZE_OFFSET); 473 id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE + 474 CDNS_I2C_FIFO_DEPTH; 475 } else { 476 cdns_i2c_writereg(id->recv_count - 477 CDNS_I2C_FIFO_DEPTH, 478 CDNS_I2C_XFER_SIZE_OFFSET); 479 id->curr_recv_count = id->recv_count; 480 } 481 } else if (id->recv_count && !hold_quirk && 482 !id->curr_recv_count) { 483 484 /* Set the slave address in address register*/ 485 cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK, 486 CDNS_I2C_ADDR_OFFSET); 487 488 if (id->recv_count > CDNS_I2C_TRANSFER_SIZE) { 489 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE, 490 CDNS_I2C_XFER_SIZE_OFFSET); 491 id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE; 492 } else { 493 cdns_i2c_writereg(id->recv_count, 494 CDNS_I2C_XFER_SIZE_OFFSET); 495 id->curr_recv_count = id->recv_count; 496 } 497 } 498 499 /* Clear hold (if not repeated start) and signal completion */ 500 if ((isr_status & CDNS_I2C_IXR_COMP) && !id->recv_count) { 501 if (!id->bus_hold_flag) 502 cdns_i2c_clear_bus_hold(id); 503 done_flag = 1; 504 } 505 506 status = IRQ_HANDLED; 507 } 508 509 /* When sending, handle transfer complete interrupt */ 510 if ((isr_status & CDNS_I2C_IXR_COMP) && !id->p_recv_buf) { 511 /* 512 * If there is more data to be sent, calculate the 513 * space available in FIFO and fill with that many bytes. 514 */ 515 if (id->send_count) { 516 avail_bytes = CDNS_I2C_FIFO_DEPTH - 517 cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET); 518 if (id->send_count > avail_bytes) 519 bytes_to_send = avail_bytes; 520 else 521 bytes_to_send = id->send_count; 522 523 while (bytes_to_send--) { 524 cdns_i2c_writereg( 525 (*(id->p_send_buf)++), 526 CDNS_I2C_DATA_OFFSET); 527 id->send_count--; 528 } 529 } else { 530 /* 531 * Signal the completion of transaction and 532 * clear the hold bus bit if there are no 533 * further messages to be processed. 534 */ 535 done_flag = 1; 536 } 537 if (!id->send_count && !id->bus_hold_flag) 538 cdns_i2c_clear_bus_hold(id); 539 540 status = IRQ_HANDLED; 541 } 542 543 /* Update the status for errors */ 544 id->err_status |= isr_status & CDNS_I2C_IXR_ERR_INTR_MASK; 545 if (id->err_status) 546 status = IRQ_HANDLED; 547 548 if (done_flag) 549 complete(&id->xfer_done); 550 551 return status; 552 } 553 554 /** 555 * cdns_i2c_isr - Interrupt handler for the I2C device 556 * @irq: irq number for the I2C device 557 * @ptr: void pointer to cdns_i2c structure 558 * 559 * This function passes the control to slave/master based on current role of 560 * i2c controller. 561 * 562 * Return: IRQ_HANDLED always 563 */ 564 static irqreturn_t cdns_i2c_isr(int irq, void *ptr) 565 { 566 #if IS_ENABLED(CONFIG_I2C_SLAVE) 567 struct cdns_i2c *id = ptr; 568 569 if (id->dev_mode == CDNS_I2C_MODE_SLAVE) 570 return cdns_i2c_slave_isr(ptr); 571 #endif 572 return cdns_i2c_master_isr(ptr); 573 } 574 575 /** 576 * cdns_i2c_mrecv - Prepare and start a master receive operation 577 * @id: pointer to the i2c device structure 578 */ 579 static void cdns_i2c_mrecv(struct cdns_i2c *id) 580 { 581 unsigned int ctrl_reg; 582 unsigned int isr_status; 583 unsigned long flags; 584 bool hold_clear = false; 585 bool irq_save = false; 586 587 u32 addr; 588 589 id->p_recv_buf = id->p_msg->buf; 590 id->recv_count = id->p_msg->len; 591 592 /* Put the controller in master receive mode and clear the FIFO */ 593 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 594 ctrl_reg |= CDNS_I2C_CR_RW | CDNS_I2C_CR_CLR_FIFO; 595 596 if (id->p_msg->flags & I2C_M_RECV_LEN) 597 id->recv_count = I2C_SMBUS_BLOCK_MAX + 1; 598 599 id->curr_recv_count = id->recv_count; 600 601 /* 602 * Check for the message size against FIFO depth and set the 603 * 'hold bus' bit if it is greater than FIFO depth. 604 */ 605 if (id->recv_count > CDNS_I2C_FIFO_DEPTH) 606 ctrl_reg |= CDNS_I2C_CR_HOLD; 607 608 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET); 609 610 /* Clear the interrupts in interrupt status register */ 611 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); 612 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET); 613 614 /* 615 * The no. of bytes to receive is checked against the limit of 616 * max transfer size. Set transfer size register with no of bytes 617 * receive if it is less than transfer size and transfer size if 618 * it is more. Enable the interrupts. 619 */ 620 if (id->recv_count > CDNS_I2C_TRANSFER_SIZE) { 621 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE, 622 CDNS_I2C_XFER_SIZE_OFFSET); 623 id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE; 624 } else { 625 cdns_i2c_writereg(id->recv_count, CDNS_I2C_XFER_SIZE_OFFSET); 626 } 627 628 /* Determine hold_clear based on number of bytes to receive and hold flag */ 629 if (!id->bus_hold_flag && 630 ((id->p_msg->flags & I2C_M_RECV_LEN) != I2C_M_RECV_LEN) && 631 (id->recv_count <= CDNS_I2C_FIFO_DEPTH)) { 632 if (cdns_i2c_readreg(CDNS_I2C_CR_OFFSET) & CDNS_I2C_CR_HOLD) { 633 hold_clear = true; 634 if (id->quirks & CDNS_I2C_BROKEN_HOLD_BIT) 635 irq_save = true; 636 } 637 } 638 639 addr = id->p_msg->addr; 640 addr &= CDNS_I2C_ADDR_MASK; 641 642 if (hold_clear) { 643 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET) & ~CDNS_I2C_CR_HOLD; 644 /* 645 * In case of Xilinx Zynq SOC, clear the HOLD bit before transfer size 646 * register reaches '0'. This is an IP bug which causes transfer size 647 * register overflow to 0xFF. To satisfy this timing requirement, 648 * disable the interrupts on current processor core between register 649 * writes to slave address register and control register. 650 */ 651 if (irq_save) 652 local_irq_save(flags); 653 654 cdns_i2c_writereg(addr, CDNS_I2C_ADDR_OFFSET); 655 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET); 656 /* Read it back to avoid bufferring and make sure write happens */ 657 cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 658 659 if (irq_save) 660 local_irq_restore(flags); 661 } else { 662 cdns_i2c_writereg(addr, CDNS_I2C_ADDR_OFFSET); 663 } 664 665 cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET); 666 } 667 668 /** 669 * cdns_i2c_msend - Prepare and start a master send operation 670 * @id: pointer to the i2c device 671 */ 672 static void cdns_i2c_msend(struct cdns_i2c *id) 673 { 674 unsigned int avail_bytes; 675 unsigned int bytes_to_send; 676 unsigned int ctrl_reg; 677 unsigned int isr_status; 678 679 id->p_recv_buf = NULL; 680 id->p_send_buf = id->p_msg->buf; 681 id->send_count = id->p_msg->len; 682 683 /* Set the controller in Master transmit mode and clear the FIFO. */ 684 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 685 ctrl_reg &= ~CDNS_I2C_CR_RW; 686 ctrl_reg |= CDNS_I2C_CR_CLR_FIFO; 687 688 /* 689 * Check for the message size against FIFO depth and set the 690 * 'hold bus' bit if it is greater than FIFO depth. 691 */ 692 if (id->send_count > CDNS_I2C_FIFO_DEPTH) 693 ctrl_reg |= CDNS_I2C_CR_HOLD; 694 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET); 695 696 /* Clear the interrupts in interrupt status register. */ 697 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); 698 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET); 699 700 /* 701 * Calculate the space available in FIFO. Check the message length 702 * against the space available, and fill the FIFO accordingly. 703 * Enable the interrupts. 704 */ 705 avail_bytes = CDNS_I2C_FIFO_DEPTH - 706 cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET); 707 708 if (id->send_count > avail_bytes) 709 bytes_to_send = avail_bytes; 710 else 711 bytes_to_send = id->send_count; 712 713 while (bytes_to_send--) { 714 cdns_i2c_writereg((*(id->p_send_buf)++), CDNS_I2C_DATA_OFFSET); 715 id->send_count--; 716 } 717 718 /* 719 * Clear the bus hold flag if there is no more data 720 * and if it is the last message. 721 */ 722 if (!id->bus_hold_flag && !id->send_count) 723 cdns_i2c_clear_bus_hold(id); 724 /* Set the slave address in address register - triggers operation. */ 725 cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK, 726 CDNS_I2C_ADDR_OFFSET); 727 728 cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET); 729 } 730 731 /** 732 * cdns_i2c_master_reset - Reset the interface 733 * @adap: pointer to the i2c adapter driver instance 734 * 735 * This function cleanup the fifos, clear the hold bit and status 736 * and disable the interrupts. 737 */ 738 static void cdns_i2c_master_reset(struct i2c_adapter *adap) 739 { 740 struct cdns_i2c *id = adap->algo_data; 741 u32 regval; 742 743 /* Disable the interrupts */ 744 cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, CDNS_I2C_IDR_OFFSET); 745 /* Clear the hold bit and fifos */ 746 regval = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 747 regval &= ~CDNS_I2C_CR_HOLD; 748 regval |= CDNS_I2C_CR_CLR_FIFO; 749 cdns_i2c_writereg(regval, CDNS_I2C_CR_OFFSET); 750 /* Update the transfercount register to zero */ 751 cdns_i2c_writereg(0, CDNS_I2C_XFER_SIZE_OFFSET); 752 /* Clear the interrupt status register */ 753 regval = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); 754 cdns_i2c_writereg(regval, CDNS_I2C_ISR_OFFSET); 755 /* Clear the status register */ 756 regval = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET); 757 cdns_i2c_writereg(regval, CDNS_I2C_SR_OFFSET); 758 } 759 760 static int cdns_i2c_process_msg(struct cdns_i2c *id, struct i2c_msg *msg, 761 struct i2c_adapter *adap) 762 { 763 unsigned long time_left; 764 u32 reg; 765 766 id->p_msg = msg; 767 id->err_status = 0; 768 reinit_completion(&id->xfer_done); 769 770 /* Check for the TEN Bit mode on each msg */ 771 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 772 if (msg->flags & I2C_M_TEN) { 773 if (reg & CDNS_I2C_CR_NEA) 774 cdns_i2c_writereg(reg & ~CDNS_I2C_CR_NEA, 775 CDNS_I2C_CR_OFFSET); 776 } else { 777 if (!(reg & CDNS_I2C_CR_NEA)) 778 cdns_i2c_writereg(reg | CDNS_I2C_CR_NEA, 779 CDNS_I2C_CR_OFFSET); 780 } 781 782 /* Check for the R/W flag on each msg */ 783 if (msg->flags & I2C_M_RD) 784 cdns_i2c_mrecv(id); 785 else 786 cdns_i2c_msend(id); 787 788 /* Wait for the signal of completion */ 789 time_left = wait_for_completion_timeout(&id->xfer_done, adap->timeout); 790 if (time_left == 0) { 791 cdns_i2c_master_reset(adap); 792 dev_err(id->adap.dev.parent, 793 "timeout waiting on completion\n"); 794 return -ETIMEDOUT; 795 } 796 797 cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, 798 CDNS_I2C_IDR_OFFSET); 799 800 /* If it is bus arbitration error, try again */ 801 if (id->err_status & CDNS_I2C_IXR_ARB_LOST) 802 return -EAGAIN; 803 804 return 0; 805 } 806 807 /** 808 * cdns_i2c_master_xfer - The main i2c transfer function 809 * @adap: pointer to the i2c adapter driver instance 810 * @msgs: pointer to the i2c message structure 811 * @num: the number of messages to transfer 812 * 813 * Initiates the send/recv activity based on the transfer message received. 814 * 815 * Return: number of msgs processed on success, negative error otherwise 816 */ 817 static int cdns_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, 818 int num) 819 { 820 int ret, count; 821 u32 reg; 822 struct cdns_i2c *id = adap->algo_data; 823 bool hold_quirk; 824 #if IS_ENABLED(CONFIG_I2C_SLAVE) 825 bool change_role = false; 826 #endif 827 828 ret = pm_runtime_resume_and_get(id->dev); 829 if (ret < 0) 830 return ret; 831 832 #if IS_ENABLED(CONFIG_I2C_SLAVE) 833 /* Check i2c operating mode and switch if possible */ 834 if (id->dev_mode == CDNS_I2C_MODE_SLAVE) { 835 if (id->slave_state != CDNS_I2C_SLAVE_STATE_IDLE) 836 return -EAGAIN; 837 838 /* Set mode to master */ 839 cdns_i2c_set_mode(CDNS_I2C_MODE_MASTER, id); 840 841 /* Mark flag to change role once xfer is completed */ 842 change_role = true; 843 } 844 #endif 845 846 /* Check if the bus is free */ 847 if (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) & CDNS_I2C_SR_BA) { 848 ret = -EAGAIN; 849 goto out; 850 } 851 852 hold_quirk = !!(id->quirks & CDNS_I2C_BROKEN_HOLD_BIT); 853 /* 854 * Set the flag to one when multiple messages are to be 855 * processed with a repeated start. 856 */ 857 if (num > 1) { 858 /* 859 * This controller does not give completion interrupt after a 860 * master receive message if HOLD bit is set (repeated start), 861 * resulting in SW timeout. Hence, if a receive message is 862 * followed by any other message, an error is returned 863 * indicating that this sequence is not supported. 864 */ 865 for (count = 0; (count < num - 1 && hold_quirk); count++) { 866 if (msgs[count].flags & I2C_M_RD) { 867 dev_warn(adap->dev.parent, 868 "Can't do repeated start after a receive message\n"); 869 ret = -EOPNOTSUPP; 870 goto out; 871 } 872 } 873 id->bus_hold_flag = 1; 874 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 875 reg |= CDNS_I2C_CR_HOLD; 876 cdns_i2c_writereg(reg, CDNS_I2C_CR_OFFSET); 877 } else { 878 id->bus_hold_flag = 0; 879 } 880 881 /* Process the msg one by one */ 882 for (count = 0; count < num; count++, msgs++) { 883 if (count == (num - 1)) 884 id->bus_hold_flag = 0; 885 886 ret = cdns_i2c_process_msg(id, msgs, adap); 887 if (ret) 888 goto out; 889 890 /* Report the other error interrupts to application */ 891 if (id->err_status) { 892 cdns_i2c_master_reset(adap); 893 894 if (id->err_status & CDNS_I2C_IXR_NACK) { 895 ret = -ENXIO; 896 goto out; 897 } 898 ret = -EIO; 899 goto out; 900 } 901 } 902 903 ret = num; 904 905 out: 906 907 #if IS_ENABLED(CONFIG_I2C_SLAVE) 908 /* Switch i2c mode to slave */ 909 if (change_role) 910 cdns_i2c_set_mode(CDNS_I2C_MODE_SLAVE, id); 911 #endif 912 913 pm_runtime_mark_last_busy(id->dev); 914 pm_runtime_put_autosuspend(id->dev); 915 return ret; 916 } 917 918 /** 919 * cdns_i2c_func - Returns the supported features of the I2C driver 920 * @adap: pointer to the i2c adapter structure 921 * 922 * Return: 32 bit value, each bit corresponding to a feature 923 */ 924 static u32 cdns_i2c_func(struct i2c_adapter *adap) 925 { 926 u32 func = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | 927 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) | 928 I2C_FUNC_SMBUS_BLOCK_DATA; 929 930 #if IS_ENABLED(CONFIG_I2C_SLAVE) 931 func |= I2C_FUNC_SLAVE; 932 #endif 933 934 return func; 935 } 936 937 #if IS_ENABLED(CONFIG_I2C_SLAVE) 938 static int cdns_reg_slave(struct i2c_client *slave) 939 { 940 int ret; 941 struct cdns_i2c *id = container_of(slave->adapter, struct cdns_i2c, 942 adap); 943 944 if (id->slave) 945 return -EBUSY; 946 947 if (slave->flags & I2C_CLIENT_TEN) 948 return -EAFNOSUPPORT; 949 950 ret = pm_runtime_resume_and_get(id->dev); 951 if (ret < 0) 952 return ret; 953 954 /* Store slave information */ 955 id->slave = slave; 956 957 /* Enable I2C slave */ 958 cdns_i2c_set_mode(CDNS_I2C_MODE_SLAVE, id); 959 960 return 0; 961 } 962 963 static int cdns_unreg_slave(struct i2c_client *slave) 964 { 965 struct cdns_i2c *id = container_of(slave->adapter, struct cdns_i2c, 966 adap); 967 968 pm_runtime_put(id->dev); 969 970 /* Remove slave information */ 971 id->slave = NULL; 972 973 /* Enable I2C master */ 974 cdns_i2c_set_mode(CDNS_I2C_MODE_MASTER, id); 975 976 return 0; 977 } 978 #endif 979 980 static const struct i2c_algorithm cdns_i2c_algo = { 981 .master_xfer = cdns_i2c_master_xfer, 982 .functionality = cdns_i2c_func, 983 #if IS_ENABLED(CONFIG_I2C_SLAVE) 984 .reg_slave = cdns_reg_slave, 985 .unreg_slave = cdns_unreg_slave, 986 #endif 987 }; 988 989 /** 990 * cdns_i2c_calc_divs - Calculate clock dividers 991 * @f: I2C clock frequency 992 * @input_clk: Input clock frequency 993 * @a: First divider (return value) 994 * @b: Second divider (return value) 995 * 996 * f is used as input and output variable. As input it is used as target I2C 997 * frequency. On function exit f holds the actually resulting I2C frequency. 998 * 999 * Return: 0 on success, negative errno otherwise. 1000 */ 1001 static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk, 1002 unsigned int *a, unsigned int *b) 1003 { 1004 unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp; 1005 unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0; 1006 unsigned int last_error, current_error; 1007 1008 /* calculate (divisor_a+1) x (divisor_b+1) */ 1009 temp = input_clk / (22 * fscl); 1010 1011 /* 1012 * If the calculated value is negative or 0, the fscl input is out of 1013 * range. Return error. 1014 */ 1015 if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX))) 1016 return -EINVAL; 1017 1018 last_error = -1; 1019 for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) { 1020 div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1)); 1021 1022 if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX)) 1023 continue; 1024 div_b--; 1025 1026 actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1)); 1027 1028 if (actual_fscl > fscl) 1029 continue; 1030 1031 current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) : 1032 (fscl - actual_fscl)); 1033 1034 if (last_error > current_error) { 1035 calc_div_a = div_a; 1036 calc_div_b = div_b; 1037 best_fscl = actual_fscl; 1038 last_error = current_error; 1039 } 1040 } 1041 1042 *a = calc_div_a; 1043 *b = calc_div_b; 1044 *f = best_fscl; 1045 1046 return 0; 1047 } 1048 1049 /** 1050 * cdns_i2c_setclk - This function sets the serial clock rate for the I2C device 1051 * @clk_in: I2C clock input frequency in Hz 1052 * @id: Pointer to the I2C device structure 1053 * 1054 * The device must be idle rather than busy transferring data before setting 1055 * these device options. 1056 * The data rate is set by values in the control register. 1057 * The formula for determining the correct register values is 1058 * Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1)) 1059 * See the hardware data sheet for a full explanation of setting the serial 1060 * clock rate. The clock can not be faster than the input clock divide by 22. 1061 * The two most common clock rates are 100KHz and 400KHz. 1062 * 1063 * Return: 0 on success, negative error otherwise 1064 */ 1065 static int cdns_i2c_setclk(unsigned long clk_in, struct cdns_i2c *id) 1066 { 1067 unsigned int div_a, div_b; 1068 unsigned int ctrl_reg; 1069 int ret = 0; 1070 unsigned long fscl = id->i2c_clk; 1071 1072 ret = cdns_i2c_calc_divs(&fscl, clk_in, &div_a, &div_b); 1073 if (ret) 1074 return ret; 1075 1076 ctrl_reg = id->ctrl_reg; 1077 ctrl_reg &= ~(CDNS_I2C_CR_DIVA_MASK | CDNS_I2C_CR_DIVB_MASK); 1078 ctrl_reg |= ((div_a << CDNS_I2C_CR_DIVA_SHIFT) | 1079 (div_b << CDNS_I2C_CR_DIVB_SHIFT)); 1080 id->ctrl_reg = ctrl_reg; 1081 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET); 1082 #if IS_ENABLED(CONFIG_I2C_SLAVE) 1083 id->ctrl_reg_diva_divb = ctrl_reg & (CDNS_I2C_CR_DIVA_MASK | 1084 CDNS_I2C_CR_DIVB_MASK); 1085 #endif 1086 return 0; 1087 } 1088 1089 /** 1090 * cdns_i2c_clk_notifier_cb - Clock rate change callback 1091 * @nb: Pointer to notifier block 1092 * @event: Notification reason 1093 * @data: Pointer to notification data object 1094 * 1095 * This function is called when the cdns_i2c input clock frequency changes. 1096 * The callback checks whether a valid bus frequency can be generated after the 1097 * change. If so, the change is acknowledged, otherwise the change is aborted. 1098 * New dividers are written to the HW in the pre- or post change notification 1099 * depending on the scaling direction. 1100 * 1101 * Return: NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK 1102 * to acknowledge the change, NOTIFY_DONE if the notification is 1103 * considered irrelevant. 1104 */ 1105 static int cdns_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long 1106 event, void *data) 1107 { 1108 struct clk_notifier_data *ndata = data; 1109 struct cdns_i2c *id = to_cdns_i2c(nb); 1110 1111 if (pm_runtime_suspended(id->dev)) 1112 return NOTIFY_OK; 1113 1114 switch (event) { 1115 case PRE_RATE_CHANGE: 1116 { 1117 unsigned long input_clk = ndata->new_rate; 1118 unsigned long fscl = id->i2c_clk; 1119 unsigned int div_a, div_b; 1120 int ret; 1121 1122 ret = cdns_i2c_calc_divs(&fscl, input_clk, &div_a, &div_b); 1123 if (ret) { 1124 dev_warn(id->adap.dev.parent, 1125 "clock rate change rejected\n"); 1126 return NOTIFY_STOP; 1127 } 1128 1129 /* scale up */ 1130 if (ndata->new_rate > ndata->old_rate) 1131 cdns_i2c_setclk(ndata->new_rate, id); 1132 1133 return NOTIFY_OK; 1134 } 1135 case POST_RATE_CHANGE: 1136 id->input_clk = ndata->new_rate; 1137 /* scale down */ 1138 if (ndata->new_rate < ndata->old_rate) 1139 cdns_i2c_setclk(ndata->new_rate, id); 1140 return NOTIFY_OK; 1141 case ABORT_RATE_CHANGE: 1142 /* scale up */ 1143 if (ndata->new_rate > ndata->old_rate) 1144 cdns_i2c_setclk(ndata->old_rate, id); 1145 return NOTIFY_OK; 1146 default: 1147 return NOTIFY_DONE; 1148 } 1149 } 1150 1151 /** 1152 * cdns_i2c_runtime_suspend - Runtime suspend method for the driver 1153 * @dev: Address of the platform_device structure 1154 * 1155 * Put the driver into low power mode. 1156 * 1157 * Return: 0 always 1158 */ 1159 static int __maybe_unused cdns_i2c_runtime_suspend(struct device *dev) 1160 { 1161 struct cdns_i2c *xi2c = dev_get_drvdata(dev); 1162 1163 clk_disable(xi2c->clk); 1164 1165 return 0; 1166 } 1167 1168 /** 1169 * cdns_i2c_init - Controller initialisation 1170 * @id: Device private data structure 1171 * 1172 * Initialise the i2c controller. 1173 * 1174 */ 1175 static void cdns_i2c_init(struct cdns_i2c *id) 1176 { 1177 cdns_i2c_writereg(id->ctrl_reg, CDNS_I2C_CR_OFFSET); 1178 /* 1179 * Cadence I2C controller has a bug wherein it generates 1180 * invalid read transaction after HW timeout in master receiver mode. 1181 * HW timeout is not used by this driver and the interrupt is disabled. 1182 * But the feature itself cannot be disabled. Hence maximum value 1183 * is written to this register to reduce the chances of error. 1184 */ 1185 cdns_i2c_writereg(CDNS_I2C_TIMEOUT_MAX, CDNS_I2C_TIME_OUT_OFFSET); 1186 } 1187 1188 /** 1189 * cdns_i2c_runtime_resume - Runtime resume 1190 * @dev: Address of the platform_device structure 1191 * 1192 * Runtime resume callback. 1193 * 1194 * Return: 0 on success and error value on error 1195 */ 1196 static int __maybe_unused cdns_i2c_runtime_resume(struct device *dev) 1197 { 1198 struct cdns_i2c *xi2c = dev_get_drvdata(dev); 1199 int ret; 1200 1201 ret = clk_enable(xi2c->clk); 1202 if (ret) { 1203 dev_err(dev, "Cannot enable clock.\n"); 1204 return ret; 1205 } 1206 cdns_i2c_init(xi2c); 1207 1208 return 0; 1209 } 1210 1211 static const struct dev_pm_ops cdns_i2c_dev_pm_ops = { 1212 SET_RUNTIME_PM_OPS(cdns_i2c_runtime_suspend, 1213 cdns_i2c_runtime_resume, NULL) 1214 }; 1215 1216 static const struct cdns_platform_data r1p10_i2c_def = { 1217 .quirks = CDNS_I2C_BROKEN_HOLD_BIT, 1218 }; 1219 1220 static const struct of_device_id cdns_i2c_of_match[] = { 1221 { .compatible = "cdns,i2c-r1p10", .data = &r1p10_i2c_def }, 1222 { .compatible = "cdns,i2c-r1p14",}, 1223 { /* end of table */ } 1224 }; 1225 MODULE_DEVICE_TABLE(of, cdns_i2c_of_match); 1226 1227 /** 1228 * cdns_i2c_probe - Platform registration call 1229 * @pdev: Handle to the platform device structure 1230 * 1231 * This function does all the memory allocation and registration for the i2c 1232 * device. User can modify the address mode to 10 bit address mode using the 1233 * ioctl call with option I2C_TENBIT. 1234 * 1235 * Return: 0 on success, negative error otherwise 1236 */ 1237 static int cdns_i2c_probe(struct platform_device *pdev) 1238 { 1239 struct resource *r_mem; 1240 struct cdns_i2c *id; 1241 int ret; 1242 const struct of_device_id *match; 1243 1244 id = devm_kzalloc(&pdev->dev, sizeof(*id), GFP_KERNEL); 1245 if (!id) 1246 return -ENOMEM; 1247 1248 id->dev = &pdev->dev; 1249 platform_set_drvdata(pdev, id); 1250 1251 match = of_match_node(cdns_i2c_of_match, pdev->dev.of_node); 1252 if (match && match->data) { 1253 const struct cdns_platform_data *data = match->data; 1254 id->quirks = data->quirks; 1255 } 1256 1257 id->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &r_mem); 1258 if (IS_ERR(id->membase)) 1259 return PTR_ERR(id->membase); 1260 1261 ret = platform_get_irq(pdev, 0); 1262 if (ret < 0) 1263 return ret; 1264 id->irq = ret; 1265 1266 id->adap.owner = THIS_MODULE; 1267 id->adap.dev.of_node = pdev->dev.of_node; 1268 id->adap.algo = &cdns_i2c_algo; 1269 id->adap.timeout = CDNS_I2C_TIMEOUT; 1270 id->adap.retries = 3; /* Default retry value. */ 1271 id->adap.algo_data = id; 1272 id->adap.dev.parent = &pdev->dev; 1273 init_completion(&id->xfer_done); 1274 snprintf(id->adap.name, sizeof(id->adap.name), 1275 "Cadence I2C at %08lx", (unsigned long)r_mem->start); 1276 1277 id->clk = devm_clk_get(&pdev->dev, NULL); 1278 if (IS_ERR(id->clk)) 1279 return dev_err_probe(&pdev->dev, PTR_ERR(id->clk), 1280 "input clock not found.\n"); 1281 1282 ret = clk_prepare_enable(id->clk); 1283 if (ret) 1284 dev_err(&pdev->dev, "Unable to enable clock.\n"); 1285 1286 pm_runtime_set_autosuspend_delay(id->dev, CNDS_I2C_PM_TIMEOUT); 1287 pm_runtime_use_autosuspend(id->dev); 1288 pm_runtime_set_active(id->dev); 1289 pm_runtime_enable(id->dev); 1290 1291 id->clk_rate_change_nb.notifier_call = cdns_i2c_clk_notifier_cb; 1292 if (clk_notifier_register(id->clk, &id->clk_rate_change_nb)) 1293 dev_warn(&pdev->dev, "Unable to register clock notifier.\n"); 1294 id->input_clk = clk_get_rate(id->clk); 1295 1296 ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency", 1297 &id->i2c_clk); 1298 if (ret || (id->i2c_clk > I2C_MAX_FAST_MODE_FREQ)) 1299 id->i2c_clk = I2C_MAX_STANDARD_MODE_FREQ; 1300 1301 #if IS_ENABLED(CONFIG_I2C_SLAVE) 1302 /* Set initial mode to master */ 1303 id->dev_mode = CDNS_I2C_MODE_MASTER; 1304 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE; 1305 #endif 1306 id->ctrl_reg = CDNS_I2C_CR_ACK_EN | CDNS_I2C_CR_NEA | CDNS_I2C_CR_MS; 1307 1308 ret = cdns_i2c_setclk(id->input_clk, id); 1309 if (ret) { 1310 dev_err(&pdev->dev, "invalid SCL clock: %u Hz\n", id->i2c_clk); 1311 ret = -EINVAL; 1312 goto err_clk_dis; 1313 } 1314 1315 ret = devm_request_irq(&pdev->dev, id->irq, cdns_i2c_isr, 0, 1316 DRIVER_NAME, id); 1317 if (ret) { 1318 dev_err(&pdev->dev, "cannot get irq %d\n", id->irq); 1319 goto err_clk_dis; 1320 } 1321 cdns_i2c_init(id); 1322 1323 ret = i2c_add_adapter(&id->adap); 1324 if (ret < 0) 1325 goto err_clk_dis; 1326 1327 dev_info(&pdev->dev, "%u kHz mmio %08lx irq %d\n", 1328 id->i2c_clk / 1000, (unsigned long)r_mem->start, id->irq); 1329 1330 return 0; 1331 1332 err_clk_dis: 1333 clk_disable_unprepare(id->clk); 1334 pm_runtime_disable(&pdev->dev); 1335 pm_runtime_set_suspended(&pdev->dev); 1336 return ret; 1337 } 1338 1339 /** 1340 * cdns_i2c_remove - Unregister the device after releasing the resources 1341 * @pdev: Handle to the platform device structure 1342 * 1343 * This function frees all the resources allocated to the device. 1344 * 1345 * Return: 0 always 1346 */ 1347 static int cdns_i2c_remove(struct platform_device *pdev) 1348 { 1349 struct cdns_i2c *id = platform_get_drvdata(pdev); 1350 1351 pm_runtime_disable(&pdev->dev); 1352 pm_runtime_set_suspended(&pdev->dev); 1353 pm_runtime_dont_use_autosuspend(&pdev->dev); 1354 1355 i2c_del_adapter(&id->adap); 1356 clk_notifier_unregister(id->clk, &id->clk_rate_change_nb); 1357 clk_disable_unprepare(id->clk); 1358 1359 return 0; 1360 } 1361 1362 static struct platform_driver cdns_i2c_drv = { 1363 .driver = { 1364 .name = DRIVER_NAME, 1365 .of_match_table = cdns_i2c_of_match, 1366 .pm = &cdns_i2c_dev_pm_ops, 1367 }, 1368 .probe = cdns_i2c_probe, 1369 .remove = cdns_i2c_remove, 1370 }; 1371 1372 module_platform_driver(cdns_i2c_drv); 1373 1374 MODULE_AUTHOR("Xilinx Inc."); 1375 MODULE_DESCRIPTION("Cadence I2C bus driver"); 1376 MODULE_LICENSE("GPL"); 1377