xref: /openbmc/linux/drivers/i2c/busses/i2c-cadence.c (revision c819e2cf)
1 /*
2  * I2C bus driver for the Cadence I2C controller.
3  *
4  * Copyright (C) 2009 - 2014 Xilinx, Inc.
5  *
6  * This program is free software; you can redistribute it
7  * and/or modify it under the terms of the GNU General Public
8  * License as published by the Free Software Foundation;
9  * either version 2 of the License, or (at your option) any
10  * later version.
11  */
12 
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/i2c.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/module.h>
19 #include <linux/platform_device.h>
20 
21 /* Register offsets for the I2C device. */
22 #define CDNS_I2C_CR_OFFSET		0x00 /* Control Register, RW */
23 #define CDNS_I2C_SR_OFFSET		0x04 /* Status Register, RO */
24 #define CDNS_I2C_ADDR_OFFSET		0x08 /* I2C Address Register, RW */
25 #define CDNS_I2C_DATA_OFFSET		0x0C /* I2C Data Register, RW */
26 #define CDNS_I2C_ISR_OFFSET		0x10 /* IRQ Status Register, RW */
27 #define CDNS_I2C_XFER_SIZE_OFFSET	0x14 /* Transfer Size Register, RW */
28 #define CDNS_I2C_TIME_OUT_OFFSET	0x1C /* Time Out Register, RW */
29 #define CDNS_I2C_IER_OFFSET		0x24 /* IRQ Enable Register, WO */
30 #define CDNS_I2C_IDR_OFFSET		0x28 /* IRQ Disable Register, WO */
31 
32 /* Control Register Bit mask definitions */
33 #define CDNS_I2C_CR_HOLD		BIT(4) /* Hold Bus bit */
34 #define CDNS_I2C_CR_ACK_EN		BIT(3)
35 #define CDNS_I2C_CR_NEA			BIT(2)
36 #define CDNS_I2C_CR_MS			BIT(1)
37 /* Read or Write Master transfer 0 = Transmitter, 1 = Receiver */
38 #define CDNS_I2C_CR_RW			BIT(0)
39 /* 1 = Auto init FIFO to zeroes */
40 #define CDNS_I2C_CR_CLR_FIFO		BIT(6)
41 #define CDNS_I2C_CR_DIVA_SHIFT		14
42 #define CDNS_I2C_CR_DIVA_MASK		(3 << CDNS_I2C_CR_DIVA_SHIFT)
43 #define CDNS_I2C_CR_DIVB_SHIFT		8
44 #define CDNS_I2C_CR_DIVB_MASK		(0x3f << CDNS_I2C_CR_DIVB_SHIFT)
45 
46 /* Status Register Bit mask definitions */
47 #define CDNS_I2C_SR_BA		BIT(8)
48 #define CDNS_I2C_SR_RXDV	BIT(5)
49 
50 /*
51  * I2C Address Register Bit mask definitions
52  * Normal addressing mode uses [6:0] bits. Extended addressing mode uses [9:0]
53  * bits. A write access to this register always initiates a transfer if the I2C
54  * is in master mode.
55  */
56 #define CDNS_I2C_ADDR_MASK	0x000003FF /* I2C Address Mask */
57 
58 /*
59  * I2C Interrupt Registers Bit mask definitions
60  * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
61  * bit definitions.
62  */
63 #define CDNS_I2C_IXR_ARB_LOST		BIT(9)
64 #define CDNS_I2C_IXR_RX_UNF		BIT(7)
65 #define CDNS_I2C_IXR_TX_OVF		BIT(6)
66 #define CDNS_I2C_IXR_RX_OVF		BIT(5)
67 #define CDNS_I2C_IXR_SLV_RDY		BIT(4)
68 #define CDNS_I2C_IXR_TO			BIT(3)
69 #define CDNS_I2C_IXR_NACK		BIT(2)
70 #define CDNS_I2C_IXR_DATA		BIT(1)
71 #define CDNS_I2C_IXR_COMP		BIT(0)
72 
73 #define CDNS_I2C_IXR_ALL_INTR_MASK	(CDNS_I2C_IXR_ARB_LOST | \
74 					 CDNS_I2C_IXR_RX_UNF | \
75 					 CDNS_I2C_IXR_TX_OVF | \
76 					 CDNS_I2C_IXR_RX_OVF | \
77 					 CDNS_I2C_IXR_SLV_RDY | \
78 					 CDNS_I2C_IXR_TO | \
79 					 CDNS_I2C_IXR_NACK | \
80 					 CDNS_I2C_IXR_DATA | \
81 					 CDNS_I2C_IXR_COMP)
82 
83 #define CDNS_I2C_IXR_ERR_INTR_MASK	(CDNS_I2C_IXR_ARB_LOST | \
84 					 CDNS_I2C_IXR_RX_UNF | \
85 					 CDNS_I2C_IXR_TX_OVF | \
86 					 CDNS_I2C_IXR_RX_OVF | \
87 					 CDNS_I2C_IXR_NACK)
88 
89 #define CDNS_I2C_ENABLED_INTR_MASK	(CDNS_I2C_IXR_ARB_LOST | \
90 					 CDNS_I2C_IXR_RX_UNF | \
91 					 CDNS_I2C_IXR_TX_OVF | \
92 					 CDNS_I2C_IXR_RX_OVF | \
93 					 CDNS_I2C_IXR_NACK | \
94 					 CDNS_I2C_IXR_DATA | \
95 					 CDNS_I2C_IXR_COMP)
96 
97 #define CDNS_I2C_TIMEOUT		msecs_to_jiffies(1000)
98 
99 #define CDNS_I2C_FIFO_DEPTH		16
100 /* FIFO depth at which the DATA interrupt occurs */
101 #define CDNS_I2C_DATA_INTR_DEPTH	(CDNS_I2C_FIFO_DEPTH - 2)
102 #define CDNS_I2C_MAX_TRANSFER_SIZE	255
103 /* Transfer size in multiples of data interrupt depth */
104 #define CDNS_I2C_TRANSFER_SIZE	(CDNS_I2C_MAX_TRANSFER_SIZE - 3)
105 
106 #define DRIVER_NAME		"cdns-i2c"
107 
108 #define CDNS_I2C_SPEED_MAX	400000
109 #define CDNS_I2C_SPEED_DEFAULT	100000
110 
111 #define CDNS_I2C_DIVA_MAX	4
112 #define CDNS_I2C_DIVB_MAX	64
113 
114 #define CDNS_I2C_TIMEOUT_MAX	0xFF
115 
116 #define cdns_i2c_readreg(offset)       readl_relaxed(id->membase + offset)
117 #define cdns_i2c_writereg(val, offset) writel_relaxed(val, id->membase + offset)
118 
119 /**
120  * struct cdns_i2c - I2C device private data structure
121  * @membase:		Base address of the I2C device
122  * @adap:		I2C adapter instance
123  * @p_msg:		Message pointer
124  * @err_status:		Error status in Interrupt Status Register
125  * @xfer_done:		Transfer complete status
126  * @p_send_buf:		Pointer to transmit buffer
127  * @p_recv_buf:		Pointer to receive buffer
128  * @suspended:		Flag holding the device's PM status
129  * @send_count:		Number of bytes still expected to send
130  * @recv_count:		Number of bytes still expected to receive
131  * @irq:		IRQ number
132  * @input_clk:		Input clock to I2C controller
133  * @i2c_clk:		Maximum I2C clock speed
134  * @bus_hold_flag:	Flag used in repeated start for clearing HOLD bit
135  * @clk:		Pointer to struct clk
136  * @clk_rate_change_nb:	Notifier block for clock rate changes
137  */
138 struct cdns_i2c {
139 	void __iomem *membase;
140 	struct i2c_adapter adap;
141 	struct i2c_msg *p_msg;
142 	int err_status;
143 	struct completion xfer_done;
144 	unsigned char *p_send_buf;
145 	unsigned char *p_recv_buf;
146 	u8 suspended;
147 	unsigned int send_count;
148 	unsigned int recv_count;
149 	int irq;
150 	unsigned long input_clk;
151 	unsigned int i2c_clk;
152 	unsigned int bus_hold_flag;
153 	struct clk *clk;
154 	struct notifier_block clk_rate_change_nb;
155 };
156 
157 #define to_cdns_i2c(_nb)	container_of(_nb, struct cdns_i2c, \
158 					     clk_rate_change_nb)
159 
160 /**
161  * cdns_i2c_clear_bus_hold() - Clear bus hold bit
162  * @id:	Pointer to driver data struct
163  *
164  * Helper to clear the controller's bus hold bit.
165  */
166 static void cdns_i2c_clear_bus_hold(struct cdns_i2c *id)
167 {
168 	u32 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
169 	if (reg & CDNS_I2C_CR_HOLD)
170 		cdns_i2c_writereg(reg & ~CDNS_I2C_CR_HOLD, CDNS_I2C_CR_OFFSET);
171 }
172 
173 /**
174  * cdns_i2c_isr - Interrupt handler for the I2C device
175  * @irq:	irq number for the I2C device
176  * @ptr:	void pointer to cdns_i2c structure
177  *
178  * This function handles the data interrupt, transfer complete interrupt and
179  * the error interrupts of the I2C device.
180  *
181  * Return: IRQ_HANDLED always
182  */
183 static irqreturn_t cdns_i2c_isr(int irq, void *ptr)
184 {
185 	unsigned int isr_status, avail_bytes;
186 	unsigned int bytes_to_recv, bytes_to_send;
187 	struct cdns_i2c *id = ptr;
188 	/* Signal completion only after everything is updated */
189 	int done_flag = 0;
190 	irqreturn_t status = IRQ_NONE;
191 
192 	isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
193 
194 	/* Handling nack and arbitration lost interrupt */
195 	if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_ARB_LOST)) {
196 		done_flag = 1;
197 		status = IRQ_HANDLED;
198 	}
199 
200 	/* Handling Data interrupt */
201 	if ((isr_status & CDNS_I2C_IXR_DATA) &&
202 			(id->recv_count >= CDNS_I2C_DATA_INTR_DEPTH)) {
203 		/* Always read data interrupt threshold bytes */
204 		bytes_to_recv = CDNS_I2C_DATA_INTR_DEPTH;
205 		id->recv_count -= CDNS_I2C_DATA_INTR_DEPTH;
206 		avail_bytes = cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
207 
208 		/*
209 		 * if the tranfer size register value is zero, then
210 		 * check for the remaining bytes and update the
211 		 * transfer size register.
212 		 */
213 		if (!avail_bytes) {
214 			if (id->recv_count > CDNS_I2C_TRANSFER_SIZE)
215 				cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE,
216 						CDNS_I2C_XFER_SIZE_OFFSET);
217 			else
218 				cdns_i2c_writereg(id->recv_count,
219 						CDNS_I2C_XFER_SIZE_OFFSET);
220 		}
221 
222 		/* Process the data received */
223 		while (bytes_to_recv--)
224 			*(id->p_recv_buf)++ =
225 				cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET);
226 
227 		if (!id->bus_hold_flag &&
228 				(id->recv_count <= CDNS_I2C_FIFO_DEPTH))
229 			cdns_i2c_clear_bus_hold(id);
230 
231 		status = IRQ_HANDLED;
232 	}
233 
234 	/* Handling Transfer Complete interrupt */
235 	if (isr_status & CDNS_I2C_IXR_COMP) {
236 		if (!id->p_recv_buf) {
237 			/*
238 			 * If the device is sending data If there is further
239 			 * data to be sent. Calculate the available space
240 			 * in FIFO and fill the FIFO with that many bytes.
241 			 */
242 			if (id->send_count) {
243 				avail_bytes = CDNS_I2C_FIFO_DEPTH -
244 				    cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
245 				if (id->send_count > avail_bytes)
246 					bytes_to_send = avail_bytes;
247 				else
248 					bytes_to_send = id->send_count;
249 
250 				while (bytes_to_send--) {
251 					cdns_i2c_writereg(
252 						(*(id->p_send_buf)++),
253 						 CDNS_I2C_DATA_OFFSET);
254 					id->send_count--;
255 				}
256 			} else {
257 				/*
258 				 * Signal the completion of transaction and
259 				 * clear the hold bus bit if there are no
260 				 * further messages to be processed.
261 				 */
262 				done_flag = 1;
263 			}
264 			if (!id->send_count && !id->bus_hold_flag)
265 				cdns_i2c_clear_bus_hold(id);
266 		} else {
267 			if (!id->bus_hold_flag)
268 				cdns_i2c_clear_bus_hold(id);
269 			/*
270 			 * If the device is receiving data, then signal
271 			 * the completion of transaction and read the data
272 			 * present in the FIFO. Signal the completion of
273 			 * transaction.
274 			 */
275 			while (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) &
276 					CDNS_I2C_SR_RXDV) {
277 				*(id->p_recv_buf)++ =
278 					cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET);
279 				id->recv_count--;
280 			}
281 			done_flag = 1;
282 		}
283 
284 		status = IRQ_HANDLED;
285 	}
286 
287 	/* Update the status for errors */
288 	id->err_status = isr_status & CDNS_I2C_IXR_ERR_INTR_MASK;
289 	if (id->err_status)
290 		status = IRQ_HANDLED;
291 
292 	cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
293 
294 	if (done_flag)
295 		complete(&id->xfer_done);
296 
297 	return status;
298 }
299 
300 /**
301  * cdns_i2c_mrecv - Prepare and start a master receive operation
302  * @id:		pointer to the i2c device structure
303  */
304 static void cdns_i2c_mrecv(struct cdns_i2c *id)
305 {
306 	unsigned int ctrl_reg;
307 	unsigned int isr_status;
308 
309 	id->p_recv_buf = id->p_msg->buf;
310 	id->recv_count = id->p_msg->len;
311 
312 	/* Put the controller in master receive mode and clear the FIFO */
313 	ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
314 	ctrl_reg |= CDNS_I2C_CR_RW | CDNS_I2C_CR_CLR_FIFO;
315 
316 	if (id->p_msg->flags & I2C_M_RECV_LEN)
317 		id->recv_count = I2C_SMBUS_BLOCK_MAX + 1;
318 
319 	/*
320 	 * Check for the message size against FIFO depth and set the
321 	 * 'hold bus' bit if it is greater than FIFO depth.
322 	 */
323 	if (id->recv_count > CDNS_I2C_FIFO_DEPTH)
324 		ctrl_reg |= CDNS_I2C_CR_HOLD;
325 
326 	cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
327 
328 	/* Clear the interrupts in interrupt status register */
329 	isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
330 	cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
331 
332 	/*
333 	 * The no. of bytes to receive is checked against the limit of
334 	 * max transfer size. Set transfer size register with no of bytes
335 	 * receive if it is less than transfer size and transfer size if
336 	 * it is more. Enable the interrupts.
337 	 */
338 	if (id->recv_count > CDNS_I2C_TRANSFER_SIZE)
339 		cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE,
340 				  CDNS_I2C_XFER_SIZE_OFFSET);
341 	else
342 		cdns_i2c_writereg(id->recv_count, CDNS_I2C_XFER_SIZE_OFFSET);
343 	/* Clear the bus hold flag if bytes to receive is less than FIFO size */
344 	if (!id->bus_hold_flag &&
345 		((id->p_msg->flags & I2C_M_RECV_LEN) != I2C_M_RECV_LEN) &&
346 		(id->recv_count <= CDNS_I2C_FIFO_DEPTH))
347 			cdns_i2c_clear_bus_hold(id);
348 	/* Set the slave address in address register - triggers operation */
349 	cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK,
350 						CDNS_I2C_ADDR_OFFSET);
351 	cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET);
352 }
353 
354 /**
355  * cdns_i2c_msend - Prepare and start a master send operation
356  * @id:		pointer to the i2c device
357  */
358 static void cdns_i2c_msend(struct cdns_i2c *id)
359 {
360 	unsigned int avail_bytes;
361 	unsigned int bytes_to_send;
362 	unsigned int ctrl_reg;
363 	unsigned int isr_status;
364 
365 	id->p_recv_buf = NULL;
366 	id->p_send_buf = id->p_msg->buf;
367 	id->send_count = id->p_msg->len;
368 
369 	/* Set the controller in Master transmit mode and clear the FIFO. */
370 	ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
371 	ctrl_reg &= ~CDNS_I2C_CR_RW;
372 	ctrl_reg |= CDNS_I2C_CR_CLR_FIFO;
373 
374 	/*
375 	 * Check for the message size against FIFO depth and set the
376 	 * 'hold bus' bit if it is greater than FIFO depth.
377 	 */
378 	if (id->send_count > CDNS_I2C_FIFO_DEPTH)
379 		ctrl_reg |= CDNS_I2C_CR_HOLD;
380 	cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
381 
382 	/* Clear the interrupts in interrupt status register. */
383 	isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
384 	cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
385 
386 	/*
387 	 * Calculate the space available in FIFO. Check the message length
388 	 * against the space available, and fill the FIFO accordingly.
389 	 * Enable the interrupts.
390 	 */
391 	avail_bytes = CDNS_I2C_FIFO_DEPTH -
392 				cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
393 
394 	if (id->send_count > avail_bytes)
395 		bytes_to_send = avail_bytes;
396 	else
397 		bytes_to_send = id->send_count;
398 
399 	while (bytes_to_send--) {
400 		cdns_i2c_writereg((*(id->p_send_buf)++), CDNS_I2C_DATA_OFFSET);
401 		id->send_count--;
402 	}
403 
404 	/*
405 	 * Clear the bus hold flag if there is no more data
406 	 * and if it is the last message.
407 	 */
408 	if (!id->bus_hold_flag && !id->send_count)
409 		cdns_i2c_clear_bus_hold(id);
410 	/* Set the slave address in address register - triggers operation. */
411 	cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK,
412 						CDNS_I2C_ADDR_OFFSET);
413 
414 	cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET);
415 }
416 
417 /**
418  * cdns_i2c_master_reset - Reset the interface
419  * @adap:	pointer to the i2c adapter driver instance
420  *
421  * This function cleanup the fifos, clear the hold bit and status
422  * and disable the interrupts.
423  */
424 static void cdns_i2c_master_reset(struct i2c_adapter *adap)
425 {
426 	struct cdns_i2c *id = adap->algo_data;
427 	u32 regval;
428 
429 	/* Disable the interrupts */
430 	cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, CDNS_I2C_IDR_OFFSET);
431 	/* Clear the hold bit and fifos */
432 	regval = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
433 	regval &= ~CDNS_I2C_CR_HOLD;
434 	regval |= CDNS_I2C_CR_CLR_FIFO;
435 	cdns_i2c_writereg(regval, CDNS_I2C_CR_OFFSET);
436 	/* Update the transfercount register to zero */
437 	cdns_i2c_writereg(0, CDNS_I2C_XFER_SIZE_OFFSET);
438 	/* Clear the interupt status register */
439 	regval = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
440 	cdns_i2c_writereg(regval, CDNS_I2C_ISR_OFFSET);
441 	/* Clear the status register */
442 	regval = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET);
443 	cdns_i2c_writereg(regval, CDNS_I2C_SR_OFFSET);
444 }
445 
446 static int cdns_i2c_process_msg(struct cdns_i2c *id, struct i2c_msg *msg,
447 		struct i2c_adapter *adap)
448 {
449 	int ret;
450 	u32 reg;
451 
452 	id->p_msg = msg;
453 	id->err_status = 0;
454 	reinit_completion(&id->xfer_done);
455 
456 	/* Check for the TEN Bit mode on each msg */
457 	reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
458 	if (msg->flags & I2C_M_TEN) {
459 		if (reg & CDNS_I2C_CR_NEA)
460 			cdns_i2c_writereg(reg & ~CDNS_I2C_CR_NEA,
461 					CDNS_I2C_CR_OFFSET);
462 	} else {
463 		if (!(reg & CDNS_I2C_CR_NEA))
464 			cdns_i2c_writereg(reg | CDNS_I2C_CR_NEA,
465 					CDNS_I2C_CR_OFFSET);
466 	}
467 
468 	/* Check for the R/W flag on each msg */
469 	if (msg->flags & I2C_M_RD)
470 		cdns_i2c_mrecv(id);
471 	else
472 		cdns_i2c_msend(id);
473 
474 	/* Wait for the signal of completion */
475 	ret = wait_for_completion_timeout(&id->xfer_done, adap->timeout);
476 	if (!ret) {
477 		cdns_i2c_master_reset(adap);
478 		dev_err(id->adap.dev.parent,
479 				"timeout waiting on completion\n");
480 		return -ETIMEDOUT;
481 	}
482 
483 	cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK,
484 			  CDNS_I2C_IDR_OFFSET);
485 
486 	/* If it is bus arbitration error, try again */
487 	if (id->err_status & CDNS_I2C_IXR_ARB_LOST)
488 		return -EAGAIN;
489 
490 	return 0;
491 }
492 
493 /**
494  * cdns_i2c_master_xfer - The main i2c transfer function
495  * @adap:	pointer to the i2c adapter driver instance
496  * @msgs:	pointer to the i2c message structure
497  * @num:	the number of messages to transfer
498  *
499  * Initiates the send/recv activity based on the transfer message received.
500  *
501  * Return: number of msgs processed on success, negative error otherwise
502  */
503 static int cdns_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
504 				int num)
505 {
506 	int ret, count;
507 	u32 reg;
508 	struct cdns_i2c *id = adap->algo_data;
509 
510 	/* Check if the bus is free */
511 	if (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) & CDNS_I2C_SR_BA)
512 		return -EAGAIN;
513 
514 	/*
515 	 * Set the flag to one when multiple messages are to be
516 	 * processed with a repeated start.
517 	 */
518 	if (num > 1) {
519 		id->bus_hold_flag = 1;
520 		reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
521 		reg |= CDNS_I2C_CR_HOLD;
522 		cdns_i2c_writereg(reg, CDNS_I2C_CR_OFFSET);
523 	} else {
524 		id->bus_hold_flag = 0;
525 	}
526 
527 	/* Process the msg one by one */
528 	for (count = 0; count < num; count++, msgs++) {
529 		if (count == (num - 1))
530 			id->bus_hold_flag = 0;
531 
532 		ret = cdns_i2c_process_msg(id, msgs, adap);
533 		if (ret)
534 			return ret;
535 
536 		/* Report the other error interrupts to application */
537 		if (id->err_status) {
538 			cdns_i2c_master_reset(adap);
539 
540 			if (id->err_status & CDNS_I2C_IXR_NACK)
541 				return -ENXIO;
542 
543 			return -EIO;
544 		}
545 	}
546 
547 	return num;
548 }
549 
550 /**
551  * cdns_i2c_func - Returns the supported features of the I2C driver
552  * @adap:	pointer to the i2c adapter structure
553  *
554  * Return: 32 bit value, each bit corresponding to a feature
555  */
556 static u32 cdns_i2c_func(struct i2c_adapter *adap)
557 {
558 	return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR |
559 		(I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
560 		I2C_FUNC_SMBUS_BLOCK_DATA;
561 }
562 
563 static const struct i2c_algorithm cdns_i2c_algo = {
564 	.master_xfer	= cdns_i2c_master_xfer,
565 	.functionality	= cdns_i2c_func,
566 };
567 
568 /**
569  * cdns_i2c_calc_divs - Calculate clock dividers
570  * @f:		I2C clock frequency
571  * @input_clk:	Input clock frequency
572  * @a:		First divider (return value)
573  * @b:		Second divider (return value)
574  *
575  * f is used as input and output variable. As input it is used as target I2C
576  * frequency. On function exit f holds the actually resulting I2C frequency.
577  *
578  * Return: 0 on success, negative errno otherwise.
579  */
580 static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk,
581 		unsigned int *a, unsigned int *b)
582 {
583 	unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp;
584 	unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0;
585 	unsigned int last_error, current_error;
586 
587 	/* calculate (divisor_a+1) x (divisor_b+1) */
588 	temp = input_clk / (22 * fscl);
589 
590 	/*
591 	 * If the calculated value is negative or 0, the fscl input is out of
592 	 * range. Return error.
593 	 */
594 	if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX)))
595 		return -EINVAL;
596 
597 	last_error = -1;
598 	for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) {
599 		div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1));
600 
601 		if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX))
602 			continue;
603 		div_b--;
604 
605 		actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1));
606 
607 		if (actual_fscl > fscl)
608 			continue;
609 
610 		current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) :
611 							(fscl - actual_fscl));
612 
613 		if (last_error > current_error) {
614 			calc_div_a = div_a;
615 			calc_div_b = div_b;
616 			best_fscl = actual_fscl;
617 			last_error = current_error;
618 		}
619 	}
620 
621 	*a = calc_div_a;
622 	*b = calc_div_b;
623 	*f = best_fscl;
624 
625 	return 0;
626 }
627 
628 /**
629  * cdns_i2c_setclk - This function sets the serial clock rate for the I2C device
630  * @clk_in:	I2C clock input frequency in Hz
631  * @id:		Pointer to the I2C device structure
632  *
633  * The device must be idle rather than busy transferring data before setting
634  * these device options.
635  * The data rate is set by values in the control register.
636  * The formula for determining the correct register values is
637  *	Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1))
638  * See the hardware data sheet for a full explanation of setting the serial
639  * clock rate. The clock can not be faster than the input clock divide by 22.
640  * The two most common clock rates are 100KHz and 400KHz.
641  *
642  * Return: 0 on success, negative error otherwise
643  */
644 static int cdns_i2c_setclk(unsigned long clk_in, struct cdns_i2c *id)
645 {
646 	unsigned int div_a, div_b;
647 	unsigned int ctrl_reg;
648 	int ret = 0;
649 	unsigned long fscl = id->i2c_clk;
650 
651 	ret = cdns_i2c_calc_divs(&fscl, clk_in, &div_a, &div_b);
652 	if (ret)
653 		return ret;
654 
655 	ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
656 	ctrl_reg &= ~(CDNS_I2C_CR_DIVA_MASK | CDNS_I2C_CR_DIVB_MASK);
657 	ctrl_reg |= ((div_a << CDNS_I2C_CR_DIVA_SHIFT) |
658 			(div_b << CDNS_I2C_CR_DIVB_SHIFT));
659 	cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
660 
661 	return 0;
662 }
663 
664 /**
665  * cdns_i2c_clk_notifier_cb - Clock rate change callback
666  * @nb:		Pointer to notifier block
667  * @event:	Notification reason
668  * @data:	Pointer to notification data object
669  *
670  * This function is called when the cdns_i2c input clock frequency changes.
671  * The callback checks whether a valid bus frequency can be generated after the
672  * change. If so, the change is acknowledged, otherwise the change is aborted.
673  * New dividers are written to the HW in the pre- or post change notification
674  * depending on the scaling direction.
675  *
676  * Return:	NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK
677  *		to acknowedge the change, NOTIFY_DONE if the notification is
678  *		considered irrelevant.
679  */
680 static int cdns_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long
681 		event, void *data)
682 {
683 	struct clk_notifier_data *ndata = data;
684 	struct cdns_i2c *id = to_cdns_i2c(nb);
685 
686 	if (id->suspended)
687 		return NOTIFY_OK;
688 
689 	switch (event) {
690 	case PRE_RATE_CHANGE:
691 	{
692 		unsigned long input_clk = ndata->new_rate;
693 		unsigned long fscl = id->i2c_clk;
694 		unsigned int div_a, div_b;
695 		int ret;
696 
697 		ret = cdns_i2c_calc_divs(&fscl, input_clk, &div_a, &div_b);
698 		if (ret) {
699 			dev_warn(id->adap.dev.parent,
700 					"clock rate change rejected\n");
701 			return NOTIFY_STOP;
702 		}
703 
704 		/* scale up */
705 		if (ndata->new_rate > ndata->old_rate)
706 			cdns_i2c_setclk(ndata->new_rate, id);
707 
708 		return NOTIFY_OK;
709 	}
710 	case POST_RATE_CHANGE:
711 		id->input_clk = ndata->new_rate;
712 		/* scale down */
713 		if (ndata->new_rate < ndata->old_rate)
714 			cdns_i2c_setclk(ndata->new_rate, id);
715 		return NOTIFY_OK;
716 	case ABORT_RATE_CHANGE:
717 		/* scale up */
718 		if (ndata->new_rate > ndata->old_rate)
719 			cdns_i2c_setclk(ndata->old_rate, id);
720 		return NOTIFY_OK;
721 	default:
722 		return NOTIFY_DONE;
723 	}
724 }
725 
726 /**
727  * cdns_i2c_suspend - Suspend method for the driver
728  * @_dev:	Address of the platform_device structure
729  *
730  * Put the driver into low power mode.
731  *
732  * Return: 0 always
733  */
734 static int __maybe_unused cdns_i2c_suspend(struct device *_dev)
735 {
736 	struct platform_device *pdev = container_of(_dev,
737 			struct platform_device, dev);
738 	struct cdns_i2c *xi2c = platform_get_drvdata(pdev);
739 
740 	clk_disable(xi2c->clk);
741 	xi2c->suspended = 1;
742 
743 	return 0;
744 }
745 
746 /**
747  * cdns_i2c_resume - Resume from suspend
748  * @_dev:	Address of the platform_device structure
749  *
750  * Resume operation after suspend.
751  *
752  * Return: 0 on success and error value on error
753  */
754 static int __maybe_unused cdns_i2c_resume(struct device *_dev)
755 {
756 	struct platform_device *pdev = container_of(_dev,
757 			struct platform_device, dev);
758 	struct cdns_i2c *xi2c = platform_get_drvdata(pdev);
759 	int ret;
760 
761 	ret = clk_enable(xi2c->clk);
762 	if (ret) {
763 		dev_err(_dev, "Cannot enable clock.\n");
764 		return ret;
765 	}
766 
767 	xi2c->suspended = 0;
768 
769 	return 0;
770 }
771 
772 static SIMPLE_DEV_PM_OPS(cdns_i2c_dev_pm_ops, cdns_i2c_suspend,
773 			 cdns_i2c_resume);
774 
775 /**
776  * cdns_i2c_probe - Platform registration call
777  * @pdev:	Handle to the platform device structure
778  *
779  * This function does all the memory allocation and registration for the i2c
780  * device. User can modify the address mode to 10 bit address mode using the
781  * ioctl call with option I2C_TENBIT.
782  *
783  * Return: 0 on success, negative error otherwise
784  */
785 static int cdns_i2c_probe(struct platform_device *pdev)
786 {
787 	struct resource *r_mem;
788 	struct cdns_i2c *id;
789 	int ret;
790 
791 	id = devm_kzalloc(&pdev->dev, sizeof(*id), GFP_KERNEL);
792 	if (!id)
793 		return -ENOMEM;
794 
795 	platform_set_drvdata(pdev, id);
796 
797 	r_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
798 	id->membase = devm_ioremap_resource(&pdev->dev, r_mem);
799 	if (IS_ERR(id->membase))
800 		return PTR_ERR(id->membase);
801 
802 	id->irq = platform_get_irq(pdev, 0);
803 
804 	id->adap.dev.of_node = pdev->dev.of_node;
805 	id->adap.algo = &cdns_i2c_algo;
806 	id->adap.timeout = CDNS_I2C_TIMEOUT;
807 	id->adap.retries = 3;		/* Default retry value. */
808 	id->adap.algo_data = id;
809 	id->adap.dev.parent = &pdev->dev;
810 	init_completion(&id->xfer_done);
811 	snprintf(id->adap.name, sizeof(id->adap.name),
812 		 "Cadence I2C at %08lx", (unsigned long)r_mem->start);
813 
814 	id->clk = devm_clk_get(&pdev->dev, NULL);
815 	if (IS_ERR(id->clk)) {
816 		dev_err(&pdev->dev, "input clock not found.\n");
817 		return PTR_ERR(id->clk);
818 	}
819 	ret = clk_prepare_enable(id->clk);
820 	if (ret) {
821 		dev_err(&pdev->dev, "Unable to enable clock.\n");
822 		return ret;
823 	}
824 	id->clk_rate_change_nb.notifier_call = cdns_i2c_clk_notifier_cb;
825 	if (clk_notifier_register(id->clk, &id->clk_rate_change_nb))
826 		dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
827 	id->input_clk = clk_get_rate(id->clk);
828 
829 	ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
830 			&id->i2c_clk);
831 	if (ret || (id->i2c_clk > CDNS_I2C_SPEED_MAX))
832 		id->i2c_clk = CDNS_I2C_SPEED_DEFAULT;
833 
834 	cdns_i2c_writereg(CDNS_I2C_CR_ACK_EN | CDNS_I2C_CR_NEA | CDNS_I2C_CR_MS,
835 			  CDNS_I2C_CR_OFFSET);
836 
837 	ret = cdns_i2c_setclk(id->input_clk, id);
838 	if (ret) {
839 		dev_err(&pdev->dev, "invalid SCL clock: %u Hz\n", id->i2c_clk);
840 		ret = -EINVAL;
841 		goto err_clk_dis;
842 	}
843 
844 	ret = devm_request_irq(&pdev->dev, id->irq, cdns_i2c_isr, 0,
845 				 DRIVER_NAME, id);
846 	if (ret) {
847 		dev_err(&pdev->dev, "cannot get irq %d\n", id->irq);
848 		goto err_clk_dis;
849 	}
850 
851 	ret = i2c_add_adapter(&id->adap);
852 	if (ret < 0) {
853 		dev_err(&pdev->dev, "reg adap failed: %d\n", ret);
854 		goto err_clk_dis;
855 	}
856 
857 	/*
858 	 * Cadence I2C controller has a bug wherein it generates
859 	 * invalid read transaction after HW timeout in master receiver mode.
860 	 * HW timeout is not used by this driver and the interrupt is disabled.
861 	 * But the feature itself cannot be disabled. Hence maximum value
862 	 * is written to this register to reduce the chances of error.
863 	 */
864 	cdns_i2c_writereg(CDNS_I2C_TIMEOUT_MAX, CDNS_I2C_TIME_OUT_OFFSET);
865 
866 	dev_info(&pdev->dev, "%u kHz mmio %08lx irq %d\n",
867 		 id->i2c_clk / 1000, (unsigned long)r_mem->start, id->irq);
868 
869 	return 0;
870 
871 err_clk_dis:
872 	clk_disable_unprepare(id->clk);
873 	return ret;
874 }
875 
876 /**
877  * cdns_i2c_remove - Unregister the device after releasing the resources
878  * @pdev:	Handle to the platform device structure
879  *
880  * This function frees all the resources allocated to the device.
881  *
882  * Return: 0 always
883  */
884 static int cdns_i2c_remove(struct platform_device *pdev)
885 {
886 	struct cdns_i2c *id = platform_get_drvdata(pdev);
887 
888 	i2c_del_adapter(&id->adap);
889 	clk_notifier_unregister(id->clk, &id->clk_rate_change_nb);
890 	clk_disable_unprepare(id->clk);
891 
892 	return 0;
893 }
894 
895 static const struct of_device_id cdns_i2c_of_match[] = {
896 	{ .compatible = "cdns,i2c-r1p10", },
897 	{ /* end of table */ }
898 };
899 MODULE_DEVICE_TABLE(of, cdns_i2c_of_match);
900 
901 static struct platform_driver cdns_i2c_drv = {
902 	.driver = {
903 		.name  = DRIVER_NAME,
904 		.of_match_table = cdns_i2c_of_match,
905 		.pm = &cdns_i2c_dev_pm_ops,
906 	},
907 	.probe  = cdns_i2c_probe,
908 	.remove = cdns_i2c_remove,
909 };
910 
911 module_platform_driver(cdns_i2c_drv);
912 
913 MODULE_AUTHOR("Xilinx Inc.");
914 MODULE_DESCRIPTION("Cadence I2C bus driver");
915 MODULE_LICENSE("GPL");
916